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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / arch / arm / boot / dts / asr1806-p301.dts
blob: 6f346550f9dbb83ea0ee86b3c3c0557e75a3d54b [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics Co., Ltd.
4 */
5
6/dts-v1/;
7#include "asr1806.dtsi"
8
9/ {
10 model = "ASR 1806(FALCON-T) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usbphy: usbphy@d4207000 {
31 status = "okay";
32 };
33#ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */
34 usb: usb@c0000000 {
35 dr_mode = "otg";
36 pinctrl-names = "default","sleep";
37 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
38 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
39 usbid_gpio = <99>;
40 edge_detect_gpio = <99>;
41 otg,use-gpio-vbus;
42 gpio-num = <122>;
43 status = "okay";
44 };
45#else
46 usb: usb@c0000000 {
47 status = "okay";
48 };
49#endif
50
51 eth0: asr-eth@0xd4281800 {
52 compatible = "asr,asr-eth";
53 pinctrl-names = "default", "rgmii-pins";
54 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
55 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
56 reg = <0xd4281800 0x200>;
57 interrupts = <10 11>;
58 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
59 clocks = <&soc_clocks ASR1803_CLK_EMAC
60 &soc_clocks ASR1803_CLK_EMAC_PTP>;
61 clock-names = "emac-clk", "ptp-clk";
62 ptp-support;
63 ptp-clk-rate = <100000000>;
64 status = "okay";
65
66 reset-gpio = <&gpio 23 0>;
67 reset-active-low;
68 reset-delays-us = <0 100000 100000>;
69
70 ldo-gpio = <&gpio 40 0>;
71 ldo-active-low;
72 ldo-delays-us = <0 100000 100000>;
73 flow-control-threshold = <60 90>;
74 clk-tuning-enable;
75 /* clk-config(32bit)
76 *
77 * clk_sel(clk-config[23:16])
78 * RGMII:
79 * tx | clk_sel: 0 - from external RX clock
80 * 1 - from inverted external RX clock
81 * rx | clk_sel: 0 - from external RX clock
82 * 1 - from inverted external RX clock
83 *
84 * RMII:
85 * tx | clk_sel: 0 - RMII clock
86 * 1 - Inverted RMII clock
87 * rx | clk_sel: 0 - RMII clock
88 * 1 - Inverted RMII clock
89 *
90 */
91#if 0
92 /* enable 1000M phy*/
93 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
94 phy-handle = <&phy0>;
95#else
96 /* enable 100M phy*/
97 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
98 phy-handle = <&phy3>;
99#endif
100 /* enable fix link for ethernet switch */
101 /*
102 fixed-link {
103 speed = <100>;
104 full-duplex;
105 phy-mode = "rmii";
106 };
107 */
108
109 mdio: mdio-bus {
110 #address-cells = <0x1>;
111 #size-cells = <0x0>;
112 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
113 phy0: phy@0 {
114 compatible = "ethernet-phy-ieee802.3-c22";
115 device_type = "ethernet-phy";
116 reg = <0x0>; /* set phy address*/
117 phy-mode = "rgmii";
118 tx_rx_delay = <0xb 0x0>; /* 150ps per step*/
119 };
120
121 /* YT8512B 10M/100M 3.3V RMII PHY */
122 phy3: phy@3 {
123 compatible = "ethernet-phy-ieee802.3-c22";
124 device_type = "ethernet-phy";
125 reg = <0x3>; /* set phy address*/
126 phy-mode = "rmii";
127 driver_strength = <0x3>;
128 };
129
130 /* IP175D 10M/100M 3.3V RMII SWITCH */
131 phy1: phy@1 {
132 compatible = "ethernet-phy-ieee802.3-c22";
133 device_type = "ethernet-phy";
134 reg = <0x1>; /* set phy address*/
135 phy-mode = "rmii";
136 };
137 };
138 };
139 qspi: spi@0xd420b000 {
140 asr,qspi-freq = <78000000>;
141 status = "okay";
142 };
143 /* SD card */
144 sdh0: sdh@d4280000 {
145 pinctrl-names = "default", "slow", "fast", "sleep";
146 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
147 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
148 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
149 pinctrl-3 = <&sdh0_pmx_cd_wakeup>;
150 /*
151 * Genernal use, juse set vmmc-supply and vqmmc-supply
152 * vmmc-supply = <&supply1>
153 * vqmmc-supply = <&supply2>
154 *
155 * For compatibility, to select one from two supply source
156 * vmmc-supply = <&supply1 &supply1_backup>;
157 * vqmmc-supply = <&supply2 &supply2_backup>;
158 * vmmc2-supply = <&supply1_backup &supply1>;
159 * vqmmc2-supply = <&supply2_backup &supply2>;
160 */
161 vmmc-supply = <&vcc_sdh1>;
162 vqmmc-supply = <&pm802ldo6>;
163#ifndef CONFIG_ASR_DSDS
164 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
165 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
166#endif
167 bus-width = <4>;
168 no-mmc;
169 no-sdio;
170 /*non-removable;
171 broken-cd;*/
172 wp-inverted;
173 asr,sdh-pm-runtime-en;
174 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
175#if 1 /* CD via gpio */
176 cd-gpios = <&gpio 90 1>;
177 asr,sdh-quirks2 = <(
178 SDHCI_QUIRK2_SET_AIB_MMC |
179 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
180 )>;
181 asr,sdh-host-caps = <(
182 MMC_CAP_CD_WAKE
183 )>;
184 asr,sdh-quirks = <(
185 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
186 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
187 )>;
188#else /* CD via SDH */
189 asr,sdh-quirks = <(
190 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
191 )>;
192 asr,sdh-quirks2 = <(
193 SDHCI_QUIRK2_SET_AIB_MMC |
194 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
195 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
196 )>;
197#endif
198 /* prop "sdh-dtr-data":
199 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
200 asr,sdh-dtr-data =
201 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
202 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
203 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
204 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
205 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
206 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
207 status = "okay";
208 };
209
210 /* SDIO */
211 sdh1: sdh@d4280800 {
212 pinctrl-names = "default", "fast", "sleep";
213 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
214 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
215 pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
216 bus-width = <4>;
217 no-mmc;
218 no-sd;
219 non-removable;
220 keep-power-in-suspend;
221 enable-sdio-wakeup;
222 /* clk-scaling-config:
223 <up_threshold down_threshold polling_interval> */
224 clk-scaling-config = <25 12 200>;
225 min-ddr-qos = <156000 312000 400000>;
226 asr,sdh-pm-runtime-en;
227 asr,sdh-quirks = <(
228 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
229 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
230 )>;
231 asr,sdh-quirks2 = <(
232 SDHCI_QUIRK2_NO_TIMER_RETUNING |
233 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
234 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
235 )>;
236 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
237 asr,sdh-host-caps2 = <(
238 MMC_CAP2_ONLY_1_8V |
239 MMC_CAP2_DISABLE_PROBE_CDSCAN |
240 MMC_CAP2_CLK_SCALE |
241 MMC_CAP2_BUS_CLK_NO_SCALE
242 )>;
243 /* prop "sdh-dtr-data":
244 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
245 asr,sdh-dtr-data =
246 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
247 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
248 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
249 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
250 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
251 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
252 status = "okay";
253 };
254 pcie0: pcie@0xd4288000{
255 reset-gpios = <&gpio 42 0 >;
256 status = "okay";
257 };
258 pciephy0: pcie-phy@d4206000 {
259 status = "okay";
260 };
261 };
262
263 apb@d4000000 {
264 ssp_dai1: pxa-ssp-dai@1 {
265 compatible = "asr,pxa-ssp-dai";
266 reg = <0x1 0x0>;
267
268 port = <&ssp1>;
269 pinctrl-names = "default","ssp";
270 pinctrl-0 = <&i2s_gpio>;
271 pinctrl-1 = <&i2s_func>;
272 ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>;
273
274 dmas = <&pdma0 54 1
275 &pdma0 55 1>;
276 dma-names = "rx", "tx";
277
278 platform_driver_name = "pdma_platform";
279 burst_size = <4>;
280 playback_period_bytes = <2048>;
281 playback_buffer_bytes = <4096>;
282 capture_period_bytes = <2048>;
283 capture_buffer_bytes = <4096>;
284 };
285 mfpr: mfpr@d401e000 {
286 status = "okay";
287 /* intend to replace lpm-board-cfg
288 no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp"
289 pin1:pin1@d401e01B0 {
290 offset = <0x1B0>;
291 udr-cfg = <0xA040>;
292 };
293 pin2:pin2@d401e01B4 {
294 offset = <0x1B4>;
295 udr-cfg = <0xA040>;
296 };
297 */
298 };
299 timer0: timer@d4014000 {
300 status = "okay";
301 };
302 uart1: uart@d4017000 { /* nezhas evb use ap uart */
303 pinctrl-names = "default","sleep";
304 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
305 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
306 edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
307 status = "okay";
308 };
309 uart2: uart@d4036000 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>;
312 status = "okay";
313 };
314 uart3: uart@d4018000 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&uart3_pmx_func>;
317 status = "disabled";
318 };
319 uart4: uart@d401f000 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart4_pmx_func>;
322 status = "disabled";
323 };
324 rtc: rtc@d4010000 {
325 status = "okay";
326 };
327 pmx: pinmux@d401e000 {
328 /* pin base = base_addr / 4, nr pins & gpio function */
329 pinctrl-single,gpio-range = <
330 /*
331 * GPIO number is hardcoded for range at here.
332 * In gpio chip, GPIO number is not hardcoded for range.
333 * Since one gpio pin may be routed to multiple pins,
334 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
335 */
336 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
337 &range 55 32 0 /* GPIO0 ~ GPIO31 */
338 &range 87 32 0 /* GPIO32 ~ GPIO63 */
339 &range 119 32 0 /* GPIO64 ~ GPIO95 */
340 &range 151 32 0 /* GPIO96 ~ GPIO127 */
341 >;
342
343 ssp0_pmx_func: ssp0_pmx_func {
344 pinctrl-single,pins = <
345 GPIO36 AF1 /* TXD */
346 GPIO35 AF1 /* RXD */
347 GPIO34 AF1 /* FRM */
348 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
349 GPIO33 AF1 /* SCLK */
350 >;
351 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
352 };
353 lcd_bl_func: lcd_bl_func {
354 pinctrl-single,pins = <
355 VCXO_OUT AF1 /* GPIO126, lcd bl */
356 GPIO24 AF0 /* reset */
357 GPIO22 AF0 /* lcd d/c */
358 >;
359 MFP_DEFAULT;
360 };
361 uart1_pmx_func1: uart1_pmx_func1 {
362 pinctrl-single,pins = <
363 GPIO29 AF1
364 >;
365 MFP_DEFAULT;
366 };
367 uart1_pmx_func2: uart1_pmx_func2 {
368 pinctrl-single,pins = <
369 GPIO30 AF1
370 >;
371 MFP_DEFAULT;
372 };
373 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
374 pinctrl-single,pins = <
375 GPIO29 AF1
376 >;
377 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
378 };
379 twsi0_pmx_func: twsi0_pmx_func {
380 pinctrl-single,pins = <
381 GPIO49 AF1
382 GPIO50 AF1
383 >;
384 MFP_LPM_FLOAT;
385 };
386 twsi0_pmx_gpio: twsi0_pmx_gpio {
387 pinctrl-single,pins = <
388 GPIO49 AF0
389 GPIO50 AF0
390 >;
391 MFP_LPM_FLOAT;
392 };
393#if 0
394 twsi1_pmx_func: twsi1_pmx_func {
395 pinctrl-single,pins = <
396 GPIO10 AF1
397 GPIO11 AF1
398 >;
399 MFP_LPM_FLOAT;
400 };
401 twsi1_pmx_gpio: twsi1_pmx_gpio {
402 pinctrl-single,pins = <
403 GPIO10 AF0
404 GPIO11 AF0
405 >;
406 MFP_LPM_FLOAT;
407 };
408#endif
409 /* no pull, no LPM */
410 dvc_pmx_func: dvc_pmx_func {
411 /* hw-dvc */
412 pinctrl-single,pins = <
413 TDS_DIO0 AF0
414 TDS_DIO1 AF0
415 >;
416 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
417 };
418 leds_pmx_func: leds_pmx_func {
419 pinctrl-single,pins = <
420 DF_IO10 AF1
421 DF_IO11 AF1
422 DF_IO12 AF1
423 >;
424 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
425 };
426
427 gps_pmx_onoff: gps_pmx_onoff {
428 pinctrl-single,pins = <
429 TDS_TXREV AF1
430 >;
431 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
432 };
433 gps_pmx_reset: gps_pmx_reset {
434 pinctrl-single,pins = <
435 TDS_RXON AF1
436 >;
437 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
438 };
439 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
440 /* gps dedicated uart */
441 pinctrl-single,pins = <
442 GPIO51 AF1
443 GPIO32 AF1
444 >;
445 MFP_DEFAULT;
446 };
447 gps_pmx_uart_txd: gps_pmx_uart_txd {
448 /* gps dedicated uart */
449 pinctrl-single,pins = <
450 GPIO52 AF1
451 GPIO31 AF1
452 >;
453 MFP_DEFAULT;
454 };
455 uart3_pmx_func: uart3_pmx_func {
456 pinctrl-single,pins = <
457 GPIO53 AF1 /* RX */
458 GPIO54 AF1 /* TX */
459 >;
460 MFP_DEFAULT;
461 };
462 uart4_pmx_func: uart4_pmx_func {
463 pinctrl-single,pins = <
464 GPIO44 AF1 /* RX */
465 GPIO45 AF1 /* TX */
466 >;
467 MFP_DEFAULT;
468 };
469 panel_rst_func: panel_rst_func {
470 pinctrl-single,pins = <
471 DF_nCS1 AF1
472 >;
473 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
474 };
475
476 sd_ldo_en: sd_ldo_en {
477 pinctrl-single,pins = <
478 GPIO45 AF0
479 >;
480 MFP_PULL_DOWN;
481 };
482 sdh0_pmx_func1: sdh0_pmx_func1 {
483 pinctrl-single,pins = <
484 MMC1_DAT3 AF0
485 MMC1_DAT2 AF0
486 MMC1_DAT1 AF0
487 MMC1_DAT0 AF0
488 MMC1_CMD AF0
489 >;
490 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
491 };
492 sdh0_pmx_func2: sdh0_pmx_func2 {
493 pinctrl-single,pins = <
494 MMC1_CLK AF0
495 >;
496 DS_MEDIUM;PULL_NONE;EDGE_NONE;
497 };
498 sdh0_pmx_func3: sdh0_pmx_func3 {
499 pinctrl-single,pins = <
500 MMC1_CD AF1
501 >;
502 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
503 };
504 sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup {
505 pinctrl-single,pins = <
506 MMC1_CD AF1
507 >;
508 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
509 };
510 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
511 pinctrl-single,pins = <
512 MMC1_DAT3 AF0
513 MMC1_DAT2 AF0
514 MMC1_DAT1 AF0
515 MMC1_DAT0 AF0
516 MMC1_CMD AF0
517 >;
518 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
519 };
520 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
521 pinctrl-single,pins = <
522 MMC1_CLK AF0
523 >;
524 DS_FAST0;PULL_NONE;EDGE_NONE;
525 };
526 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
527 pinctrl-single,pins = <
528 MMC1_DAT3 AF0
529 MMC1_DAT2 AF0
530 MMC1_DAT1 AF0
531 MMC1_DAT0 AF0
532 MMC1_CMD AF0
533 >;
534 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
535 };
536 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
537 pinctrl-single,pins = <
538 MMC1_CLK AF0
539 >;
540 DS_FAST1;PULL_NONE;EDGE_NONE;
541 };
542 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
543 pinctrl-single,pins = <
544 TDS_DIO13 AF0 /* WLAN_DAT3 */
545 TDS_DIO14 AF0 /* WLAN_DAT2 */
546 TDS_DIO15 AF0 /* WLAN_DAT1 */
547 TDS_DIO16 AF0 /* WLAN_DAT0 */
548 TDS_DIO17 AF0 /* WLAN_CMD */
549 >;
550 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
551 };
552 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
553 pinctrl-single,pins = <
554 TDS_DIO18 AF0 /* WLAN_CLK */
555 >;
556 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
557 };
558 sdh1_pmx_func1: sdh1_pmx_func1 {
559 pinctrl-single,pins = <
560 TDS_DIO13 AF0 /* WLAN_DAT3 */
561 TDS_DIO14 AF0 /* WLAN_DAT2 */
562 TDS_DIO15 AF0 /* WLAN_DAT1 */
563 TDS_DIO16 AF0 /* WLAN_DAT0 */
564 TDS_DIO17 AF0 /* WLAN_CMD */
565 >;
566 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
567 };
568 sdh1_pmx_func2: sdh1_pmx_func2 {
569 pinctrl-single,pins = <
570 TDS_DIO18 AF0 /* WLAN_CLK */
571 >;
572 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
573 };
574 sdh1_pmx_func3: sdh1_pmx_func3 {
575 pinctrl-single,pins = <
576 GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
577 >;
578 MFP_PULL_DOWN;
579 };
580 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
581 pinctrl-single,pins = <
582 GPIO10 AF0 /* VCXO_REQ AF1 */
583 >;
584 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
585 };
586 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
587 pinctrl-single,pins = <
588 GPIO11 AF0 /* GPIO31 AF0 WLAN_PDn */
589 GPIO08 AF0 /* GPIO32 AF0 LDO_EN */
590 >;
591 MFP_PULL_DOWN;
592 };
593 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
594 pinctrl-single,pins = <
595 GPIO11 AF0 /* GPIO31 AF0 WLAN_PDn */
596 GPIO08 AF0 /* GPIO32 AF0 LDO_EN */
597 >;
598 MFP_PULL_UP;
599 };
600 alc5616_pmx_func1: alc5616_pmx_func1 {
601 pinctrl-single,pins = <
602 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
603 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
604 >;
605 MFP_DEFAULT;
606 };
607 alc5616_pmx_func2: alc5616_pmx_func2 {
608 pinctrl-single,pins = <
609 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
610 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
611 >;
612 MFP_DEFAULT;
613 };
614 audio_pa_pmx_func: audio_pa_pmx_func {
615 pinctrl-single,pins = <
616 GPIO14 AF0 /* PA */
617 >;
618 MFP_DEFAULT;
619 };
620 ecall_pmx_func: ecall_pmx_func {
621 pinctrl-single,pins = <
622 GPIO08 AF0 /* auto mode ecall */
623 GPIO09 AF0 /* manual mode ecall */
624 >;
625 MFP_DEFAULT;
626 };
627 slic_pmx_func1: slic_pmx_func1 {
628 pinctrl-single,pins = <
629 GPIO20 AF0 /* SLIC_INT, GPIO20 */
630 VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */
631 >;
632 MFP_DEFAULT;
633 };
634 slic_pmx_func2: slic_pmx_func2 {
635 pinctrl-single,pins = <
636 GPIO21 AF0 /* SLIC_RESET, GPIO21 */
637 >;
638 MFP_DEFAULT;
639 };
640 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
641 pinctrl-single,pins = <
642 GPIO20 AF0 /* SLIC_INT, GPIO20 */
643 >;
644 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
645 };
646
647 otg_vbus_func: otg_vbus_func {
648 pinctrl-single,pins = <
649 VBUS_DRV AF1 /* GPIO[122] */
650 >;
651 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
652 };
653
654 emac_pmx_func0: emac_pmx_func0 {
655 pinctrl-single,pins = <
656 GPIO00 AF1 /* GMAC1_RX_DV */
657 GPIO01 AF1 /* GMAC1_RX_D0 */
658 GPIO02 AF1 /* GMAC1_RX_D1 */
659 GPIO03 AF1 /* GMAC1_RX_CLK */
660 /* GPIO04 AF1 GMAC1_RX_D2 */
661 /* GPIO05 AF1 GMAC1_RX_D3 */
662 GPIO06 AF1 /* GMAC1_TX_D0 */
663 GPIO07 AF1 /* GMAC1_TX_D1 */
664 /* GPIO12 AF1 GMAC1_TX_CLK */
665 /* GPIO13 AF1 GMAC1_TX_D2 */
666 /* GPIO14 AF1 GMAC1_TX_D3 */
667 GPIO15 AF1 /* GMAC1_TX_EN */
668 GPIO16 AF1 /* GMAC1_TX_MDC */
669 /* GPIO17 AF1 GMAC1_TX_MDIO */
670 >;
671 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
672 };
673 emac_pmx_func1: emac_pmx_func1 {
674 pinctrl-single,pins = <
675 GPIO04 AF1 /* GMAC1_RX_D2 */
676 GPIO05 AF1 /* GMAC1_RX_D3 */
677 GPIO12 AF1 /* GMAC1_TX_CLK */
678 GPIO13 AF1 /* GMAC1_TX_D2 */
679 GPIO14 AF1 /* GMAC1_TX_D3 */
680 >;
681 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
682 };
683 emac_pmx_func2: emac_pmx_func2 {
684 pinctrl-single,pins = <
685 GPIO17 AF1 /* GMAC1_TX_MDIO */
686 GPIO18 AF1 /* GMAC1_TX_INT_N */
687 >;
688 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
689 };
690 emac_pmx_func3: emac_pmx_func3 {
691 pinctrl-single,pins = <
692 GPIO23 AF0 /* RESET */
693 GPIO40 AF0 /* LDO_EN */
694 >;
695 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
696 };
697 usim1_pmx_func: usim1_pmx_func {
698 pinctrl-single,pins = <
699 GPIO19 AF0
700 >;
701 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
702 };
703 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
704 pinctrl-single,pins = <
705 GPIO19 AF0
706 >;
707 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
708 };
709 usim2_pmx_func: usim2_pmx_func {
710 pinctrl-single,pins = <
711 GPIO44 AF0
712 >;
713 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
714 };
715 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
716 pinctrl-single,pins = <
717 GPIO44 AF0
718 >;
719 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
720 };
721 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
722 pinctrl-single,pins = <
723 GPIO42 AF0 /* PERST_N */
724 GPIO24 AF0 /* DC_EN */
725 >;
726 MFP_PULL_DOWN;
727 };
728 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
729 pinctrl-single,pins = <
730 GPIO42 AF0 /* PERST_N */
731 GPIO24 AF0 /* DC_EN */
732 >;
733 MFP_PULL_UP;
734 };
735 gpiokey_pmx_func: gpiokey_pmx_func {
736 pinctrl-single,pins = <
737 GPIO09 AF0
738 >;
739 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
740 };
741 usb_id_pinmux: usb_id_pinmux {
742 pinctrl-single,pins = <
743 USB_ID AF1/* usbid-gpio99 */
744 >;
745 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
746 };
747 usb_id_pinmux_slp: usb_id_pinmux_slp {
748 pinctrl-single,pins = <
749 USB_ID AF1 /* usbid-gpio99 */
750 >;
751 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
752 };
753 usb_host_pinmux: usb_host_pinmux {
754 pinctrl-single,pins = <
755 VBUS_DRV AF1 /* gpio-122 */
756 >;
757 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
758 };
759 i2s_func: i2s_func {
760 pinctrl-single,pins = <
761 GPIO25 AF2
762 GPIO26 AF2
763 GPIO27 AF2
764 GPIO28 AF2
765 >;
766 MFP_DEFAULT;
767 };
768 i2s_gpio: i2s_gpio {
769 pinctrl-single,pins = <
770 GPIO25 AF0
771 GPIO26 AF0
772 GPIO27 AF0
773 GPIO28 AF0
774 >;
775 MFP_LPM_FLOAT;
776 };
777 };
778
779 ssp0: spi@d401b000 {
780 status = "okay";
781 pinctrl-names = "default";
782 pinctrl-0 = <&ssp0_pmx_func>;
783 asr,spi-inc-mode;
784#ifdef CONFIG_FB_SPI_LCD
785 /* this enhancemnet feature is not suitable for
786 3 line 9bits spi lcd. */
787 /* asr,ssp-enhancement; */
788
789 lcd: spidev@0 {
790 #address-cells = <1>;
791 #size-cells = <1>;
792 compatible = "spilcd";
793 pinctrl-names = "default";
794 pinctrl-0 = <&lcd_bl_func>;
795 reg = <0>;
796 /* ST7735: need to set spi-max-frequency to 26M
797 * ST7789V: can set spi-max-frequency to 52M
798 */
799 spi-max-frequency = <26000000>;
800 xres = <128>;
801 yres = <128>;
802 bits = <8>; /* 8: 4line, 9: 3line */
803 rst_gpio = <&gpio 24 0>;
804 bl_gpio = <&gpio 126 0>;
805 rs_gpio = <&gpio 22 0>;
806 /* if comment the following statement, it means
807 * the avdd is sit on the "always-on" ldo.
808 */
809 /* avdd-supply = <&LDO1>; */
810 };
811#else
812 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
813 slic: spidev@0{
814 #address-cells = <1>;
815 #size-cells = <1>;
816 compatible = "asr,slic";
817 reg = <0>;
818 spi-cpol;
819 spi-cpha;
820 spi-max-frequency = <6500000>;
821 };
822#endif
823 };
824 twsi0: i2c@d4011000 {
825 status= "okay";
826 alc5616@1b {
827 compatible = "asrmicro,alc5616";
828 reg = <0x1b>;
829 pinctrl-names = "default", "sleep";
830 pinctrl-0 = <&alc5616_pmx_func1>;
831 pinctrl-1 = <&alc5616_pmx_func2>;
832 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
833 clock-names = "i2s_sys_clk";
834#if 0
835 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
836 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
837#else
838 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
839#endif
840 };
841
842 /*
843 pmic4: 88pm805@38 {
844 compatible = "marvell,88pm805";
845 reg = <0x38>;
846 };
847 */
848 };
849 twsi1: i2c@d4010800 {
850#if 0
851 pinctrl-names = "default","gpio";
852 pinctrl-0 = <&twsi1_pmx_func>;
853 pinctrl-1 = <&twsi1_pmx_gpio>;
854 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
855#endif
856 status= "disabled";
857 nau8810@1a {
858 compatible = "marvell,nau8810";
859 reg = <0x1a>;
860 };
861 };
862 twsi2: i2c@d4037000 {
863 status = "okay";
864
865 pmic4: 88pm805@38 {
866 compatible = "marvell,88pm805";
867 reg = <0x38>;
868 };
869
870 pmic5: pm802@0 {
871 compatible = "asr,pm802";
872 reg = <0x00>;
873 interrupts = <4>;
874 interrupt-parent = <&intc>;
875 interrupt-controller;
876 #interrupt-cells = <1>;
877 chg_irq_from_exton;
878 scs-int-active-high;
879 battery {
880 compatible = "asr,pm802-bat";
881 status = "disabled";
882
883 online-gpadc = <1>;
884 temperature-gpadc = <1>;
885
886 hi-volt-online = <1150>; /* mV */
887 lo-volt-online = <20>; /* mV */
888 hi-volt-temp = <1150>; /* mV */
889 lo-volt-temp = <200>; /* mV */
890
891 sw-fg-use-ntc;
892 full-capacity = <2050>; /* mAh */
893 r1-resistor = <40>; /* mohm */
894 r2-resistor = <30>; /* mohm */
895 rs-resistor = <120>; /* mohm */
896 roff-resistor = <0>; /* mohm */
897 roff-initial-resistor = <0>; /* mohm */
898
899 times-in-zero-degree = <1>;
900 offset-in-zero-degree = <0>;
901
902 times-in-ten-degree = <2>;
903 offset-in-ten-degree = <100>;
904
905 power-off-threshold = <3350>; /* mV */
906 safe-power-off-threshold = <3200>; /* mV */
907
908 online-gp-bias-curr = <11>; /* uA */
909
910 soc-ramp-up-interval = <150>; /* s */
911 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
912 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
913 ntc-table-size = <88>;
914 stop-chg-for-vbatmeas;
915 /* -24C, -23C, ..., 62C, 63C */
916 ntc-table = <
917 89680 85130 80840 76790 72970 69360 65960 62740
918 59700 56830 54130 51530 49100 46800 44610 42550
919 40590 38730 36970 35300 33710 32210 30780 29420
920 28130 26910 25750 24640 23590 22580 21630 20720
921 19860 19030 18250 17500 16790 16110 15460 14840
922 14250 13690 13150 12640 12150 11680 11230 10800
923 10390 10000 9620 9270 8920 8590 8280 7980
924 7690 7410 7150 6890 6650 6410 6190 5970
925 5770 5570 5380 5190 5020 4850 4680 4530
926 4380 4230 4100 3960 3830 3710 3590 3480
927 3370 3260 3160 3060 2960 2870 2780 2700
928 >;
929 };
930 usb {
931 status = "disabled";
932 vbus_gpio = <0xff>; /* set_vbus */
933 id-gpadc = <0xff>; /* usb-id */
934 vchg-from-exton = <1>;
935 vbus-detect = <1>; /* vbus-irq */
936 get-vbus = <1>; /* get-vbus */
937 };
938 };
939 pmic6: pm803@30 {
940 compatible = "asr,pm803";
941 reg = <0x30>;
942 interrupts = <4>;
943 interrupt-parent = <&intc>;
944 interrupt-controller;
945 #interrupt-cells = <1>;
946 chg_irq_from_exton;
947 scs-int-active-high;
948 battery {
949 compatible = "asr,pm803-bat";
950 status = "disabled";
951
952 online-gpadc = <1>;
953 temperature-gpadc = <1>;
954
955 hi-volt-online = <1150>; /* mV */
956 lo-volt-online = <20>; /* mV */
957 hi-volt-temp = <1150>; /* mV */
958 lo-volt-temp = <200>; /* mV */
959
960 sw-fg-use-ntc;
961 full-capacity = <2050>; /* mAh */
962 r1-resistor = <40>; /* mohm */
963 r2-resistor = <30>; /* mohm */
964 rs-resistor = <120>; /* mohm */
965 roff-resistor = <0>; /* mohm */
966 roff-initial-resistor = <0>; /* mohm */
967
968 times-in-zero-degree = <1>;
969 offset-in-zero-degree = <0>;
970
971 times-in-ten-degree = <2>;
972 offset-in-ten-degree = <100>;
973
974 power-off-threshold = <3350>; /* mV */
975 safe-power-off-threshold = <3200>; /* mV */
976
977 online-gp-bias-curr = <11>; /* uA */
978
979 soc-ramp-up-interval = <150>; /* s */
980 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
981 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
982 ntc-table-size = <88>;
983 stop-chg-for-vbatmeas;
984 /* -24C, -23C, ..., 62C, 63C */
985 ntc-table = <
986 89680 85130 80840 76790 72970 69360 65960 62740
987 59700 56830 54130 51530 49100 46800 44610 42550
988 40590 38730 36970 35300 33710 32210 30780 29420
989 28130 26910 25750 24640 23590 22580 21630 20720
990 19860 19030 18250 17500 16790 16110 15460 14840
991 14250 13690 13150 12640 12150 11680 11230 10800
992 10390 10000 9620 9270 8920 8590 8280 7980
993 7690 7410 7150 6890 6650 6410 6190 5970
994 5770 5570 5380 5190 5020 4850 4680 4530
995 4380 4230 4100 3960 3830 3710 3590 3480
996 3370 3260 3160 3060 2960 2870 2780 2700
997 >;
998 };
999 usb {
1000 status = "disabled";
1001 vbus_gpio = <0xff>; /* set_vbus */
1002 id-gpadc = <0xff>; /* usb-id */
1003 vchg-from-exton = <1>;
1004 vbus-detect = <1>; /* vbus-irq */
1005 get-vbus = <1>; /* get-vbus */
1006 };
1007 };
1008 };
1009 };
1010 };
1011
1012 vcc_sdh1: sd-regulator {
1013 compatible = "regulator-fixed";
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&sd_ldo_en>;
1016 regulator-name = "SDH1 VCC";
1017 regulator-min-microvolt = <3300000>;
1018 regulator-max-microvolt = <3300000>;
1019 gpio = <&gpio 45 0>;
1020 enable-active-high;
1021 status = "okay";
1022 };
1023
1024 asr-rfkill {
1025 compatible = "asr,asr-rfkill";
1026 pinctrl-names = "off", "on";
1027 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
1028 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
1029 sd-host = <&sdh1>;
1030 pd-gpio = <&gpio 11 0>;
1031 3v3-ldo-gpio = <&gpio 8 0>;
1032 edge-wakeup-gpio = <&gpio 10 0>;
1033 status = "okay";
1034 };
1035
1036 pcie-rfkill {
1037 compatible = "mrvl,pcie-rfkill";
1038 pinctrl-names = "off", "on";
1039 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
1040 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
1041 rst-gpio = <&gpio 42 0>;
1042 3v3-ldo-gpio = <&gpio 24 0>;
1043 status = "okay";
1044 };
1045
1046 sound {
1047 compatible = "ASRMICRO,asrmicro-snd-card";
1048 ssp-controllers = <&ssp_dai1>;
1049 };
1050
1051 ecall {
1052 compatible = "asr,ecall-event";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&ecall_pmx_func>;
1055 gpio-auto-ecall = <8>;
1056 gpio-manual-ecall = <9>;
1057 status = "disabled";
1058 };
1059
1060 usim1: usim1 {
1061 compatible = "asr,usim1";
1062 pinctrl-names = "default", "sleep";
1063 pinctrl-0 = <&usim1_pmx_func>;
1064 pinctrl-1 = <&usim1_pmx_func_sleep>;
1065 edge_detect_gpio = <19>; /* GPIO19: SIM detect pin */
1066 status = "okay";
1067 };
1068 /* set okay for this node if usim2 is needed */
1069 usim2: usim2 {
1070 compatible = "asr,usim2";
1071 pinctrl-names = "default", "sleep";
1072 pinctrl-0 = <&usim2_pmx_func>;
1073 pinctrl-1 = <&usim2_pmx_func_sleep>;
1074 edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */
1075#ifdef CONFIG_ASR_DSDS
1076 status = "okay";
1077#else
1078 status = "disabled";
1079#endif
1080 };
1081 gpio_keys {
1082 compatible = "gpio-keys";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 /* autorepeat; */
1086 pinctrl-names = "default";
1087 pinctrl-0 = <&gpiokey_pmx_func>;
1088 button@1 {
1089 label = "qrcode-key";
1090 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
1091 /* NOTE:
1092 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
1093 * Customer SHOULD change it to any other gpios.
1094 * Because user may do the misoperation that
1095 * powerup with FDL key pressed,
1096 * then the borad will enter force download mode.
1097 */
1098 gpios = <&gpio 9 1>;
1099 gpio-key,wakeup;
1100 };
1101 };
1102
1103 audio_pa {
1104 compatible = "asrmicro,audio-pa";
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&audio_pa_pmx_func>;
1107 pa-gpio = <&gpio 14 0>;
1108 status = "okay";
1109 };
1110
1111 audio_regs {
1112 compatible = "ASRMICRO,audio-registers";
1113 reg = <0xD4050044 0x4>;
1114 status = "okay";
1115 };
1116
1117 nz3-slic {
1118 compatible = "asr,nz3-slic";
1119 pinctrl-names = "default", "sleep";
1120 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1121 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1122 rst-gpio = <&gpio 21 0>;
1123 edge-wakeup-gpio = <&gpio 20 0>;
1124 vdd-3v3-gpio = <&gpio 127 0>;
1125 status = "disabled";
1126 };
1127 microsemi-slic {
1128 compatible = "asr,microsemi-slic";
1129 pinctrl-names = "default", "sleep";
1130 pinctrl-0 = <&slic_pmx_func1>;
1131 pinctrl-1 = <&slic_pmx_func1_sleep>;
1132 edge-wakeup-gpio = <&gpio 20 0>;
1133 vdd-3v3-gpio = <&gpio 127 0>;
1134 status = "disabled";
1135 };
1136 maxlinear-slic {
1137 compatible = "asr,maxlinear-slic";
1138 pinctrl-names = "default", "sleep";
1139 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1140 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1141 rst-gpio = <&gpio 21 0>;
1142 edge-wakeup-gpio = <&gpio 20 0>;
1143 vdd-3v3-gpio = <&gpio 127 0>;
1144 status = "disabled";
1145 };
1146 /* deprecated, move to mfpr@d401e000
1147 lpm-board-cfg {
1148 compatible = "asr,lpm-board-cfg";
1149 wakeup-state-d1pp = <0x1>;
1150 udr-mfpr-config = <0x1B0 0xA040 0x0
1151 0x1B4 0xA040 0x0>;
1152 };
1153 */
1154};
1155#ifdef CONFIG_ASR_DSDS
1156#include "asr_pm802_2usim.dtsi"
1157#include "88pm805.dtsi"
1158#include "asr_pm803_2usim.dtsi"
1159#else
1160#include "asr_pm802.dtsi"
1161#include "88pm805.dtsi"
1162#include "asr_pm803.dtsi"
1163#endif
1164
1165#ifdef CONFIG_AB_SYSTEM
1166#include "asr1806_ab_flash_layout.dtsi"
1167#else
1168#include "asr1806_flash_layout.dtsi"
1169#endif