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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / arch / arm / boot / dts / qcom-ipq8064.dtsi
blob: 976a8a1fa953591ad92e73d9447d552cddf7d3c1 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm IPQ8064";
16 compatible = "qcom,ipq8064";
17 interrupt-parent = <&intc>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "qcom,krait";
25 enable-method = "qcom,kpss-acc-v1";
26 device_type = "cpu";
27 reg = <0>;
28 next-level-cache = <&L2>;
29 qcom,acc = <&acc0>;
30 qcom,saw = <&saw0>;
31 };
32
33 cpu@1 {
34 compatible = "qcom,krait";
35 enable-method = "qcom,kpss-acc-v1";
36 device_type = "cpu";
37 reg = <1>;
38 next-level-cache = <&L2>;
39 qcom,acc = <&acc1>;
40 qcom,saw = <&saw1>;
41 };
42
43 L2: l2-cache {
44 compatible = "cache";
45 cache-level = <2>;
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x0 0x0>;
52 };
53
54 cpu-pmu {
55 compatible = "qcom,krait-pmu";
56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
57 IRQ_TYPE_LEVEL_HIGH)>;
58 };
59
60 reserved-memory {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 nss@40000000 {
66 reg = <0x40000000 0x1000000>;
67 no-map;
68 };
69
70 smem@41000000 {
71 reg = <0x41000000 0x200000>;
72 no-map;
73 };
74 };
75
76 clocks {
77 cxo_board {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <25000000>;
81 };
82
83 pxo_board {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <25000000>;
87 };
88
89 sleep_clk: sleep_clk {
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 #clock-cells = <0>;
93 };
94 };
95
96 soc: soc {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100 compatible = "simple-bus";
101
102 lpass@28100000 {
103 compatible = "qcom,lpass-cpu";
104 status = "disabled";
105 clocks = <&lcc AHBIX_CLK>,
106 <&lcc MI2S_OSR_CLK>,
107 <&lcc MI2S_BIT_CLK>;
108 clock-names = "ahbix-clk",
109 "mi2s-osr-clk",
110 "mi2s-bit-clk";
111 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
112 interrupt-names = "lpass-irq-lpaif";
113 reg = <0x28100000 0x10000>;
114 reg-names = "lpass-lpaif";
115 };
116
117 qcom_pinmux: pinmux@800000 {
118 compatible = "qcom,ipq8064-pinctrl";
119 reg = <0x800000 0x4000>;
120
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
126
127 pcie0_pins: pcie0_pinmux {
128 mux {
129 pins = "gpio3";
130 function = "pcie1_rst";
131 drive-strength = <12>;
132 bias-disable;
133 };
134 };
135
136 pcie1_pins: pcie1_pinmux {
137 mux {
138 pins = "gpio48";
139 function = "pcie2_rst";
140 drive-strength = <12>;
141 bias-disable;
142 };
143 };
144
145 pcie2_pins: pcie2_pinmux {
146 mux {
147 pins = "gpio63";
148 function = "pcie3_rst";
149 drive-strength = <12>;
150 bias-disable;
151 };
152 };
153
154 spi_pins: spi_pins {
155 mux {
156 pins = "gpio18", "gpio19", "gpio21";
157 function = "gsbi5";
158 drive-strength = <10>;
159 bias-none;
160 };
161 };
162
163 leds_pins: leds_pins {
164 mux {
165 pins = "gpio7", "gpio8", "gpio9",
166 "gpio26", "gpio53";
167 function = "gpio";
168 drive-strength = <2>;
169 bias-pull-down;
170 output-low;
171 };
172 };
173
174 buttons_pins: buttons_pins {
175 mux {
176 pins = "gpio54";
177 drive-strength = <2>;
178 bias-pull-up;
179 };
180 };
181 };
182
183 intc: interrupt-controller@2000000 {
184 compatible = "qcom,msm-qgic2";
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 reg = <0x02000000 0x1000>,
188 <0x02002000 0x1000>;
189 };
190
191 timer@200a000 {
192 compatible = "qcom,kpss-timer",
193 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
194 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
195 IRQ_TYPE_EDGE_RISING)>,
196 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
197 IRQ_TYPE_EDGE_RISING)>,
198 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
199 IRQ_TYPE_EDGE_RISING)>,
200 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
201 IRQ_TYPE_EDGE_RISING)>,
202 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
203 IRQ_TYPE_EDGE_RISING)>;
204 reg = <0x0200a000 0x100>;
205 clock-frequency = <25000000>,
206 <32768>;
207 clocks = <&sleep_clk>;
208 clock-names = "sleep";
209 cpu-offset = <0x80000>;
210 };
211
212 acc0: clock-controller@2088000 {
213 compatible = "qcom,kpss-acc-v1";
214 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
215 };
216
217 acc1: clock-controller@2098000 {
218 compatible = "qcom,kpss-acc-v1";
219 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
220 };
221
222 saw0: regulator@2089000 {
223 compatible = "qcom,saw2";
224 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
225 regulator;
226 };
227
228 saw1: regulator@2099000 {
229 compatible = "qcom,saw2";
230 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
231 regulator;
232 };
233
234 gsbi2: gsbi@12480000 {
235 compatible = "qcom,gsbi-v1.0.0";
236 cell-index = <2>;
237 reg = <0x12480000 0x100>;
238 clocks = <&gcc GSBI2_H_CLK>;
239 clock-names = "iface";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges;
243 status = "disabled";
244
245 syscon-tcsr = <&tcsr>;
246
247 serial@12490000 {
248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
249 reg = <0x12490000 0x1000>,
250 <0x12480000 0x1000>;
251 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
253 clock-names = "core", "iface";
254 status = "disabled";
255 };
256
257 i2c@124a0000 {
258 compatible = "qcom,i2c-qup-v1.1.1";
259 reg = <0x124a0000 0x1000>;
260 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
261
262 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
263 clock-names = "core", "iface";
264 status = "disabled";
265
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
269
270 };
271
272 gsbi4: gsbi@16300000 {
273 compatible = "qcom,gsbi-v1.0.0";
274 cell-index = <4>;
275 reg = <0x16300000 0x100>;
276 clocks = <&gcc GSBI4_H_CLK>;
277 clock-names = "iface";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 ranges;
281 status = "disabled";
282
283 syscon-tcsr = <&tcsr>;
284
285 gsbi4_serial: serial@16340000 {
286 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
287 reg = <0x16340000 0x1000>,
288 <0x16300000 0x1000>;
289 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
291 clock-names = "core", "iface";
292 status = "disabled";
293 };
294
295 i2c@16380000 {
296 compatible = "qcom,i2c-qup-v1.1.1";
297 reg = <0x16380000 0x1000>;
298 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
299
300 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
301 clock-names = "core", "iface";
302 status = "disabled";
303
304 #address-cells = <1>;
305 #size-cells = <0>;
306 };
307 };
308
309 gsbi5: gsbi@1a200000 {
310 compatible = "qcom,gsbi-v1.0.0";
311 cell-index = <5>;
312 reg = <0x1a200000 0x100>;
313 clocks = <&gcc GSBI5_H_CLK>;
314 clock-names = "iface";
315 #address-cells = <1>;
316 #size-cells = <1>;
317 ranges;
318 status = "disabled";
319
320 syscon-tcsr = <&tcsr>;
321
322 serial@1a240000 {
323 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
324 reg = <0x1a240000 0x1000>,
325 <0x1a200000 0x1000>;
326 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
328 clock-names = "core", "iface";
329 status = "disabled";
330 };
331
332 i2c@1a280000 {
333 compatible = "qcom,i2c-qup-v1.1.1";
334 reg = <0x1a280000 0x1000>;
335 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
336
337 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
338 clock-names = "core", "iface";
339 status = "disabled";
340
341 #address-cells = <1>;
342 #size-cells = <0>;
343 };
344
345 spi@1a280000 {
346 compatible = "qcom,spi-qup-v1.1.1";
347 reg = <0x1a280000 0x1000>;
348 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
349
350 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
351 clock-names = "core", "iface";
352 status = "disabled";
353
354 #address-cells = <1>;
355 #size-cells = <0>;
356 };
357 };
358
359 gsbi7: gsbi@16600000 {
360 status = "disabled";
361 compatible = "qcom,gsbi-v1.0.0";
362 cell-index = <7>;
363 reg = <0x16600000 0x100>;
364 clocks = <&gcc GSBI7_H_CLK>;
365 clock-names = "iface";
366 #address-cells = <1>;
367 #size-cells = <1>;
368 ranges;
369 syscon-tcsr = <&tcsr>;
370
371 gsbi7_serial: serial@16640000 {
372 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
373 reg = <0x16640000 0x1000>,
374 <0x16600000 0x1000>;
375 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
377 clock-names = "core", "iface";
378 status = "disabled";
379 };
380 };
381
382 sata_phy: sata-phy@1b400000 {
383 compatible = "qcom,ipq806x-sata-phy";
384 reg = <0x1b400000 0x200>;
385
386 clocks = <&gcc SATA_PHY_CFG_CLK>;
387 clock-names = "cfg";
388
389 #phy-cells = <0>;
390 status = "disabled";
391 };
392
393 sata@29000000 {
394 compatible = "qcom,ipq806x-ahci", "generic-ahci";
395 reg = <0x29000000 0x180>;
396
397 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
398
399 clocks = <&gcc SFAB_SATA_S_H_CLK>,
400 <&gcc SATA_H_CLK>,
401 <&gcc SATA_A_CLK>,
402 <&gcc SATA_RXOOB_CLK>,
403 <&gcc SATA_PMALIVE_CLK>;
404 clock-names = "slave_face", "iface", "core",
405 "rxoob", "pmalive";
406
407 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
408 assigned-clock-rates = <100000000>, <100000000>;
409
410 phys = <&sata_phy>;
411 phy-names = "sata-phy";
412 status = "disabled";
413 };
414
415 qcom,ssbi@500000 {
416 compatible = "qcom,ssbi";
417 reg = <0x00500000 0x1000>;
418 qcom,controller-type = "pmic-arbiter";
419 };
420
421 gcc: clock-controller@900000 {
422 compatible = "qcom,gcc-ipq8064";
423 reg = <0x00900000 0x4000>;
424 #clock-cells = <1>;
425 #reset-cells = <1>;
426 };
427
428 tcsr: syscon@1a400000 {
429 compatible = "qcom,tcsr-ipq8064", "syscon";
430 reg = <0x1a400000 0x100>;
431 };
432
433 lcc: clock-controller@28000000 {
434 compatible = "qcom,lcc-ipq8064";
435 reg = <0x28000000 0x1000>;
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 };
439
440 pcie0: pci@1b500000 {
441 compatible = "qcom,pcie-ipq8064";
442 reg = <0x1b500000 0x1000
443 0x1b502000 0x80
444 0x1b600000 0x100
445 0x0ff00000 0x100000>;
446 reg-names = "dbi", "elbi", "parf", "config";
447 device_type = "pci";
448 linux,pci-domain = <0>;
449 bus-range = <0x00 0xff>;
450 num-lanes = <1>;
451 #address-cells = <3>;
452 #size-cells = <2>;
453
454 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
455 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
456
457 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "msi";
459 #interrupt-cells = <1>;
460 interrupt-map-mask = <0 0 0 0x7>;
461 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
462 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
463 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
464 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
465
466 clocks = <&gcc PCIE_A_CLK>,
467 <&gcc PCIE_H_CLK>,
468 <&gcc PCIE_PHY_CLK>,
469 <&gcc PCIE_AUX_CLK>,
470 <&gcc PCIE_ALT_REF_CLK>;
471 clock-names = "core", "iface", "phy", "aux", "ref";
472
473 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
474 assigned-clock-rates = <100000000>;
475
476 resets = <&gcc PCIE_ACLK_RESET>,
477 <&gcc PCIE_HCLK_RESET>,
478 <&gcc PCIE_POR_RESET>,
479 <&gcc PCIE_PCI_RESET>,
480 <&gcc PCIE_PHY_RESET>,
481 <&gcc PCIE_EXT_RESET>;
482 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
483
484 pinctrl-0 = <&pcie0_pins>;
485 pinctrl-names = "default";
486
487 status = "disabled";
488 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
489 };
490
491 pcie1: pci@1b700000 {
492 compatible = "qcom,pcie-ipq8064";
493 reg = <0x1b700000 0x1000
494 0x1b702000 0x80
495 0x1b800000 0x100
496 0x31f00000 0x100000>;
497 reg-names = "dbi", "elbi", "parf", "config";
498 device_type = "pci";
499 linux,pci-domain = <1>;
500 bus-range = <0x00 0xff>;
501 num-lanes = <1>;
502 #address-cells = <3>;
503 #size-cells = <2>;
504
505 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
506 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
507
508 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "msi";
510 #interrupt-cells = <1>;
511 interrupt-map-mask = <0 0 0 0x7>;
512 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
513 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
514 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
515 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
516
517 clocks = <&gcc PCIE_1_A_CLK>,
518 <&gcc PCIE_1_H_CLK>,
519 <&gcc PCIE_1_PHY_CLK>,
520 <&gcc PCIE_1_AUX_CLK>,
521 <&gcc PCIE_1_ALT_REF_CLK>;
522 clock-names = "core", "iface", "phy", "aux", "ref";
523
524 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
525 assigned-clock-rates = <100000000>;
526
527 resets = <&gcc PCIE_1_ACLK_RESET>,
528 <&gcc PCIE_1_HCLK_RESET>,
529 <&gcc PCIE_1_POR_RESET>,
530 <&gcc PCIE_1_PCI_RESET>,
531 <&gcc PCIE_1_PHY_RESET>,
532 <&gcc PCIE_1_EXT_RESET>;
533 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
534
535 pinctrl-0 = <&pcie1_pins>;
536 pinctrl-names = "default";
537
538 status = "disabled";
539 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
540 };
541
542 pcie2: pci@1b900000 {
543 compatible = "qcom,pcie-ipq8064";
544 reg = <0x1b900000 0x1000
545 0x1b902000 0x80
546 0x1ba00000 0x100
547 0x35f00000 0x100000>;
548 reg-names = "dbi", "elbi", "parf", "config";
549 device_type = "pci";
550 linux,pci-domain = <2>;
551 bus-range = <0x00 0xff>;
552 num-lanes = <1>;
553 #address-cells = <3>;
554 #size-cells = <2>;
555
556 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
557 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
558
559 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-names = "msi";
561 #interrupt-cells = <1>;
562 interrupt-map-mask = <0 0 0 0x7>;
563 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
564 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
565 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
566 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
567
568 clocks = <&gcc PCIE_2_A_CLK>,
569 <&gcc PCIE_2_H_CLK>,
570 <&gcc PCIE_2_PHY_CLK>,
571 <&gcc PCIE_2_AUX_CLK>,
572 <&gcc PCIE_2_ALT_REF_CLK>;
573 clock-names = "core", "iface", "phy", "aux", "ref";
574
575 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
576 assigned-clock-rates = <100000000>;
577
578 resets = <&gcc PCIE_2_ACLK_RESET>,
579 <&gcc PCIE_2_HCLK_RESET>,
580 <&gcc PCIE_2_POR_RESET>,
581 <&gcc PCIE_2_PCI_RESET>,
582 <&gcc PCIE_2_PHY_RESET>,
583 <&gcc PCIE_2_EXT_RESET>;
584 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
585
586 pinctrl-0 = <&pcie2_pins>;
587 pinctrl-names = "default";
588
589 status = "disabled";
590 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
591 };
592
593 vsdcc_fixed: vsdcc-regulator {
594 compatible = "regulator-fixed";
595 regulator-name = "SDCC Power";
596 regulator-min-microvolt = <3300000>;
597 regulator-max-microvolt = <3300000>;
598 regulator-always-on;
599 };
600
601 sdcc1bam:dma@12402000 {
602 compatible = "qcom,bam-v1.3.0";
603 reg = <0x12402000 0x8000>;
604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&gcc SDC1_H_CLK>;
606 clock-names = "bam_clk";
607 #dma-cells = <1>;
608 qcom,ee = <0>;
609 };
610
611 sdcc3bam:dma@12182000 {
612 compatible = "qcom,bam-v1.3.0";
613 reg = <0x12182000 0x8000>;
614 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&gcc SDC3_H_CLK>;
616 clock-names = "bam_clk";
617 #dma-cells = <1>;
618 qcom,ee = <0>;
619 };
620
621 amba {
622 compatible = "simple-bus";
623 #address-cells = <1>;
624 #size-cells = <1>;
625 ranges;
626
627 sdcc@12400000 {
628 status = "disabled";
629 compatible = "arm,pl18x", "arm,primecell";
630 arm,primecell-periphid = <0x00051180>;
631 reg = <0x12400000 0x2000>;
632 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "cmd_irq";
634 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
635 clock-names = "mclk", "apb_pclk";
636 bus-width = <8>;
637 max-frequency = <96000000>;
638 non-removable;
639 cap-sd-highspeed;
640 cap-mmc-highspeed;
641 mmc-ddr-1_8v;
642 vmmc-supply = <&vsdcc_fixed>;
643 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
644 dma-names = "tx", "rx";
645 };
646
647 sdcc@12180000 {
648 compatible = "arm,pl18x", "arm,primecell";
649 arm,primecell-periphid = <0x00051180>;
650 status = "disabled";
651 reg = <0x12180000 0x2000>;
652 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
653 interrupt-names = "cmd_irq";
654 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
655 clock-names = "mclk", "apb_pclk";
656 bus-width = <8>;
657 cap-sd-highspeed;
658 cap-mmc-highspeed;
659 max-frequency = <192000000>;
660 #mmc-ddr-1_8v;
661 sd-uhs-sdr104;
662 sd-uhs-ddr50;
663 vqmmc-supply = <&vsdcc_fixed>;
664 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
665 dma-names = "tx", "rx";
666 };
667 };
668 };
669};