| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (C) 2015 - ARM Ltd |
| 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ARM_KVM_HYP_H__ |
| 8 | #define __ARM_KVM_HYP_H__ |
| 9 | |
| 10 | #include <linux/compiler.h> |
| 11 | #include <linux/kvm_host.h> |
| 12 | #include <asm/cp15.h> |
| 13 | #include <asm/vfp.h> |
| 14 | |
| 15 | #define __hyp_text __section(.hyp.text) notrace |
| 16 | |
| 17 | #define write_special(v, r) \ |
| 18 | asm volatile("msr " __stringify(r) ", %0" : : "r" (v)) |
| 19 | #define read_special(r) ({ \ |
| 20 | u32 __val; \ |
| 21 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ |
| 22 | __val; \ |
| 23 | }) |
| 24 | |
| 25 | #define TTBR0 __ACCESS_CP15_64(0, c2) |
| 26 | #define TTBR1 __ACCESS_CP15_64(1, c2) |
| 27 | #define VTTBR __ACCESS_CP15_64(6, c2) |
| 28 | #define PAR __ACCESS_CP15_64(0, c7) |
| 29 | #define CNTP_CVAL __ACCESS_CP15_64(2, c14) |
| 30 | #define CNTV_CVAL __ACCESS_CP15_64(3, c14) |
| 31 | #define CNTVOFF __ACCESS_CP15_64(4, c14) |
| 32 | |
| 33 | #define MIDR __ACCESS_CP15(c0, 0, c0, 0) |
| 34 | #define CSSELR __ACCESS_CP15(c0, 2, c0, 0) |
| 35 | #define VPIDR __ACCESS_CP15(c0, 4, c0, 0) |
| 36 | #define VMPIDR __ACCESS_CP15(c0, 4, c0, 5) |
| 37 | #define SCTLR __ACCESS_CP15(c1, 0, c0, 0) |
| 38 | #define CPACR __ACCESS_CP15(c1, 0, c0, 2) |
| 39 | #define HCR __ACCESS_CP15(c1, 4, c1, 0) |
| 40 | #define HDCR __ACCESS_CP15(c1, 4, c1, 1) |
| 41 | #define HCPTR __ACCESS_CP15(c1, 4, c1, 2) |
| 42 | #define HSTR __ACCESS_CP15(c1, 4, c1, 3) |
| 43 | #define TTBCR __ACCESS_CP15(c2, 0, c0, 2) |
| 44 | #define HTCR __ACCESS_CP15(c2, 4, c0, 2) |
| 45 | #define VTCR __ACCESS_CP15(c2, 4, c1, 2) |
| 46 | #define DACR __ACCESS_CP15(c3, 0, c0, 0) |
| 47 | #define DFSR __ACCESS_CP15(c5, 0, c0, 0) |
| 48 | #define IFSR __ACCESS_CP15(c5, 0, c0, 1) |
| 49 | #define ADFSR __ACCESS_CP15(c5, 0, c1, 0) |
| 50 | #define AIFSR __ACCESS_CP15(c5, 0, c1, 1) |
| 51 | #define HSR __ACCESS_CP15(c5, 4, c2, 0) |
| 52 | #define DFAR __ACCESS_CP15(c6, 0, c0, 0) |
| 53 | #define IFAR __ACCESS_CP15(c6, 0, c0, 2) |
| 54 | #define HDFAR __ACCESS_CP15(c6, 4, c0, 0) |
| 55 | #define HIFAR __ACCESS_CP15(c6, 4, c0, 2) |
| 56 | #define HPFAR __ACCESS_CP15(c6, 4, c0, 4) |
| 57 | #define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0) |
| 58 | #define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6) |
| 59 | #define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1) |
| 60 | #define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0) |
| 61 | #define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0) |
| 62 | #define TLBIALL __ACCESS_CP15(c8, 0, c7, 0) |
| 63 | #define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4) |
| 64 | #define PRRR __ACCESS_CP15(c10, 0, c2, 0) |
| 65 | #define NMRR __ACCESS_CP15(c10, 0, c2, 1) |
| 66 | #define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0) |
| 67 | #define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1) |
| 68 | #define VBAR __ACCESS_CP15(c12, 0, c0, 0) |
| 69 | #define CID __ACCESS_CP15(c13, 0, c0, 1) |
| 70 | #define TID_URW __ACCESS_CP15(c13, 0, c0, 2) |
| 71 | #define TID_URO __ACCESS_CP15(c13, 0, c0, 3) |
| 72 | #define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4) |
| 73 | #define HTPIDR __ACCESS_CP15(c13, 4, c0, 2) |
| 74 | #define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0) |
| 75 | #define CNTP_CTL __ACCESS_CP15(c14, 0, c2, 1) |
| 76 | #define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1) |
| 77 | #define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0) |
| 78 | |
| 79 | /* AArch64 compatibility macros, only for the timer so far */ |
| 80 | #define read_sysreg_el0(r) read_sysreg(r##_EL0) |
| 81 | #define write_sysreg_el0(v, r) write_sysreg(v, r##_EL0) |
| 82 | |
| 83 | #define SYS_CNTP_CTL_EL0 CNTP_CTL |
| 84 | #define SYS_CNTP_CVAL_EL0 CNTP_CVAL |
| 85 | #define SYS_CNTV_CTL_EL0 CNTV_CTL |
| 86 | #define SYS_CNTV_CVAL_EL0 CNTV_CVAL |
| 87 | |
| 88 | #define cntvoff_el2 CNTVOFF |
| 89 | #define cnthctl_el2 CNTHCTL |
| 90 | |
| 91 | void __timer_enable_traps(struct kvm_vcpu *vcpu); |
| 92 | void __timer_disable_traps(struct kvm_vcpu *vcpu); |
| 93 | |
| 94 | void __vgic_v2_save_state(struct kvm_vcpu *vcpu); |
| 95 | void __vgic_v2_restore_state(struct kvm_vcpu *vcpu); |
| 96 | |
| 97 | void __sysreg_save_state(struct kvm_cpu_context *ctxt); |
| 98 | void __sysreg_restore_state(struct kvm_cpu_context *ctxt); |
| 99 | |
| 100 | void __vgic_v3_save_state(struct kvm_vcpu *vcpu); |
| 101 | void __vgic_v3_restore_state(struct kvm_vcpu *vcpu); |
| 102 | void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu); |
| 103 | void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu); |
| 104 | void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu); |
| 105 | void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu); |
| 106 | |
| 107 | asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp); |
| 108 | asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp); |
| 109 | static inline bool __vfp_enabled(void) |
| 110 | { |
| 111 | return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10))); |
| 112 | } |
| 113 | |
| 114 | void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt); |
| 115 | void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt); |
| 116 | |
| 117 | asmlinkage int __guest_enter(struct kvm_vcpu *vcpu, |
| 118 | struct kvm_cpu_context *host); |
| 119 | asmlinkage int __hyp_do_panic(const char *, int, u32); |
| 120 | |
| 121 | #endif /* __ARM_KVM_HYP_H__ */ |