| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * arch/arm/mach-footbridge/include/mach/hardware.h |
| 4 | * |
| 5 | * Copyright (C) 1998-1999 Russell King. |
| 6 | * |
| 7 | * This file contains the hardware definitions of the EBSA-285. |
| 8 | */ |
| 9 | #ifndef __ASM_ARCH_HARDWARE_H |
| 10 | #define __ASM_ARCH_HARDWARE_H |
| 11 | |
| 12 | /* Virtual Physical Size |
| 13 | * 0xff800000 0x40000000 1MB X-Bus |
| 14 | * 0xff000000 0x7c000000 1MB PCI I/O space |
| 15 | * 0xfe000000 0x42000000 1MB CSR |
| 16 | * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) |
| 17 | * 0xfc000000 0x79000000 1MB PCI IACK/special space |
| 18 | * 0xfb000000 0x7a000000 16MB PCI Config type 1 |
| 19 | * 0xfa000000 0x7b000000 16MB PCI Config type 0 |
| 20 | * 0xf9000000 0x50000000 1MB Cache flush |
| 21 | * 0xf0000000 0x80000000 16MB ISA memory |
| 22 | */ |
| 23 | |
| 24 | #ifdef CONFIG_MMU |
| 25 | #define MMU_IO(a, b) (a) |
| 26 | #else |
| 27 | #define MMU_IO(a, b) (b) |
| 28 | #endif |
| 29 | |
| 30 | #define XBUS_SIZE 0x00100000 |
| 31 | #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) |
| 32 | |
| 33 | #define ARMCSR_SIZE 0x00100000 |
| 34 | #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) |
| 35 | |
| 36 | #define WFLUSH_SIZE 0x00100000 |
| 37 | #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) |
| 38 | |
| 39 | #define PCIIACK_SIZE 0x00100000 |
| 40 | #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) |
| 41 | |
| 42 | #define PCICFG1_SIZE 0x01000000 |
| 43 | #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) |
| 44 | |
| 45 | #define PCICFG0_SIZE 0x01000000 |
| 46 | #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) |
| 47 | |
| 48 | #define PCIMEM_SIZE 0x01000000 |
| 49 | #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) |
| 50 | |
| 51 | #define XBUS_CS2 0x40012000 |
| 52 | |
| 53 | #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) |
| 54 | #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) |
| 55 | #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) |
| 56 | #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) |
| 57 | #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) |
| 58 | |
| 59 | #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ |
| 60 | |
| 61 | |
| 62 | /* PIC irq control */ |
| 63 | #define PIC_LO 0x20 |
| 64 | #define PIC_MASK_LO 0x21 |
| 65 | #define PIC_HI 0xA0 |
| 66 | #define PIC_MASK_HI 0xA1 |
| 67 | |
| 68 | /* GPIO pins */ |
| 69 | #define GPIO_CCLK 0x800 |
| 70 | #define GPIO_DSCLK 0x400 |
| 71 | #define GPIO_E2CLK 0x200 |
| 72 | #define GPIO_IOLOAD 0x100 |
| 73 | #define GPIO_RED_LED 0x080 |
| 74 | #define GPIO_WDTIMER 0x040 |
| 75 | #define GPIO_DATA 0x020 |
| 76 | #define GPIO_IOCLK 0x010 |
| 77 | #define GPIO_DONE 0x008 |
| 78 | #define GPIO_FAN 0x004 |
| 79 | #define GPIO_GREEN_LED 0x002 |
| 80 | #define GPIO_RESET 0x001 |
| 81 | |
| 82 | /* CPLD pins */ |
| 83 | #define CPLD_DS_ENABLE 8 |
| 84 | #define CPLD_7111_DISABLE 4 |
| 85 | #define CPLD_UNMUTE 2 |
| 86 | #define CPLD_FLASH_WR_ENABLE 1 |
| 87 | |
| 88 | #ifndef __ASSEMBLY__ |
| 89 | extern raw_spinlock_t nw_gpio_lock; |
| 90 | extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); |
| 91 | extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); |
| 92 | extern unsigned int nw_gpio_read(void); |
| 93 | extern void nw_cpld_modify(unsigned int mask, unsigned int set); |
| 94 | #endif |
| 95 | |
| 96 | #endif |