| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/reset.c |
| 3 | * |
| 4 | * Author: Neil Zhang <zhangwm@marvell.com> |
| 5 | * Copyright: (C) 2012 Marvell International Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/smp.h> |
| 15 | #include <linux/cputype.h> |
| 16 | |
| 17 | #include <asm/io.h> |
| 18 | #include <asm/cacheflush.h> |
| 19 | #include <asm/mach/map.h> |
| 20 | #include <asm/mcpm.h> |
| 21 | |
| 22 | #include <soc/asr/addr-map.h> |
| 23 | |
| 24 | #include "reset.h" |
| 25 | |
| 26 | #define PMU_CC2_AP APMU_REG(0x0100) |
| 27 | #define CIU_WARM_RESET_VECTOR CIU_REG(0x00d8) |
| 28 | #define SW_SCRATCH CIU_REG(0x24) |
| 29 | |
| 30 | #define ASR1901_APMU_CORE_WAKEUP APMU_REG(0x012C) |
| 31 | |
| 32 | /* |
| 33 | * This function is called from boot_secondary to bootup the secondary cpu. |
| 34 | */ |
| 35 | #ifndef CONFIG_OPTEE |
| 36 | void mmp_cpu_power_up(unsigned int cpu, unsigned int cluster) |
| 37 | { |
| 38 | u32 tmp; |
| 39 | |
| 40 | BUG_ON(cpu == 0); |
| 41 | |
| 42 | tmp = readl(PMU_CC2_AP); |
| 43 | if (cpu_is_asr1901() || cpu_is_asr1906()) { |
| 44 | tmp = readl(ASR1901_APMU_CORE_WAKEUP); |
| 45 | if (!(tmp & ASR1901_CPU_CORE_WAKEUP(cpu))) { |
| 46 | /* Release secondary core from reset */ |
| 47 | tmp |= ASR1901_CPU_CORE_WAKEUP(cpu); |
| 48 | writel(tmp, ASR1901_APMU_CORE_WAKEUP); |
| 49 | } |
| 50 | } else if (cpu_is_pxa1088() || cpu_is_pxa1L88() || cpu_is_pxa1U88()) { |
| 51 | if (tmp & PXA1088_CPU_CORE_RST(cpu)) { |
| 52 | /* Release secondary core from reset */ |
| 53 | tmp &= ~(PXA1088_CPU_POR_RST(cpu) |
| 54 | | PXA1088_CPU_CORE_RST(cpu) | PXA1088_CPU_DBG_RST(cpu)); |
| 55 | writel(tmp, PMU_CC2_AP); |
| 56 | } |
| 57 | } else { |
| 58 | if (tmp & CPU_CORE_RST(cpu)) { |
| 59 | /* Release secondary core from reset */ |
| 60 | tmp &= ~(CPU_CORE_RST(cpu) |
| 61 | | CPU_DBG_RST(cpu) | CPU_WDOG_RST(cpu)); |
| 62 | writel(tmp, PMU_CC2_AP); |
| 63 | } |
| 64 | } |
| 65 | } |
| 66 | #endif |
| 67 | |
| 68 | int __init mmp_entry_vector_init(void) |
| 69 | { |
| 70 | |
| 71 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_ASR1901) |
| 72 | |
| 73 | #ifndef CONFIG_OPTEE |
| 74 | writel(__pa(mcpm_entry_point), CIU_WARM_RESET_VECTOR); |
| 75 | #endif |
| 76 | |
| 77 | #endif |
| 78 | |
| 79 | #ifdef CONFIG_CPU_ASR18XX |
| 80 | writel(__pa(cpu_resume), CIU_WARM_RESET_VECTOR); |
| 81 | #endif |
| 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | late_initcall(mmp_entry_vector_init); |