| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * arch/arm/mach-rpc/include/mach/hardware.h |
| 4 | * |
| 5 | * Copyright (C) 1996-1999 Russell King. |
| 6 | * |
| 7 | * This file contains the hardware definitions of the RiscPC series machines. |
| 8 | */ |
| 9 | #ifndef __ASM_ARCH_HARDWARE_H |
| 10 | #define __ASM_ARCH_HARDWARE_H |
| 11 | |
| 12 | #include <mach/memory.h> |
| 13 | |
| 14 | /* |
| 15 | * What hardware must be present |
| 16 | */ |
| 17 | #define HAS_IOMD |
| 18 | #define HAS_VIDC20 |
| 19 | |
| 20 | /* Hardware addresses of major areas. |
| 21 | * *_START is the physical address |
| 22 | * *_SIZE is the size of the region |
| 23 | * *_BASE is the virtual address |
| 24 | */ |
| 25 | #define RPC_RAM_SIZE 0x10000000 |
| 26 | #define RPC_RAM_START 0x10000000 |
| 27 | |
| 28 | #define EASI_SIZE 0x08000000 /* EASI I/O */ |
| 29 | #define EASI_START 0x08000000 |
| 30 | #define EASI_BASE IOMEM(0xe5000000) |
| 31 | |
| 32 | #define IO_START 0x03000000 /* I/O */ |
| 33 | #define IO_SIZE 0x01000000 |
| 34 | #define IO_BASE IOMEM(0xe0000000) |
| 35 | |
| 36 | #define SCREEN_START 0x02000000 /* VRAM */ |
| 37 | #define SCREEN_END 0xdfc00000 |
| 38 | #define SCREEN_BASE 0xdf800000 |
| 39 | |
| 40 | #define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000) |
| 41 | |
| 42 | /* |
| 43 | * IO Addresses |
| 44 | */ |
| 45 | #define ECARD_EASI_BASE (EASI_BASE) |
| 46 | #define VIDC_BASE (IO_BASE + 0x00400000) |
| 47 | #define EXPMASK_BASE (IO_BASE + 0x00360000) |
| 48 | #define ECARD_IOC4_BASE (IO_BASE + 0x00270000) |
| 49 | #define ECARD_IOC_BASE (IO_BASE + 0x00240000) |
| 50 | #define IOMD_BASE (IO_BASE + 0x00200000) |
| 51 | #define IOC_BASE (IO_BASE + 0x00200000) |
| 52 | #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) |
| 53 | #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) |
| 54 | #define PCIO_BASE (IO_BASE + 0x00010000) |
| 55 | #define ECARD_MEMC_BASE (IO_BASE + 0x00000000) |
| 56 | |
| 57 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) |
| 58 | |
| 59 | #define NETSLOT_BASE 0x0302b000 |
| 60 | #define NETSLOT_SIZE 0x00001000 |
| 61 | |
| 62 | #define PODSLOT_IOC0_BASE 0x03240000 |
| 63 | #define PODSLOT_IOC4_BASE 0x03270000 |
| 64 | #define PODSLOT_IOC_SIZE (1 << 14) |
| 65 | #define PODSLOT_MEMC_BASE 0x03000000 |
| 66 | #define PODSLOT_MEMC_SIZE (1 << 14) |
| 67 | #define PODSLOT_EASI_BASE 0x08000000 |
| 68 | #define PODSLOT_EASI_SIZE (1 << 24) |
| 69 | |
| 70 | #define EXPMASK_STATUS (EXPMASK_BASE + 0x00) |
| 71 | #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) |
| 72 | |
| 73 | #endif |