| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2003 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * S3C2410 - Memory map definitions |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARCH_MAP_H |
| 10 | #define __ASM_ARCH_MAP_H |
| 11 | |
| 12 | #include <plat/map-base.h> |
| 13 | #include <plat/map-s3c.h> |
| 14 | |
| 15 | /* |
| 16 | * interrupt controller is the first thing we put in, to make |
| 17 | * the assembly code for the irq detection easier |
| 18 | */ |
| 19 | #define S3C2410_PA_IRQ (0x4A000000) |
| 20 | #define S3C24XX_SZ_IRQ SZ_1M |
| 21 | |
| 22 | /* memory controller registers */ |
| 23 | #define S3C2410_PA_MEMCTRL (0x48000000) |
| 24 | #define S3C24XX_SZ_MEMCTRL SZ_1M |
| 25 | |
| 26 | /* Timers */ |
| 27 | #define S3C2410_PA_TIMER (0x51000000) |
| 28 | #define S3C24XX_SZ_TIMER SZ_1M |
| 29 | |
| 30 | /* Clock and Power management */ |
| 31 | #define S3C24XX_SZ_CLKPWR SZ_1M |
| 32 | |
| 33 | /* USB Device port */ |
| 34 | #define S3C2410_PA_USBDEV (0x52000000) |
| 35 | #define S3C24XX_SZ_USBDEV SZ_1M |
| 36 | |
| 37 | /* Watchdog */ |
| 38 | #define S3C2410_PA_WATCHDOG (0x53000000) |
| 39 | #define S3C24XX_SZ_WATCHDOG SZ_1M |
| 40 | |
| 41 | /* Standard size definitions for peripheral blocks. */ |
| 42 | |
| 43 | #define S3C24XX_SZ_UART SZ_1M |
| 44 | #define S3C24XX_SZ_IIS SZ_1M |
| 45 | #define S3C24XX_SZ_ADC SZ_1M |
| 46 | #define S3C24XX_SZ_SPI SZ_1M |
| 47 | #define S3C24XX_SZ_SDI SZ_1M |
| 48 | #define S3C24XX_SZ_NAND SZ_1M |
| 49 | #define S3C24XX_SZ_GPIO SZ_1M |
| 50 | |
| 51 | /* USB host controller */ |
| 52 | #define S3C2410_PA_USBHOST (0x49000000) |
| 53 | |
| 54 | /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ |
| 55 | #define S3C2416_PA_HSUDC (0x49800000) |
| 56 | #define S3C2416_SZ_HSUDC (SZ_4K) |
| 57 | |
| 58 | /* DMA controller */ |
| 59 | #define S3C2410_PA_DMA (0x4B000000) |
| 60 | #define S3C24XX_SZ_DMA SZ_1M |
| 61 | |
| 62 | /* Clock and Power management */ |
| 63 | #define S3C2410_PA_CLKPWR (0x4C000000) |
| 64 | |
| 65 | /* LCD controller */ |
| 66 | #define S3C2410_PA_LCD (0x4D000000) |
| 67 | #define S3C24XX_SZ_LCD SZ_1M |
| 68 | |
| 69 | /* NAND flash controller */ |
| 70 | #define S3C2410_PA_NAND (0x4E000000) |
| 71 | |
| 72 | /* IIC hardware controller */ |
| 73 | #define S3C2410_PA_IIC (0x54000000) |
| 74 | |
| 75 | /* IIS controller */ |
| 76 | #define S3C2410_PA_IIS (0x55000000) |
| 77 | |
| 78 | /* RTC */ |
| 79 | #define S3C2410_PA_RTC (0x57000000) |
| 80 | #define S3C24XX_SZ_RTC SZ_1M |
| 81 | |
| 82 | /* ADC */ |
| 83 | #define S3C2410_PA_ADC (0x58000000) |
| 84 | |
| 85 | /* SPI */ |
| 86 | #define S3C2410_PA_SPI (0x59000000) |
| 87 | #define S3C2443_PA_SPI0 (0x52000000) |
| 88 | #define S3C2443_PA_SPI1 S3C2410_PA_SPI |
| 89 | |
| 90 | /* SDI */ |
| 91 | #define S3C2410_PA_SDI (0x5A000000) |
| 92 | |
| 93 | /* CAMIF */ |
| 94 | #define S3C2440_PA_CAMIF (0x4F000000) |
| 95 | #define S3C2440_SZ_CAMIF SZ_1M |
| 96 | |
| 97 | /* AC97 */ |
| 98 | |
| 99 | #define S3C2440_PA_AC97 (0x5B000000) |
| 100 | #define S3C2440_SZ_AC97 SZ_1M |
| 101 | |
| 102 | /* S3C2443/S3C2416 High-speed SD/MMC */ |
| 103 | #define S3C2443_PA_HSMMC (0x4A800000) |
| 104 | #define S3C2416_PA_HSMMC0 (0x4AC00000) |
| 105 | |
| 106 | #define S3C2443_PA_FB (0x4C800000) |
| 107 | |
| 108 | /* S3C2412 memory and IO controls */ |
| 109 | #define S3C2412_PA_SSMC (0x4F000000) |
| 110 | |
| 111 | #define S3C2412_PA_EBI (0x48800000) |
| 112 | |
| 113 | /* physical addresses of all the chip-select areas */ |
| 114 | |
| 115 | #define S3C2410_CS0 (0x00000000) |
| 116 | #define S3C2410_CS1 (0x08000000) |
| 117 | #define S3C2410_CS2 (0x10000000) |
| 118 | #define S3C2410_CS3 (0x18000000) |
| 119 | #define S3C2410_CS4 (0x20000000) |
| 120 | #define S3C2410_CS5 (0x28000000) |
| 121 | #define S3C2410_CS6 (0x30000000) |
| 122 | #define S3C2410_CS7 (0x38000000) |
| 123 | |
| 124 | #define S3C2410_SDRAM_PA (S3C2410_CS6) |
| 125 | |
| 126 | /* Use a single interface for common resources between S3C24XX cpus */ |
| 127 | |
| 128 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ |
| 129 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL |
| 130 | #define S3C24XX_PA_DMA S3C2410_PA_DMA |
| 131 | #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR |
| 132 | #define S3C24XX_PA_LCD S3C2410_PA_LCD |
| 133 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER |
| 134 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV |
| 135 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG |
| 136 | #define S3C24XX_PA_IIS S3C2410_PA_IIS |
| 137 | #define S3C24XX_PA_RTC S3C2410_PA_RTC |
| 138 | #define S3C24XX_PA_ADC S3C2410_PA_ADC |
| 139 | #define S3C24XX_PA_SPI S3C2410_PA_SPI |
| 140 | #define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) |
| 141 | #define S3C24XX_PA_SDI S3C2410_PA_SDI |
| 142 | #define S3C24XX_PA_NAND S3C2410_PA_NAND |
| 143 | |
| 144 | #define S3C_PA_FB S3C2443_PA_FB |
| 145 | #define S3C_PA_IIC S3C2410_PA_IIC |
| 146 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST |
| 147 | #define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 |
| 148 | #define S3C_PA_HSMMC1 S3C2443_PA_HSMMC |
| 149 | #define S3C_PA_WDT S3C2410_PA_WATCHDOG |
| 150 | #define S3C_PA_NAND S3C24XX_PA_NAND |
| 151 | |
| 152 | #define S3C_PA_SPI0 S3C2443_PA_SPI0 |
| 153 | #define S3C_PA_SPI1 S3C2443_PA_SPI1 |
| 154 | |
| 155 | #define SAMSUNG_PA_TIMER S3C2410_PA_TIMER |
| 156 | |
| 157 | #endif /* __ASM_ARCH_MAP_H */ |