blob: bef9f96ffa11bdd718c85bfb4b07c0bc80dbe9a3 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/guest.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11#include <linux/bits.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/nospec.h>
15#include <linux/kvm_host.h>
16#include <linux/module.h>
17#include <linux/stddef.h>
18#include <linux/string.h>
19#include <linux/vmalloc.h>
20#include <linux/fs.h>
21#include <kvm/arm_psci.h>
22#include <asm/cputype.h>
23#include <linux/uaccess.h>
24#include <asm/fpsimd.h>
25#include <asm/kvm.h>
26#include <asm/kvm_emulate.h>
27#include <asm/kvm_coproc.h>
28#include <asm/kvm_host.h>
29#include <asm/sigcontext.h>
30
31#include "trace.h"
32
33#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
34#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
35
36struct kvm_stats_debugfs_item debugfs_entries[] = {
37 VCPU_STAT(hvc_exit_stat),
38 VCPU_STAT(wfe_exit_stat),
39 VCPU_STAT(wfi_exit_stat),
40 VCPU_STAT(mmio_exit_user),
41 VCPU_STAT(mmio_exit_kernel),
42 VCPU_STAT(exits),
43 { NULL }
44};
45
46int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
47{
48 return 0;
49}
50
51static bool core_reg_offset_is_vreg(u64 off)
52{
53 return off >= KVM_REG_ARM_CORE_REG(fp_regs.vregs) &&
54 off < KVM_REG_ARM_CORE_REG(fp_regs.fpsr);
55}
56
57static u64 core_reg_offset_from_id(u64 id)
58{
59 return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
60}
61
62static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
63{
64 int size;
65
66 switch (off) {
67 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
68 KVM_REG_ARM_CORE_REG(regs.regs[30]):
69 case KVM_REG_ARM_CORE_REG(regs.sp):
70 case KVM_REG_ARM_CORE_REG(regs.pc):
71 case KVM_REG_ARM_CORE_REG(regs.pstate):
72 case KVM_REG_ARM_CORE_REG(sp_el1):
73 case KVM_REG_ARM_CORE_REG(elr_el1):
74 case KVM_REG_ARM_CORE_REG(spsr[0]) ...
75 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]):
76 size = sizeof(__u64);
77 break;
78
79 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
80 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
81 size = sizeof(__uint128_t);
82 break;
83
84 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
85 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
86 size = sizeof(__u32);
87 break;
88
89 default:
90 return -EINVAL;
91 }
92
93 if (!IS_ALIGNED(off, size / sizeof(__u32)))
94 return -EINVAL;
95
96 /*
97 * The KVM_REG_ARM64_SVE regs must be used instead of
98 * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
99 * SVE-enabled vcpus:
100 */
101 if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
102 return -EINVAL;
103
104 return size;
105}
106
107static int validate_core_offset(const struct kvm_vcpu *vcpu,
108 const struct kvm_one_reg *reg)
109{
110 u64 off = core_reg_offset_from_id(reg->id);
111 int size = core_reg_size_from_offset(vcpu, off);
112
113 if (size < 0)
114 return -EINVAL;
115
116 if (KVM_REG_SIZE(reg->id) != size)
117 return -EINVAL;
118
119 return 0;
120}
121
122static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
123{
124 /*
125 * Because the kvm_regs structure is a mix of 32, 64 and
126 * 128bit fields, we index it as if it was a 32bit
127 * array. Hence below, nr_regs is the number of entries, and
128 * off the index in the "array".
129 */
130 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
131 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
132 int nr_regs = sizeof(*regs) / sizeof(__u32);
133 u32 off;
134
135 /* Our ID is an index into the kvm_regs struct. */
136 off = core_reg_offset_from_id(reg->id);
137 if (off >= nr_regs ||
138 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
139 return -ENOENT;
140
141 if (validate_core_offset(vcpu, reg))
142 return -EINVAL;
143
144 if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id)))
145 return -EFAULT;
146
147 return 0;
148}
149
150static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
151{
152 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
153 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
154 int nr_regs = sizeof(*regs) / sizeof(__u32);
155 __uint128_t tmp;
156 void *valp = &tmp;
157 u64 off;
158 int err = 0;
159
160 /* Our ID is an index into the kvm_regs struct. */
161 off = core_reg_offset_from_id(reg->id);
162 if (off >= nr_regs ||
163 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
164 return -ENOENT;
165
166 if (validate_core_offset(vcpu, reg))
167 return -EINVAL;
168
169 if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
170 return -EINVAL;
171
172 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
173 err = -EFAULT;
174 goto out;
175 }
176
177 if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
178 u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
179 switch (mode) {
180 case PSR_AA32_MODE_USR:
181 if (!system_supports_32bit_el0())
182 return -EINVAL;
183 break;
184 case PSR_AA32_MODE_FIQ:
185 case PSR_AA32_MODE_IRQ:
186 case PSR_AA32_MODE_SVC:
187 case PSR_AA32_MODE_ABT:
188 case PSR_AA32_MODE_UND:
189 case PSR_AA32_MODE_SYS:
190 if (!vcpu_el1_is_32bit(vcpu))
191 return -EINVAL;
192 break;
193 case PSR_MODE_EL0t:
194 case PSR_MODE_EL1t:
195 case PSR_MODE_EL1h:
196 if (vcpu_el1_is_32bit(vcpu))
197 return -EINVAL;
198 break;
199 default:
200 err = -EINVAL;
201 goto out;
202 }
203 }
204
205 memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id));
206
207 if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) {
208 int i;
209
210 for (i = 0; i < 16; i++)
211 *vcpu_reg32(vcpu, i) = (u32)*vcpu_reg32(vcpu, i);
212 }
213out:
214 return err;
215}
216
217#define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64)
218#define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
219#define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
220
221static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
222{
223 unsigned int max_vq, vq;
224 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
225
226 if (!vcpu_has_sve(vcpu))
227 return -ENOENT;
228
229 if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl)))
230 return -EINVAL;
231
232 memset(vqs, 0, sizeof(vqs));
233
234 max_vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
235 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
236 if (sve_vq_available(vq))
237 vqs[vq_word(vq)] |= vq_mask(vq);
238
239 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
240 return -EFAULT;
241
242 return 0;
243}
244
245static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
246{
247 unsigned int max_vq, vq;
248 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
249
250 if (!vcpu_has_sve(vcpu))
251 return -ENOENT;
252
253 if (kvm_arm_vcpu_sve_finalized(vcpu))
254 return -EPERM; /* too late! */
255
256 if (WARN_ON(vcpu->arch.sve_state))
257 return -EINVAL;
258
259 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
260 return -EFAULT;
261
262 max_vq = 0;
263 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; ++vq)
264 if (vq_present(vqs, vq))
265 max_vq = vq;
266
267 if (max_vq > sve_vq_from_vl(kvm_sve_max_vl))
268 return -EINVAL;
269
270 /*
271 * Vector lengths supported by the host can't currently be
272 * hidden from the guest individually: instead we can only set a
273 * maxmium via ZCR_EL2.LEN. So, make sure the available vector
274 * lengths match the set requested exactly up to the requested
275 * maximum:
276 */
277 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
278 if (vq_present(vqs, vq) != sve_vq_available(vq))
279 return -EINVAL;
280
281 /* Can't run with no vector lengths at all: */
282 if (max_vq < SVE_VQ_MIN)
283 return -EINVAL;
284
285 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
286 vcpu->arch.sve_max_vl = sve_vl_from_vq(max_vq);
287
288 return 0;
289}
290
291#define SVE_REG_SLICE_SHIFT 0
292#define SVE_REG_SLICE_BITS 5
293#define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
294#define SVE_REG_ID_BITS 5
295
296#define SVE_REG_SLICE_MASK \
297 GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \
298 SVE_REG_SLICE_SHIFT)
299#define SVE_REG_ID_MASK \
300 GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
301
302#define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS)
303
304#define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0))
305#define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0))
306
307/*
308 * Number of register slices required to cover each whole SVE register.
309 * NOTE: Only the first slice every exists, for now.
310 * If you are tempted to modify this, you must also rework sve_reg_to_region()
311 * to match:
312 */
313#define vcpu_sve_slices(vcpu) 1
314
315/* Bounds of a single SVE register slice within vcpu->arch.sve_state */
316struct sve_state_reg_region {
317 unsigned int koffset; /* offset into sve_state in kernel memory */
318 unsigned int klen; /* length in kernel memory */
319 unsigned int upad; /* extra trailing padding in user memory */
320};
321
322/*
323 * Validate SVE register ID and get sanitised bounds for user/kernel SVE
324 * register copy
325 */
326static int sve_reg_to_region(struct sve_state_reg_region *region,
327 struct kvm_vcpu *vcpu,
328 const struct kvm_one_reg *reg)
329{
330 /* reg ID ranges for Z- registers */
331 const u64 zreg_id_min = KVM_REG_ARM64_SVE_ZREG(0, 0);
332 const u64 zreg_id_max = KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1,
333 SVE_NUM_SLICES - 1);
334
335 /* reg ID ranges for P- registers and FFR (which are contiguous) */
336 const u64 preg_id_min = KVM_REG_ARM64_SVE_PREG(0, 0);
337 const u64 preg_id_max = KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1);
338
339 unsigned int vq;
340 unsigned int reg_num;
341
342 unsigned int reqoffset, reqlen; /* User-requested offset and length */
343 unsigned int maxlen; /* Maxmimum permitted length */
344
345 size_t sve_state_size;
346
347 const u64 last_preg_id = KVM_REG_ARM64_SVE_PREG(SVE_NUM_PREGS - 1,
348 SVE_NUM_SLICES - 1);
349
350 /* Verify that the P-regs and FFR really do have contiguous IDs: */
351 BUILD_BUG_ON(KVM_REG_ARM64_SVE_FFR(0) != last_preg_id + 1);
352
353 /* Verify that we match the UAPI header: */
354 BUILD_BUG_ON(SVE_NUM_SLICES != KVM_ARM64_SVE_MAX_SLICES);
355
356 reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;
357
358 if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) {
359 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
360 return -ENOENT;
361
362 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
363
364 reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
365 SVE_SIG_REGS_OFFSET;
366 reqlen = KVM_SVE_ZREG_SIZE;
367 maxlen = SVE_SIG_ZREG_SIZE(vq);
368 } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) {
369 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
370 return -ENOENT;
371
372 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
373
374 reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
375 SVE_SIG_REGS_OFFSET;
376 reqlen = KVM_SVE_PREG_SIZE;
377 maxlen = SVE_SIG_PREG_SIZE(vq);
378 } else {
379 return -EINVAL;
380 }
381
382 sve_state_size = vcpu_sve_state_size(vcpu);
383 if (WARN_ON(!sve_state_size))
384 return -EINVAL;
385
386 region->koffset = array_index_nospec(reqoffset, sve_state_size);
387 region->klen = min(maxlen, reqlen);
388 region->upad = reqlen - region->klen;
389
390 return 0;
391}
392
393static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
394{
395 int ret;
396 struct sve_state_reg_region region;
397 char __user *uptr = (char __user *)reg->addr;
398
399 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
400 if (reg->id == KVM_REG_ARM64_SVE_VLS)
401 return get_sve_vls(vcpu, reg);
402
403 /* Try to interpret reg ID as an architectural SVE register... */
404 ret = sve_reg_to_region(&region, vcpu, reg);
405 if (ret)
406 return ret;
407
408 if (!kvm_arm_vcpu_sve_finalized(vcpu))
409 return -EPERM;
410
411 if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
412 region.klen) ||
413 clear_user(uptr + region.klen, region.upad))
414 return -EFAULT;
415
416 return 0;
417}
418
419static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
420{
421 int ret;
422 struct sve_state_reg_region region;
423 const char __user *uptr = (const char __user *)reg->addr;
424
425 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
426 if (reg->id == KVM_REG_ARM64_SVE_VLS)
427 return set_sve_vls(vcpu, reg);
428
429 /* Try to interpret reg ID as an architectural SVE register... */
430 ret = sve_reg_to_region(&region, vcpu, reg);
431 if (ret)
432 return ret;
433
434 if (!kvm_arm_vcpu_sve_finalized(vcpu))
435 return -EPERM;
436
437 if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
438 region.klen))
439 return -EFAULT;
440
441 return 0;
442}
443
444int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
445{
446 return -EINVAL;
447}
448
449int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
450{
451 return -EINVAL;
452}
453
454static int copy_core_reg_indices(const struct kvm_vcpu *vcpu,
455 u64 __user *uindices)
456{
457 unsigned int i;
458 int n = 0;
459
460 for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
461 u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i;
462 int size = core_reg_size_from_offset(vcpu, i);
463
464 if (size < 0)
465 continue;
466
467 switch (size) {
468 case sizeof(__u32):
469 reg |= KVM_REG_SIZE_U32;
470 break;
471
472 case sizeof(__u64):
473 reg |= KVM_REG_SIZE_U64;
474 break;
475
476 case sizeof(__uint128_t):
477 reg |= KVM_REG_SIZE_U128;
478 break;
479
480 default:
481 WARN_ON(1);
482 continue;
483 }
484
485 if (uindices) {
486 if (put_user(reg, uindices))
487 return -EFAULT;
488 uindices++;
489 }
490
491 n++;
492 }
493
494 return n;
495}
496
497static unsigned long num_core_regs(const struct kvm_vcpu *vcpu)
498{
499 return copy_core_reg_indices(vcpu, NULL);
500}
501
502/**
503 * ARM64 versions of the TIMER registers, always available on arm64
504 */
505
506#define NUM_TIMER_REGS 3
507
508static bool is_timer_reg(u64 index)
509{
510 switch (index) {
511 case KVM_REG_ARM_TIMER_CTL:
512 case KVM_REG_ARM_TIMER_CNT:
513 case KVM_REG_ARM_TIMER_CVAL:
514 return true;
515 }
516 return false;
517}
518
519static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
520{
521 if (put_user(KVM_REG_ARM_TIMER_CTL, uindices))
522 return -EFAULT;
523 uindices++;
524 if (put_user(KVM_REG_ARM_TIMER_CNT, uindices))
525 return -EFAULT;
526 uindices++;
527 if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices))
528 return -EFAULT;
529
530 return 0;
531}
532
533static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
534{
535 void __user *uaddr = (void __user *)(long)reg->addr;
536 u64 val;
537 int ret;
538
539 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
540 if (ret != 0)
541 return -EFAULT;
542
543 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
544}
545
546static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
547{
548 void __user *uaddr = (void __user *)(long)reg->addr;
549 u64 val;
550
551 val = kvm_arm_timer_get_reg(vcpu, reg->id);
552 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
553}
554
555static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
556{
557 const unsigned int slices = vcpu_sve_slices(vcpu);
558
559 if (!vcpu_has_sve(vcpu))
560 return 0;
561
562 /* Policed by KVM_GET_REG_LIST: */
563 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
564
565 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
566 + 1; /* KVM_REG_ARM64_SVE_VLS */
567}
568
569static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
570 u64 __user *uindices)
571{
572 const unsigned int slices = vcpu_sve_slices(vcpu);
573 u64 reg;
574 unsigned int i, n;
575 int num_regs = 0;
576
577 if (!vcpu_has_sve(vcpu))
578 return 0;
579
580 /* Policed by KVM_GET_REG_LIST: */
581 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
582
583 /*
584 * Enumerate this first, so that userspace can save/restore in
585 * the order reported by KVM_GET_REG_LIST:
586 */
587 reg = KVM_REG_ARM64_SVE_VLS;
588 if (put_user(reg, uindices++))
589 return -EFAULT;
590 ++num_regs;
591
592 for (i = 0; i < slices; i++) {
593 for (n = 0; n < SVE_NUM_ZREGS; n++) {
594 reg = KVM_REG_ARM64_SVE_ZREG(n, i);
595 if (put_user(reg, uindices++))
596 return -EFAULT;
597 num_regs++;
598 }
599
600 for (n = 0; n < SVE_NUM_PREGS; n++) {
601 reg = KVM_REG_ARM64_SVE_PREG(n, i);
602 if (put_user(reg, uindices++))
603 return -EFAULT;
604 num_regs++;
605 }
606
607 reg = KVM_REG_ARM64_SVE_FFR(i);
608 if (put_user(reg, uindices++))
609 return -EFAULT;
610 num_regs++;
611 }
612
613 return num_regs;
614}
615
616/**
617 * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
618 *
619 * This is for all registers.
620 */
621unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
622{
623 unsigned long res = 0;
624
625 res += num_core_regs(vcpu);
626 res += num_sve_regs(vcpu);
627 res += kvm_arm_num_sys_reg_descs(vcpu);
628 res += kvm_arm_get_fw_num_regs(vcpu);
629 res += NUM_TIMER_REGS;
630
631 return res;
632}
633
634/**
635 * kvm_arm_copy_reg_indices - get indices of all registers.
636 *
637 * We do core registers right here, then we append system regs.
638 */
639int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
640{
641 int ret;
642
643 ret = copy_core_reg_indices(vcpu, uindices);
644 if (ret < 0)
645 return ret;
646 uindices += ret;
647
648 ret = copy_sve_reg_indices(vcpu, uindices);
649 if (ret < 0)
650 return ret;
651 uindices += ret;
652
653 ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
654 if (ret < 0)
655 return ret;
656 uindices += kvm_arm_get_fw_num_regs(vcpu);
657
658 ret = copy_timer_indices(vcpu, uindices);
659 if (ret < 0)
660 return ret;
661 uindices += NUM_TIMER_REGS;
662
663 return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
664}
665
666int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
667{
668 /* We currently use nothing arch-specific in upper 32 bits */
669 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
670 return -EINVAL;
671
672 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
673 case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg);
674 case KVM_REG_ARM_FW: return kvm_arm_get_fw_reg(vcpu, reg);
675 case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
676 }
677
678 if (is_timer_reg(reg->id))
679 return get_timer_reg(vcpu, reg);
680
681 return kvm_arm_sys_reg_get_reg(vcpu, reg);
682}
683
684int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
685{
686 /* We currently use nothing arch-specific in upper 32 bits */
687 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
688 return -EINVAL;
689
690 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
691 case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
692 case KVM_REG_ARM_FW: return kvm_arm_set_fw_reg(vcpu, reg);
693 case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
694 }
695
696 if (is_timer_reg(reg->id))
697 return set_timer_reg(vcpu, reg);
698
699 return kvm_arm_sys_reg_set_reg(vcpu, reg);
700}
701
702int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
703 struct kvm_sregs *sregs)
704{
705 return -EINVAL;
706}
707
708int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
709 struct kvm_sregs *sregs)
710{
711 return -EINVAL;
712}
713
714int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
715 struct kvm_vcpu_events *events)
716{
717 events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
718 events->exception.serror_has_esr = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
719
720 if (events->exception.serror_pending && events->exception.serror_has_esr)
721 events->exception.serror_esr = vcpu_get_vsesr(vcpu);
722
723 return 0;
724}
725
726int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
727 struct kvm_vcpu_events *events)
728{
729 bool serror_pending = events->exception.serror_pending;
730 bool has_esr = events->exception.serror_has_esr;
731
732 if (serror_pending && has_esr) {
733 if (!cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
734 return -EINVAL;
735
736 if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
737 kvm_set_sei_esr(vcpu, events->exception.serror_esr);
738 else
739 return -EINVAL;
740 } else if (serror_pending) {
741 kvm_inject_vabt(vcpu);
742 }
743
744 return 0;
745}
746
747int __attribute_const__ kvm_target_cpu(void)
748{
749 unsigned long implementor = read_cpuid_implementor();
750 unsigned long part_number = read_cpuid_part_number();
751
752 switch (implementor) {
753 case ARM_CPU_IMP_ARM:
754 switch (part_number) {
755 case ARM_CPU_PART_AEM_V8:
756 return KVM_ARM_TARGET_AEM_V8;
757 case ARM_CPU_PART_FOUNDATION:
758 return KVM_ARM_TARGET_FOUNDATION_V8;
759 case ARM_CPU_PART_CORTEX_A53:
760 return KVM_ARM_TARGET_CORTEX_A53;
761 case ARM_CPU_PART_CORTEX_A57:
762 return KVM_ARM_TARGET_CORTEX_A57;
763 }
764 break;
765 case ARM_CPU_IMP_APM:
766 switch (part_number) {
767 case APM_CPU_PART_POTENZA:
768 return KVM_ARM_TARGET_XGENE_POTENZA;
769 }
770 break;
771 }
772
773 /* Return a default generic target */
774 return KVM_ARM_TARGET_GENERIC_V8;
775}
776
777int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)
778{
779 int target = kvm_target_cpu();
780
781 if (target < 0)
782 return -ENODEV;
783
784 memset(init, 0, sizeof(*init));
785
786 /*
787 * For now, we don't return any features.
788 * In future, we might use features to return target
789 * specific features available for the preferred
790 * target type.
791 */
792 init->target = (__u32)target;
793
794 return 0;
795}
796
797int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
798{
799 return -EINVAL;
800}
801
802int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
803{
804 return -EINVAL;
805}
806
807int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
808 struct kvm_translation *tr)
809{
810 return -EINVAL;
811}
812
813#define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
814 KVM_GUESTDBG_USE_SW_BP | \
815 KVM_GUESTDBG_USE_HW | \
816 KVM_GUESTDBG_SINGLESTEP)
817
818/**
819 * kvm_arch_vcpu_ioctl_set_guest_debug - set up guest debugging
820 * @kvm: pointer to the KVM struct
821 * @kvm_guest_debug: the ioctl data buffer
822 *
823 * This sets up and enables the VM for guest debugging. Userspace
824 * passes in a control flag to enable different debug types and
825 * potentially other architecture specific information in the rest of
826 * the structure.
827 */
828int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
829 struct kvm_guest_debug *dbg)
830{
831 int ret = 0;
832
833 trace_kvm_set_guest_debug(vcpu, dbg->control);
834
835 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
836 ret = -EINVAL;
837 goto out;
838 }
839
840 if (dbg->control & KVM_GUESTDBG_ENABLE) {
841 vcpu->guest_debug = dbg->control;
842
843 /* Hardware assisted Break and Watch points */
844 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
845 vcpu->arch.external_debug_state = dbg->arch;
846 }
847
848 } else {
849 /* If not enabled clear all flags */
850 vcpu->guest_debug = 0;
851 }
852
853out:
854 return ret;
855}
856
857int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
858 struct kvm_device_attr *attr)
859{
860 int ret;
861
862 switch (attr->group) {
863 case KVM_ARM_VCPU_PMU_V3_CTRL:
864 ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
865 break;
866 case KVM_ARM_VCPU_TIMER_CTRL:
867 ret = kvm_arm_timer_set_attr(vcpu, attr);
868 break;
869 default:
870 ret = -ENXIO;
871 break;
872 }
873
874 return ret;
875}
876
877int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
878 struct kvm_device_attr *attr)
879{
880 int ret;
881
882 switch (attr->group) {
883 case KVM_ARM_VCPU_PMU_V3_CTRL:
884 ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
885 break;
886 case KVM_ARM_VCPU_TIMER_CTRL:
887 ret = kvm_arm_timer_get_attr(vcpu, attr);
888 break;
889 default:
890 ret = -ENXIO;
891 break;
892 }
893
894 return ret;
895}
896
897int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
898 struct kvm_device_attr *attr)
899{
900 int ret;
901
902 switch (attr->group) {
903 case KVM_ARM_VCPU_PMU_V3_CTRL:
904 ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
905 break;
906 case KVM_ARM_VCPU_TIMER_CTRL:
907 ret = kvm_arm_timer_has_attr(vcpu, attr);
908 break;
909 default:
910 ret = -ENXIO;
911 break;
912 }
913
914 return ret;
915}