| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | |
| 4 | #ifndef __ASM_CSKY_ENTRY_H |
| 5 | #define __ASM_CSKY_ENTRY_H |
| 6 | |
| 7 | #include <asm/setup.h> |
| 8 | #include <abi/regdef.h> |
| 9 | |
| 10 | #define LSAVE_PC 8 |
| 11 | #define LSAVE_PSR 12 |
| 12 | #define LSAVE_A0 24 |
| 13 | #define LSAVE_A1 28 |
| 14 | #define LSAVE_A2 32 |
| 15 | #define LSAVE_A3 36 |
| 16 | #define LSAVE_A4 40 |
| 17 | #define LSAVE_A5 44 |
| 18 | |
| 19 | #define KSPTOUSP |
| 20 | #define USPTOKSP |
| 21 | |
| 22 | #define usp cr<14, 1> |
| 23 | |
| 24 | .macro SAVE_ALL epc_inc |
| 25 | subi sp, 152 |
| 26 | stw tls, (sp, 0) |
| 27 | stw lr, (sp, 4) |
| 28 | |
| 29 | mfcr lr, epc |
| 30 | movi tls, \epc_inc |
| 31 | add lr, tls |
| 32 | stw lr, (sp, 8) |
| 33 | |
| 34 | mfcr lr, epsr |
| 35 | stw lr, (sp, 12) |
| 36 | btsti lr, 31 |
| 37 | bf 1f |
| 38 | addi lr, sp, 152 |
| 39 | br 2f |
| 40 | 1: |
| 41 | mfcr lr, usp |
| 42 | 2: |
| 43 | stw lr, (sp, 16) |
| 44 | |
| 45 | stw a0, (sp, 20) |
| 46 | stw a0, (sp, 24) |
| 47 | stw a1, (sp, 28) |
| 48 | stw a2, (sp, 32) |
| 49 | stw a3, (sp, 36) |
| 50 | |
| 51 | addi sp, 40 |
| 52 | stm r4-r13, (sp) |
| 53 | |
| 54 | addi sp, 40 |
| 55 | stm r16-r30, (sp) |
| 56 | #ifdef CONFIG_CPU_HAS_HILO |
| 57 | mfhi lr |
| 58 | stw lr, (sp, 60) |
| 59 | mflo lr |
| 60 | stw lr, (sp, 64) |
| 61 | mfcr lr, cr14 |
| 62 | stw lr, (sp, 68) |
| 63 | #endif |
| 64 | subi sp, 80 |
| 65 | .endm |
| 66 | |
| 67 | .macro RESTORE_ALL |
| 68 | psrclr ie |
| 69 | ldw tls, (sp, 0) |
| 70 | ldw lr, (sp, 4) |
| 71 | ldw a0, (sp, 8) |
| 72 | mtcr a0, epc |
| 73 | ldw a0, (sp, 12) |
| 74 | mtcr a0, epsr |
| 75 | btsti a0, 31 |
| 76 | ldw a0, (sp, 16) |
| 77 | mtcr a0, usp |
| 78 | mtcr a0, ss0 |
| 79 | |
| 80 | #ifdef CONFIG_CPU_HAS_HILO |
| 81 | ldw a0, (sp, 140) |
| 82 | mthi a0 |
| 83 | ldw a0, (sp, 144) |
| 84 | mtlo a0 |
| 85 | ldw a0, (sp, 148) |
| 86 | mtcr a0, cr14 |
| 87 | #endif |
| 88 | |
| 89 | ldw a0, (sp, 24) |
| 90 | ldw a1, (sp, 28) |
| 91 | ldw a2, (sp, 32) |
| 92 | ldw a3, (sp, 36) |
| 93 | |
| 94 | addi sp, 40 |
| 95 | ldm r4-r13, (sp) |
| 96 | addi sp, 40 |
| 97 | ldm r16-r30, (sp) |
| 98 | addi sp, 72 |
| 99 | bf 1f |
| 100 | mfcr sp, ss0 |
| 101 | 1: |
| 102 | rte |
| 103 | .endm |
| 104 | |
| 105 | .macro SAVE_SWITCH_STACK |
| 106 | subi sp, 64 |
| 107 | stm r4-r11, (sp) |
| 108 | stw lr, (sp, 32) |
| 109 | stw r16, (sp, 36) |
| 110 | stw r17, (sp, 40) |
| 111 | stw r26, (sp, 44) |
| 112 | stw r27, (sp, 48) |
| 113 | stw r28, (sp, 52) |
| 114 | stw r29, (sp, 56) |
| 115 | stw r30, (sp, 60) |
| 116 | #ifdef CONFIG_CPU_HAS_HILO |
| 117 | subi sp, 16 |
| 118 | mfhi lr |
| 119 | stw lr, (sp, 0) |
| 120 | mflo lr |
| 121 | stw lr, (sp, 4) |
| 122 | mfcr lr, cr14 |
| 123 | stw lr, (sp, 8) |
| 124 | #endif |
| 125 | .endm |
| 126 | |
| 127 | .macro RESTORE_SWITCH_STACK |
| 128 | #ifdef CONFIG_CPU_HAS_HILO |
| 129 | ldw lr, (sp, 0) |
| 130 | mthi lr |
| 131 | ldw lr, (sp, 4) |
| 132 | mtlo lr |
| 133 | ldw lr, (sp, 8) |
| 134 | mtcr lr, cr14 |
| 135 | addi sp, 16 |
| 136 | #endif |
| 137 | ldm r4-r11, (sp) |
| 138 | ldw lr, (sp, 32) |
| 139 | ldw r16, (sp, 36) |
| 140 | ldw r17, (sp, 40) |
| 141 | ldw r26, (sp, 44) |
| 142 | ldw r27, (sp, 48) |
| 143 | ldw r28, (sp, 52) |
| 144 | ldw r29, (sp, 56) |
| 145 | ldw r30, (sp, 60) |
| 146 | addi sp, 64 |
| 147 | .endm |
| 148 | |
| 149 | /* MMU registers operators. */ |
| 150 | .macro RD_MIR rx |
| 151 | mfcr \rx, cr<0, 15> |
| 152 | .endm |
| 153 | |
| 154 | .macro RD_MEH rx |
| 155 | mfcr \rx, cr<4, 15> |
| 156 | .endm |
| 157 | |
| 158 | .macro RD_MCIR rx |
| 159 | mfcr \rx, cr<8, 15> |
| 160 | .endm |
| 161 | |
| 162 | .macro RD_PGDR rx |
| 163 | mfcr \rx, cr<29, 15> |
| 164 | .endm |
| 165 | |
| 166 | .macro RD_PGDR_K rx |
| 167 | mfcr \rx, cr<28, 15> |
| 168 | .endm |
| 169 | |
| 170 | .macro WR_MEH rx |
| 171 | mtcr \rx, cr<4, 15> |
| 172 | .endm |
| 173 | |
| 174 | .macro WR_MCIR rx |
| 175 | mtcr \rx, cr<8, 15> |
| 176 | .endm |
| 177 | |
| 178 | .macro SETUP_MMU |
| 179 | /* Init psr and enable ee */ |
| 180 | lrw r6, DEFAULT_PSR_VALUE |
| 181 | mtcr r6, psr |
| 182 | psrset ee |
| 183 | |
| 184 | /* Invalid I/Dcache BTB BHT */ |
| 185 | movi r6, 7 |
| 186 | lsli r6, 16 |
| 187 | addi r6, (1<<4) | 3 |
| 188 | mtcr r6, cr17 |
| 189 | |
| 190 | /* Invalid all TLB */ |
| 191 | bgeni r6, 26 |
| 192 | mtcr r6, cr<8, 15> /* Set MCIR */ |
| 193 | |
| 194 | /* Check MMU on/off */ |
| 195 | mfcr r6, cr18 |
| 196 | btsti r6, 0 |
| 197 | bt 1f |
| 198 | |
| 199 | /* MMU off: setup mapping tlb entry */ |
| 200 | movi r6, 0 |
| 201 | mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ |
| 202 | |
| 203 | grs r6, 1f /* Get current pa by PC */ |
| 204 | bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */ |
| 205 | andn r6, r7 |
| 206 | mtcr r6, cr<4, 15> /* Set MEH */ |
| 207 | |
| 208 | mov r8, r6 |
| 209 | movi r7, 0x00000006 |
| 210 | or r8, r7 |
| 211 | mtcr r8, cr<2, 15> /* Set MEL0 */ |
| 212 | movi r7, 0x00001006 |
| 213 | or r8, r7 |
| 214 | mtcr r8, cr<3, 15> /* Set MEL1 */ |
| 215 | |
| 216 | bgeni r8, 28 |
| 217 | mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ |
| 218 | |
| 219 | br 2f |
| 220 | 1: |
| 221 | /* |
| 222 | * MMU on: use origin MSA value from bootloader |
| 223 | * |
| 224 | * cr<30/31, 15> MSA register format: |
| 225 | * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 226 | * BA Reserved SH WA B SO SEC C D V |
| 227 | */ |
| 228 | mfcr r6, cr<30, 15> /* Get MSA0 */ |
| 229 | 2: |
| 230 | lsri r6, 29 |
| 231 | lsli r6, 29 |
| 232 | addi r6, 0x1ce |
| 233 | mtcr r6, cr<30, 15> /* Set MSA0 */ |
| 234 | |
| 235 | movi r6, 0 |
| 236 | mtcr r6, cr<31, 15> /* Clr MSA1 */ |
| 237 | |
| 238 | /* enable MMU */ |
| 239 | mfcr r6, cr18 |
| 240 | bseti r6, 0 |
| 241 | mtcr r6, cr18 |
| 242 | |
| 243 | jmpi 3f /* jump to va */ |
| 244 | 3: |
| 245 | .endm |
| 246 | |
| 247 | .macro ANDI_R3 rx, imm |
| 248 | lsri \rx, 3 |
| 249 | andi \rx, (\imm >> 3) |
| 250 | .endm |
| 251 | #endif /* __ASM_CSKY_ENTRY_H */ |