| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _M68KNOMMU_CACHEFLUSH_H |
| 3 | #define _M68KNOMMU_CACHEFLUSH_H |
| 4 | |
| 5 | /* |
| 6 | * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com> |
| 7 | */ |
| 8 | #include <linux/mm.h> |
| 9 | #include <asm/mcfsim.h> |
| 10 | |
| 11 | #define flush_cache_all() __flush_cache_all() |
| 12 | #define flush_cache_mm(mm) do { } while (0) |
| 13 | #define flush_cache_dup_mm(mm) do { } while (0) |
| 14 | #define flush_cache_range(vma, start, end) do { } while (0) |
| 15 | #define flush_cache_page(vma, vmaddr) do { } while (0) |
| 16 | #define flush_dcache_range(start, len) __flush_dcache_all() |
| 17 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
| 18 | #define flush_dcache_page(page) do { } while (0) |
| 19 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 20 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| 21 | #define flush_icache_range(start, len) __flush_icache_all() |
| 22 | #define flush_icache_page(vma,pg) do { } while (0) |
| 23 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) |
| 24 | #define flush_cache_vmap(start, end) do { } while (0) |
| 25 | #define flush_cache_vunmap(start, end) do { } while (0) |
| 26 | |
| 27 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 28 | memcpy(dst, src, len) |
| 29 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 30 | memcpy(dst, src, len) |
| 31 | |
| 32 | void mcf_cache_push(void); |
| 33 | |
| 34 | static inline void __clear_cache_all(void) |
| 35 | { |
| 36 | #ifdef CACHE_INVALIDATE |
| 37 | __asm__ __volatile__ ( |
| 38 | "movec %0, %%CACR\n\t" |
| 39 | "nop\n\t" |
| 40 | : : "r" (CACHE_INVALIDATE) ); |
| 41 | #endif |
| 42 | } |
| 43 | |
| 44 | static inline void __flush_cache_all(void) |
| 45 | { |
| 46 | #ifdef CACHE_PUSH |
| 47 | mcf_cache_push(); |
| 48 | #endif |
| 49 | __clear_cache_all(); |
| 50 | } |
| 51 | |
| 52 | /* |
| 53 | * Some ColdFire parts implement separate instruction and data caches, |
| 54 | * on those we should just flush the appropriate cache. If we don't need |
| 55 | * to do any specific flushing then this will be optimized away. |
| 56 | */ |
| 57 | static inline void __flush_icache_all(void) |
| 58 | { |
| 59 | #ifdef CACHE_INVALIDATEI |
| 60 | __asm__ __volatile__ ( |
| 61 | "movec %0, %%CACR\n\t" |
| 62 | "nop\n\t" |
| 63 | : : "r" (CACHE_INVALIDATEI) ); |
| 64 | #endif |
| 65 | } |
| 66 | |
| 67 | static inline void __flush_dcache_all(void) |
| 68 | { |
| 69 | #ifdef CACHE_PUSH |
| 70 | mcf_cache_push(); |
| 71 | #endif |
| 72 | #ifdef CACHE_INVALIDATED |
| 73 | __asm__ __volatile__ ( |
| 74 | "movec %0, %%CACR\n\t" |
| 75 | "nop\n\t" |
| 76 | : : "r" (CACHE_INVALIDATED) ); |
| 77 | #else |
| 78 | /* Flush the write buffer */ |
| 79 | __asm__ __volatile__ ( "nop" ); |
| 80 | #endif |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * Push cache entries at supplied address. We want to write back any dirty |
| 85 | * data and then invalidate the cache lines associated with this address. |
| 86 | */ |
| 87 | static inline void cache_push(unsigned long paddr, int len) |
| 88 | { |
| 89 | __flush_cache_all(); |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Clear cache entries at supplied address (that is don't write back any |
| 94 | * dirty data). |
| 95 | */ |
| 96 | static inline void cache_clear(unsigned long paddr, int len) |
| 97 | { |
| 98 | __clear_cache_all(); |
| 99 | } |
| 100 | |
| 101 | #endif /* _M68KNOMMU_CACHEFLUSH_H */ |