| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /****************************************************************************/ |
| 3 | |
| 4 | /* |
| 5 | * m523xsim.h -- ColdFire 523x System Integration Module support. |
| 6 | * |
| 7 | * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> |
| 8 | */ |
| 9 | |
| 10 | /****************************************************************************/ |
| 11 | #ifndef m523xsim_h |
| 12 | #define m523xsim_h |
| 13 | /****************************************************************************/ |
| 14 | |
| 15 | #define CPU_NAME "COLDFIRE(m523x)" |
| 16 | #define CPU_INSTR_PER_JIFFY 3 |
| 17 | #define MCF_BUSCLK (MCF_CLK / 2) |
| 18 | |
| 19 | #include <asm/m52xxacr.h> |
| 20 | |
| 21 | /* |
| 22 | * Define the 523x SIM register set addresses. |
| 23 | */ |
| 24 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| 25 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ |
| 26 | |
| 27 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 28 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 29 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 30 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 31 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 32 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 33 | #define MCFINTC_IRLR 0x18 /* */ |
| 34 | #define MCFINTC_IACKL 0x19 /* */ |
| 35 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 36 | |
| 37 | #define MCFINT_VECBASE 64 /* Vector base number */ |
| 38 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 39 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| 40 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ |
| 41 | #define MCFINT_I2C0 17 /* Interrupt number for I2C */ |
| 42 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| 43 | #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ |
| 44 | #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ |
| 45 | #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ |
| 46 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 47 | |
| 48 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| 49 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
| 50 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
| 51 | |
| 52 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| 53 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
| 54 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| 55 | |
| 56 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 57 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| 58 | #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) |
| 59 | |
| 60 | /* |
| 61 | * SDRAM configuration registers. |
| 62 | */ |
| 63 | #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ |
| 64 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ |
| 65 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ |
| 66 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ |
| 67 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ |
| 68 | |
| 69 | /* |
| 70 | * Reset Control Unit (relative to IPSBAR). |
| 71 | */ |
| 72 | #define MCF_RCR (MCF_IPSBAR + 0x110000) |
| 73 | #define MCF_RSR (MCF_IPSBAR + 0x110001) |
| 74 | |
| 75 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 76 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| 77 | |
| 78 | /* |
| 79 | * UART module. |
| 80 | */ |
| 81 | #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) |
| 82 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) |
| 83 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) |
| 84 | |
| 85 | /* |
| 86 | * FEC ethernet module. |
| 87 | */ |
| 88 | #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) |
| 89 | #define MCFFEC_SIZE0 0x800 |
| 90 | |
| 91 | /* |
| 92 | * QSPI module. |
| 93 | */ |
| 94 | #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
| 95 | #define MCFQSPI_SIZE 0x40 |
| 96 | |
| 97 | #define MCFQSPI_CS0 91 |
| 98 | #define MCFQSPI_CS1 92 |
| 99 | #define MCFQSPI_CS2 103 |
| 100 | #define MCFQSPI_CS3 99 |
| 101 | |
| 102 | /* |
| 103 | * GPIO module. |
| 104 | */ |
| 105 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
| 106 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) |
| 107 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) |
| 108 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) |
| 109 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) |
| 110 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) |
| 111 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) |
| 112 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) |
| 113 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) |
| 114 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) |
| 115 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) |
| 116 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) |
| 117 | #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) |
| 118 | |
| 119 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) |
| 120 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) |
| 121 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) |
| 122 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) |
| 123 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) |
| 124 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) |
| 125 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) |
| 126 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) |
| 127 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) |
| 128 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) |
| 129 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) |
| 130 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) |
| 131 | #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) |
| 132 | |
| 133 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) |
| 134 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) |
| 135 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) |
| 136 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) |
| 137 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) |
| 138 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) |
| 139 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) |
| 140 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) |
| 141 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) |
| 142 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) |
| 143 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) |
| 144 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) |
| 145 | #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) |
| 146 | |
| 147 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) |
| 148 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) |
| 149 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) |
| 150 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) |
| 151 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) |
| 152 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) |
| 153 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) |
| 154 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) |
| 155 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) |
| 156 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) |
| 157 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) |
| 158 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) |
| 159 | #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) |
| 160 | |
| 161 | /* |
| 162 | * PIT timer base addresses. |
| 163 | */ |
| 164 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
| 165 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) |
| 166 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) |
| 167 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) |
| 168 | |
| 169 | /* |
| 170 | * EPort |
| 171 | */ |
| 172 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) |
| 173 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| 174 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) |
| 175 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| 176 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
| 177 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) |
| 178 | |
| 179 | /* |
| 180 | * Generic GPIO support |
| 181 | */ |
| 182 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR |
| 183 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR |
| 184 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR |
| 185 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR |
| 186 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR |
| 187 | |
| 188 | #define MCFGPIO_PIN_MAX 107 |
| 189 | #define MCFGPIO_IRQ_MAX 8 |
| 190 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 191 | |
| 192 | /* |
| 193 | * Pin Assignment |
| 194 | */ |
| 195 | #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) |
| 196 | #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) |
| 197 | #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) |
| 198 | #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) |
| 199 | #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) |
| 200 | #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) |
| 201 | #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) |
| 202 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) |
| 203 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) |
| 204 | #define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E) |
| 205 | |
| 206 | /* |
| 207 | * DMA unit base addresses. |
| 208 | */ |
| 209 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) |
| 210 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) |
| 211 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) |
| 212 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) |
| 213 | |
| 214 | /* |
| 215 | * I2C module. |
| 216 | */ |
| 217 | #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) |
| 218 | #define MCFI2C_SIZE0 0x40 |
| 219 | |
| 220 | /****************************************************************************/ |
| 221 | #endif /* m523xsim_h */ |