| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2015 John Crispin <john@phrozen.org> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _MT7621_REGS_H_ |
| 8 | #define _MT7621_REGS_H_ |
| 9 | |
| 10 | #define MT7621_PALMBUS_BASE 0x1C000000 |
| 11 | #define MT7621_PALMBUS_SIZE 0x03FFFFFF |
| 12 | |
| 13 | #define MT7621_SYSC_BASE 0x1E000000 |
| 14 | |
| 15 | #define SYSC_REG_CHIP_NAME0 0x00 |
| 16 | #define SYSC_REG_CHIP_NAME1 0x04 |
| 17 | #define SYSC_REG_CHIP_REV 0x0c |
| 18 | #define SYSC_REG_SYSTEM_CONFIG0 0x10 |
| 19 | #define SYSC_REG_SYSTEM_CONFIG1 0x14 |
| 20 | |
| 21 | #define CHIP_REV_PKG_MASK 0x1 |
| 22 | #define CHIP_REV_PKG_SHIFT 16 |
| 23 | #define CHIP_REV_VER_MASK 0xf |
| 24 | #define CHIP_REV_VER_SHIFT 8 |
| 25 | #define CHIP_REV_ECO_MASK 0xf |
| 26 | |
| 27 | #define MT7621_DRAM_BASE 0x0 |
| 28 | #define MT7621_DDR2_SIZE_MIN 32 |
| 29 | #define MT7621_DDR2_SIZE_MAX 256 |
| 30 | |
| 31 | #define MT7621_CHIP_NAME0 0x3637544D |
| 32 | #define MT7621_CHIP_NAME1 0x20203132 |
| 33 | |
| 34 | #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) |
| 35 | |
| 36 | #endif |