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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / arch / mips / include / asm / octeon / octeon-feature.h
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b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining checks for different Octeon features.
30 */
31
32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__
34#include <asm/octeon/cvmx-mio-defs.h>
35#include <asm/octeon/cvmx-rnm-defs.h>
36
37enum octeon_feature {
38 /* CN68XX uses port kinds for packet interface */
39 OCTEON_FEATURE_PKND,
40 /* CN68XX has different fields in word0 - word2 */
41 OCTEON_FEATURE_CN68XX_WQE,
42 /*
43 * Octeon models in the CN5XXX family and higher support
44 * atomic add instructions to memory (saa/saad).
45 */
46 OCTEON_FEATURE_SAAD,
47 /* Does this Octeon support the ZIP offload engine? */
48 OCTEON_FEATURE_ZIP,
49 OCTEON_FEATURE_DORM_CRYPTO,
50 /* Does this Octeon support PCI express? */
51 OCTEON_FEATURE_PCIE,
52 /* Does this Octeon support SRIOs */
53 OCTEON_FEATURE_SRIO,
54 /* Does this Octeon support Interlaken */
55 OCTEON_FEATURE_ILK,
56 /* Some Octeon models support internal memory for storing
57 * cryptographic keys */
58 OCTEON_FEATURE_KEY_MEMORY,
59 /* Octeon has a LED controller for banks of external LEDs */
60 OCTEON_FEATURE_LED_CONTROLLER,
61 /* Octeon has a trace buffer */
62 OCTEON_FEATURE_TRA,
63 /* Octeon has a management port */
64 OCTEON_FEATURE_MGMT_PORT,
65 /* Octeon has a raid unit */
66 OCTEON_FEATURE_RAID,
67 /* Octeon has a builtin USB */
68 OCTEON_FEATURE_USB,
69 /* Octeon IPD can run without using work queue entries */
70 OCTEON_FEATURE_NO_WPTR,
71 /* Octeon has DFA state machines */
72 OCTEON_FEATURE_DFA,
73 /* Octeon MDIO block supports clause 45 transactions for 10
74 * Gig support */
75 OCTEON_FEATURE_MDIO_CLAUSE_45,
76 /*
77 * CN52XX and CN56XX used a block named NPEI for PCIe
78 * access. Newer chips replaced this with SLI+DPI.
79 */
80 OCTEON_FEATURE_NPEI,
81 OCTEON_FEATURE_HFA,
82 OCTEON_FEATURE_DFM,
83 OCTEON_FEATURE_CIU2,
84 OCTEON_FEATURE_CIU3,
85 /* Octeon has FPA first seen on 78XX */
86 OCTEON_FEATURE_FPA3,
87 OCTEON_FEATURE_FAU,
88 OCTEON_MAX_FEATURE
89};
90
91enum octeon_feature_bits {
92 OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */
93};
94extern enum octeon_feature_bits __octeon_feature_bits;
95
96/**
97 * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
98 *
99 * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
100 */
101static inline int octeon_has_crypto(void)
102{
103 return __octeon_feature_bits & OCTEON_HAS_CRYPTO;
104}
105
106/**
107 * Determine if the current Octeon supports a specific feature. These
108 * checks have been optimized to be fairly quick, but they should still
109 * be kept out of fast path code.
110 *
111 * @feature: Feature to check for. This should always be a constant so the
112 * compiler can remove the switch statement through optimization.
113 *
114 * Returns Non zero if the feature exists. Zero if the feature does not
115 * exist.
116 */
117static inline bool octeon_has_feature(enum octeon_feature feature)
118{
119 switch (feature) {
120 case OCTEON_FEATURE_SAAD:
121 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
122
123 case OCTEON_FEATURE_DORM_CRYPTO:
124 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
125 union cvmx_mio_fus_dat2 fus_2;
126 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
127 return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
128 } else {
129 return false;
130 }
131
132 case OCTEON_FEATURE_PCIE:
133 return OCTEON_IS_MODEL(OCTEON_CN56XX)
134 || OCTEON_IS_MODEL(OCTEON_CN52XX)
135 || OCTEON_IS_MODEL(OCTEON_CN6XXX)
136 || OCTEON_IS_MODEL(OCTEON_CN7XXX);
137
138 case OCTEON_FEATURE_SRIO:
139 return OCTEON_IS_MODEL(OCTEON_CN63XX)
140 || OCTEON_IS_MODEL(OCTEON_CN66XX);
141
142 case OCTEON_FEATURE_ILK:
143 return (OCTEON_IS_MODEL(OCTEON_CN68XX));
144
145 case OCTEON_FEATURE_KEY_MEMORY:
146 return OCTEON_IS_MODEL(OCTEON_CN38XX)
147 || OCTEON_IS_MODEL(OCTEON_CN58XX)
148 || OCTEON_IS_MODEL(OCTEON_CN56XX)
149 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
150
151 case OCTEON_FEATURE_LED_CONTROLLER:
152 return OCTEON_IS_MODEL(OCTEON_CN38XX)
153 || OCTEON_IS_MODEL(OCTEON_CN58XX)
154 || OCTEON_IS_MODEL(OCTEON_CN56XX);
155
156 case OCTEON_FEATURE_TRA:
157 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
158 || OCTEON_IS_MODEL(OCTEON_CN50XX));
159 case OCTEON_FEATURE_MGMT_PORT:
160 return OCTEON_IS_MODEL(OCTEON_CN56XX)
161 || OCTEON_IS_MODEL(OCTEON_CN52XX)
162 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
163
164 case OCTEON_FEATURE_RAID:
165 return OCTEON_IS_MODEL(OCTEON_CN56XX)
166 || OCTEON_IS_MODEL(OCTEON_CN52XX)
167 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
168
169 case OCTEON_FEATURE_USB:
170 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
171 || OCTEON_IS_MODEL(OCTEON_CN58XX));
172
173 case OCTEON_FEATURE_NO_WPTR:
174 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
175 || OCTEON_IS_MODEL(OCTEON_CN52XX)
176 || OCTEON_IS_MODEL(OCTEON_CN6XXX))
177 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
178 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
179
180 case OCTEON_FEATURE_MDIO_CLAUSE_45:
181 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
182 || OCTEON_IS_MODEL(OCTEON_CN58XX)
183 || OCTEON_IS_MODEL(OCTEON_CN50XX));
184
185 case OCTEON_FEATURE_NPEI:
186 return OCTEON_IS_MODEL(OCTEON_CN56XX)
187 || OCTEON_IS_MODEL(OCTEON_CN52XX);
188
189 case OCTEON_FEATURE_PKND:
190 return OCTEON_IS_MODEL(OCTEON_CN68XX);
191
192 case OCTEON_FEATURE_CN68XX_WQE:
193 return OCTEON_IS_MODEL(OCTEON_CN68XX);
194
195 case OCTEON_FEATURE_CIU2:
196 return OCTEON_IS_MODEL(OCTEON_CN68XX);
197 case OCTEON_FEATURE_CIU3:
198 case OCTEON_FEATURE_FPA3:
199 return OCTEON_IS_MODEL(OCTEON_CN78XX)
200 || OCTEON_IS_MODEL(OCTEON_CNF75XX)
201 || OCTEON_IS_MODEL(OCTEON_CN73XX);
202 case OCTEON_FEATURE_FAU:
203 return !(OCTEON_IS_MODEL(OCTEON_CN78XX)
204 || OCTEON_IS_MODEL(OCTEON_CNF75XX)
205 || OCTEON_IS_MODEL(OCTEON_CN73XX));
206
207 default:
208 break;
209 }
210 return false;
211}
212
213#endif /* __OCTEON_FEATURE_H__ */