| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H |
| 3 | #define __ASM_SH_CPU_SH4_DMA_SH7780_H |
| 4 | |
| 5 | #include <linux/sh_intc.h> |
| 6 | |
| 7 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ |
| 8 | defined(CONFIG_CPU_SUBTYPE_SH7730) |
| 9 | #define DMTE0_IRQ evt2irq(0x800) |
| 10 | #define DMTE4_IRQ evt2irq(0xb80) |
| 11 | #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ |
| 12 | #define SH_DMAC_BASE0 0xFE008020 |
| 13 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 14 | #define DMTE0_IRQ evt2irq(0x800) |
| 15 | #define DMTE4_IRQ evt2irq(0xb80) |
| 16 | #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ |
| 17 | #define SH_DMAC_BASE0 0xFE008020 |
| 18 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 19 | #define DMTE0_IRQ evt2irq(0x640) |
| 20 | #define DMTE4_IRQ evt2irq(0x780) |
| 21 | #define DMAE0_IRQ evt2irq(0x6c0) |
| 22 | #define SH_DMAC_BASE0 0xFF608020 |
| 23 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 24 | #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ |
| 25 | #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ |
| 26 | #define DMTE6_IRQ evt2irq(0x700) |
| 27 | #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ |
| 28 | #define DMTE9_IRQ evt2irq(0x760) |
| 29 | #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ |
| 30 | #define DMTE11_IRQ evt2irq(0xb20) |
| 31 | #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ |
| 32 | #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ |
| 33 | #define SH_DMAC_BASE0 0xFE008020 |
| 34 | #define SH_DMAC_BASE1 0xFDC08020 |
| 35 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
| 36 | #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ |
| 37 | #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ |
| 38 | #define DMTE6_IRQ evt2irq(0x700) |
| 39 | #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ |
| 40 | #define DMTE9_IRQ evt2irq(0x760) |
| 41 | #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ |
| 42 | #define DMTE11_IRQ evt2irq(0xb20) |
| 43 | #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ |
| 44 | #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ |
| 45 | #define SH_DMAC_BASE0 0xFE008020 |
| 46 | #define SH_DMAC_BASE1 0xFDC08020 |
| 47 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 48 | #define DMTE0_IRQ evt2irq(0x640) |
| 49 | #define DMTE4_IRQ evt2irq(0x780) |
| 50 | #define DMTE6_IRQ evt2irq(0x7c0) |
| 51 | #define DMTE8_IRQ evt2irq(0xd80) |
| 52 | #define DMTE9_IRQ evt2irq(0xda0) |
| 53 | #define DMTE10_IRQ evt2irq(0xdc0) |
| 54 | #define DMTE11_IRQ evt2irq(0xde0) |
| 55 | #define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */ |
| 56 | #define SH_DMAC_BASE0 0xFC808020 |
| 57 | #define SH_DMAC_BASE1 0xFC818020 |
| 58 | #else /* SH7785 */ |
| 59 | #define DMTE0_IRQ evt2irq(0x620) |
| 60 | #define DMTE4_IRQ evt2irq(0x6a0) |
| 61 | #define DMTE6_IRQ evt2irq(0x880) |
| 62 | #define DMTE8_IRQ evt2irq(0x8c0) |
| 63 | #define DMTE9_IRQ evt2irq(0x8e0) |
| 64 | #define DMTE10_IRQ evt2irq(0x900) |
| 65 | #define DMTE11_IRQ evt2irq(0x920) |
| 66 | #define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */ |
| 67 | #define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */ |
| 68 | #define SH_DMAC_BASE0 0xFC808020 |
| 69 | #define SH_DMAC_BASE1 0xFCC08020 |
| 70 | #endif |
| 71 | |
| 72 | #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ |