| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef __ASM_SH_CPU_FEATURES_H |
| 3 | #define __ASM_SH_CPU_FEATURES_H |
| 4 | |
| 5 | /* |
| 6 | * Processor flags |
| 7 | * |
| 8 | * Note: When adding a new flag, keep cpu_flags[] in |
| 9 | * arch/sh/kernel/setup.c in sync so symbolic name |
| 10 | * mapping of the processor flags has a chance of being |
| 11 | * reasonably accurate. |
| 12 | * |
| 13 | * These flags are also available through the ELF |
| 14 | * auxiliary vector as AT_HWCAP. |
| 15 | */ |
| 16 | #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ |
| 17 | #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ |
| 18 | #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ |
| 19 | #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ |
| 20 | #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ |
| 21 | #define CPU_HAS_PTEA 0x0020 /* PTEA register */ |
| 22 | #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ |
| 23 | #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ |
| 24 | #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ |
| 25 | #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ |
| 26 | #define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ |
| 27 | |
| 28 | #endif /* __ASM_SH_CPU_FEATURES_H */ |