b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 |
| 4 | * |
| 5 | * Copyright (C) 2007 Magnus Damm |
| 6 | * Copyright (C) 2009 Paul Mundt |
| 7 | * |
| 8 | * Based on setup-sh7709.c |
| 9 | * |
| 10 | * Copyright (C) 2006 Paul Mundt |
| 11 | */ |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/irq.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/serial.h> |
| 17 | #include <linux/serial_sci.h> |
| 18 | #include <linux/sh_timer.h> |
| 19 | #include <linux/sh_intc.h> |
| 20 | #include <cpu/serial.h> |
| 21 | |
| 22 | enum { |
| 23 | UNUSED = 0, |
| 24 | |
| 25 | /* interrupt sources */ |
| 26 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, |
| 27 | PINT07, PINT815, |
| 28 | DMAC, SCIF0, SCIF2, SCI, ADC_ADI, |
| 29 | LCDC, PCC0, PCC1, |
| 30 | TMU0, TMU1, TMU2, |
| 31 | RTC, WDT, REF, |
| 32 | }; |
| 33 | |
| 34 | static struct intc_vect vectors[] __initdata = { |
| 35 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
| 36 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), |
| 37 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), |
| 38 | INTC_VECT(RTC, 0x4c0), |
| 39 | INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), |
| 40 | INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), |
| 41 | INTC_VECT(WDT, 0x560), |
| 42 | INTC_VECT(REF, 0x580), |
| 43 | INTC_VECT(REF, 0x5a0), |
| 44 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 45 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 46 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 47 | /* IRQ0->5 are handled in setup-sh3.c */ |
| 48 | INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), |
| 49 | INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), |
| 50 | INTC_VECT(ADC_ADI, 0x980), |
| 51 | INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), |
| 52 | INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), |
| 53 | #endif |
| 54 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 55 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 56 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), |
| 57 | INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), |
| 58 | INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), |
| 59 | #endif |
| 60 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) |
| 61 | INTC_VECT(LCDC, 0x9a0), |
| 62 | INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0), |
| 63 | #endif |
| 64 | }; |
| 65 | |
| 66 | static struct intc_prio_reg prio_registers[] __initdata = { |
| 67 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
| 68 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, |
| 69 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 70 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 71 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 72 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
| 73 | { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, |
| 74 | { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, |
| 75 | #endif |
| 76 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 77 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 78 | { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } }, |
| 79 | { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } }, |
| 80 | #endif |
| 81 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) |
| 82 | { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, |
| 83 | #endif |
| 84 | }; |
| 85 | |
| 86 | static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, |
| 87 | NULL, prio_registers, NULL); |
| 88 | |
| 89 | static struct resource rtc_resources[] = { |
| 90 | [0] = { |
| 91 | .start = 0xfffffec0, |
| 92 | .end = 0xfffffec0 + 0x1e, |
| 93 | .flags = IORESOURCE_IO, |
| 94 | }, |
| 95 | [1] = { |
| 96 | .start = evt2irq(0x480), |
| 97 | .flags = IORESOURCE_IRQ, |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | static struct platform_device rtc_device = { |
| 102 | .name = "sh-rtc", |
| 103 | .id = -1, |
| 104 | .num_resources = ARRAY_SIZE(rtc_resources), |
| 105 | .resource = rtc_resources, |
| 106 | }; |
| 107 | |
| 108 | static struct plat_sci_port scif0_platform_data = { |
| 109 | .type = PORT_SCI, |
| 110 | .ops = &sh770x_sci_port_ops, |
| 111 | }; |
| 112 | |
| 113 | static struct resource scif0_resources[] = { |
| 114 | DEFINE_RES_MEM(0xfffffe80, 0x10), |
| 115 | DEFINE_RES_IRQ(evt2irq(0x4e0)), |
| 116 | }; |
| 117 | |
| 118 | static struct platform_device scif0_device = { |
| 119 | .name = "sh-sci", |
| 120 | .id = 0, |
| 121 | .resource = scif0_resources, |
| 122 | .num_resources = ARRAY_SIZE(scif0_resources), |
| 123 | .dev = { |
| 124 | .platform_data = &scif0_platform_data, |
| 125 | }, |
| 126 | }; |
| 127 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 128 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 129 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 130 | static struct plat_sci_port scif1_platform_data = { |
| 131 | .type = PORT_SCIF, |
| 132 | .ops = &sh770x_sci_port_ops, |
| 133 | .regtype = SCIx_SH3_SCIF_REGTYPE, |
| 134 | }; |
| 135 | |
| 136 | static struct resource scif1_resources[] = { |
| 137 | DEFINE_RES_MEM(0xa4000150, 0x10), |
| 138 | DEFINE_RES_IRQ(evt2irq(0x900)), |
| 139 | }; |
| 140 | |
| 141 | static struct platform_device scif1_device = { |
| 142 | .name = "sh-sci", |
| 143 | .id = 1, |
| 144 | .resource = scif1_resources, |
| 145 | .num_resources = ARRAY_SIZE(scif1_resources), |
| 146 | .dev = { |
| 147 | .platform_data = &scif1_platform_data, |
| 148 | }, |
| 149 | }; |
| 150 | #endif |
| 151 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 152 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 153 | static struct plat_sci_port scif2_platform_data = { |
| 154 | .type = PORT_IRDA, |
| 155 | .ops = &sh770x_sci_port_ops, |
| 156 | }; |
| 157 | |
| 158 | static struct resource scif2_resources[] = { |
| 159 | DEFINE_RES_MEM(0xa4000140, 0x10), |
| 160 | DEFINE_RES_IRQ(evt2irq(0x880)), |
| 161 | }; |
| 162 | |
| 163 | static struct platform_device scif2_device = { |
| 164 | .name = "sh-sci", |
| 165 | .id = 2, |
| 166 | .resource = scif2_resources, |
| 167 | .num_resources = ARRAY_SIZE(scif2_resources), |
| 168 | .dev = { |
| 169 | .platform_data = &scif2_platform_data, |
| 170 | }, |
| 171 | }; |
| 172 | #endif |
| 173 | |
| 174 | static struct sh_timer_config tmu0_platform_data = { |
| 175 | .channels_mask = 7, |
| 176 | }; |
| 177 | |
| 178 | static struct resource tmu0_resources[] = { |
| 179 | DEFINE_RES_MEM(0xfffffe90, 0x2c), |
| 180 | DEFINE_RES_IRQ(evt2irq(0x400)), |
| 181 | DEFINE_RES_IRQ(evt2irq(0x420)), |
| 182 | DEFINE_RES_IRQ(evt2irq(0x440)), |
| 183 | }; |
| 184 | |
| 185 | static struct platform_device tmu0_device = { |
| 186 | .name = "sh-tmu-sh3", |
| 187 | .id = 0, |
| 188 | .dev = { |
| 189 | .platform_data = &tmu0_platform_data, |
| 190 | }, |
| 191 | .resource = tmu0_resources, |
| 192 | .num_resources = ARRAY_SIZE(tmu0_resources), |
| 193 | }; |
| 194 | |
| 195 | static struct platform_device *sh770x_devices[] __initdata = { |
| 196 | &scif0_device, |
| 197 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 198 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 199 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 200 | &scif1_device, |
| 201 | #endif |
| 202 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 203 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 204 | &scif2_device, |
| 205 | #endif |
| 206 | &tmu0_device, |
| 207 | &rtc_device, |
| 208 | }; |
| 209 | |
| 210 | static int __init sh770x_devices_setup(void) |
| 211 | { |
| 212 | return platform_add_devices(sh770x_devices, |
| 213 | ARRAY_SIZE(sh770x_devices)); |
| 214 | } |
| 215 | arch_initcall(sh770x_devices_setup); |
| 216 | |
| 217 | static struct platform_device *sh770x_early_devices[] __initdata = { |
| 218 | &scif0_device, |
| 219 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 220 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 221 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 222 | &scif1_device, |
| 223 | #endif |
| 224 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 225 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 226 | &scif2_device, |
| 227 | #endif |
| 228 | &tmu0_device, |
| 229 | }; |
| 230 | |
| 231 | void __init plat_early_device_setup(void) |
| 232 | { |
| 233 | early_platform_add_devices(sh770x_early_devices, |
| 234 | ARRAY_SIZE(sh770x_early_devices)); |
| 235 | } |
| 236 | |
| 237 | void __init plat_irq_setup(void) |
| 238 | { |
| 239 | register_intc_controller(&intc_desc); |
| 240 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 241 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 242 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 243 | plat_irq_setup_sh3(); |
| 244 | #endif |
| 245 | } |