b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * cppc_msr.c: MSR Interface for CPPC |
| 4 | * Copyright (c) 2016, Intel Corporation. |
| 5 | */ |
| 6 | |
| 7 | #include <acpi/cppc_acpi.h> |
| 8 | #include <asm/msr.h> |
| 9 | |
| 10 | /* Refer to drivers/acpi/cppc_acpi.c for the description of functions */ |
| 11 | |
| 12 | bool cpc_ffh_supported(void) |
| 13 | { |
| 14 | return true; |
| 15 | } |
| 16 | |
| 17 | int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) |
| 18 | { |
| 19 | int err; |
| 20 | |
| 21 | err = rdmsrl_safe_on_cpu(cpunum, reg->address, val); |
| 22 | if (!err) { |
| 23 | u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, |
| 24 | reg->bit_offset); |
| 25 | |
| 26 | *val &= mask; |
| 27 | *val >>= reg->bit_offset; |
| 28 | } |
| 29 | return err; |
| 30 | } |
| 31 | |
| 32 | int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) |
| 33 | { |
| 34 | u64 rd_val; |
| 35 | int err; |
| 36 | |
| 37 | err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val); |
| 38 | if (!err) { |
| 39 | u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, |
| 40 | reg->bit_offset); |
| 41 | |
| 42 | val <<= reg->bit_offset; |
| 43 | val &= mask; |
| 44 | rd_val &= ~mask; |
| 45 | rd_val |= val; |
| 46 | err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val); |
| 47 | } |
| 48 | return err; |
| 49 | } |