blob: faae8a1856709a9868ad8ae1ed23a142179b175b [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0-only
2#define pr_fmt(fmt) "SMP alternatives: " fmt
3
4#include <linux/module.h>
5#include <linux/sched.h>
6#include <linux/mutex.h>
7#include <linux/list.h>
8#include <linux/stringify.h>
9#include <linux/mm.h>
10#include <linux/vmalloc.h>
11#include <linux/memory.h>
12#include <linux/stop_machine.h>
13#include <linux/slab.h>
14#include <linux/kdebug.h>
15#include <linux/kprobes.h>
16#include <linux/mmu_context.h>
17#include <linux/bsearch.h>
18#include <asm/text-patching.h>
19#include <asm/alternative.h>
20#include <asm/sections.h>
21#include <asm/pgtable.h>
22#include <asm/mce.h>
23#include <asm/nmi.h>
24#include <asm/cacheflush.h>
25#include <asm/tlbflush.h>
26#include <asm/io.h>
27#include <asm/fixmap.h>
28
29int __read_mostly alternatives_patched;
30
31EXPORT_SYMBOL_GPL(alternatives_patched);
32
33#define MAX_PATCH_LEN (255-1)
34
35static int __initdata_or_module debug_alternative;
36
37static int __init debug_alt(char *str)
38{
39 debug_alternative = 1;
40 return 1;
41}
42__setup("debug-alternative", debug_alt);
43
44static int noreplace_smp;
45
46static int __init setup_noreplace_smp(char *str)
47{
48 noreplace_smp = 1;
49 return 1;
50}
51__setup("noreplace-smp", setup_noreplace_smp);
52
53#define DPRINTK(fmt, args...) \
54do { \
55 if (debug_alternative) \
56 printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
57} while (0)
58
59#define DUMP_BYTES(buf, len, fmt, args...) \
60do { \
61 if (unlikely(debug_alternative)) { \
62 int j; \
63 \
64 if (!(len)) \
65 break; \
66 \
67 printk(KERN_DEBUG fmt, ##args); \
68 for (j = 0; j < (len) - 1; j++) \
69 printk(KERN_CONT "%02hhx ", buf[j]); \
70 printk(KERN_CONT "%02hhx\n", buf[j]); \
71 } \
72} while (0)
73
74/*
75 * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
76 * that correspond to that nop. Getting from one nop to the next, we
77 * add to the array the offset that is equal to the sum of all sizes of
78 * nops preceding the one we are after.
79 *
80 * Note: The GENERIC_NOP5_ATOMIC is at the end, as it breaks the
81 * nice symmetry of sizes of the previous nops.
82 */
83#if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
84static const unsigned char intelnops[] =
85{
86 GENERIC_NOP1,
87 GENERIC_NOP2,
88 GENERIC_NOP3,
89 GENERIC_NOP4,
90 GENERIC_NOP5,
91 GENERIC_NOP6,
92 GENERIC_NOP7,
93 GENERIC_NOP8,
94 GENERIC_NOP5_ATOMIC
95};
96static const unsigned char * const intel_nops[ASM_NOP_MAX+2] =
97{
98 NULL,
99 intelnops,
100 intelnops + 1,
101 intelnops + 1 + 2,
102 intelnops + 1 + 2 + 3,
103 intelnops + 1 + 2 + 3 + 4,
104 intelnops + 1 + 2 + 3 + 4 + 5,
105 intelnops + 1 + 2 + 3 + 4 + 5 + 6,
106 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
107 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
108};
109#endif
110
111#ifdef K8_NOP1
112static const unsigned char k8nops[] =
113{
114 K8_NOP1,
115 K8_NOP2,
116 K8_NOP3,
117 K8_NOP4,
118 K8_NOP5,
119 K8_NOP6,
120 K8_NOP7,
121 K8_NOP8,
122 K8_NOP5_ATOMIC
123};
124static const unsigned char * const k8_nops[ASM_NOP_MAX+2] =
125{
126 NULL,
127 k8nops,
128 k8nops + 1,
129 k8nops + 1 + 2,
130 k8nops + 1 + 2 + 3,
131 k8nops + 1 + 2 + 3 + 4,
132 k8nops + 1 + 2 + 3 + 4 + 5,
133 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
134 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
135 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
136};
137#endif
138
139#if defined(K7_NOP1) && !defined(CONFIG_X86_64)
140static const unsigned char k7nops[] =
141{
142 K7_NOP1,
143 K7_NOP2,
144 K7_NOP3,
145 K7_NOP4,
146 K7_NOP5,
147 K7_NOP6,
148 K7_NOP7,
149 K7_NOP8,
150 K7_NOP5_ATOMIC
151};
152static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
153{
154 NULL,
155 k7nops,
156 k7nops + 1,
157 k7nops + 1 + 2,
158 k7nops + 1 + 2 + 3,
159 k7nops + 1 + 2 + 3 + 4,
160 k7nops + 1 + 2 + 3 + 4 + 5,
161 k7nops + 1 + 2 + 3 + 4 + 5 + 6,
162 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
163 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
164};
165#endif
166
167#ifdef P6_NOP1
168static const unsigned char p6nops[] =
169{
170 P6_NOP1,
171 P6_NOP2,
172 P6_NOP3,
173 P6_NOP4,
174 P6_NOP5,
175 P6_NOP6,
176 P6_NOP7,
177 P6_NOP8,
178 P6_NOP5_ATOMIC
179};
180static const unsigned char * const p6_nops[ASM_NOP_MAX+2] =
181{
182 NULL,
183 p6nops,
184 p6nops + 1,
185 p6nops + 1 + 2,
186 p6nops + 1 + 2 + 3,
187 p6nops + 1 + 2 + 3 + 4,
188 p6nops + 1 + 2 + 3 + 4 + 5,
189 p6nops + 1 + 2 + 3 + 4 + 5 + 6,
190 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
191 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
192};
193#endif
194
195/* Initialize these to a safe default */
196#ifdef CONFIG_X86_64
197const unsigned char * const *ideal_nops = p6_nops;
198#else
199const unsigned char * const *ideal_nops = intel_nops;
200#endif
201
202void __init arch_init_ideal_nops(void)
203{
204 switch (boot_cpu_data.x86_vendor) {
205 case X86_VENDOR_INTEL:
206 /*
207 * Due to a decoder implementation quirk, some
208 * specific Intel CPUs actually perform better with
209 * the "k8_nops" than with the SDM-recommended NOPs.
210 */
211 if (boot_cpu_data.x86 == 6 &&
212 boot_cpu_data.x86_model >= 0x0f &&
213 boot_cpu_data.x86_model != 0x1c &&
214 boot_cpu_data.x86_model != 0x26 &&
215 boot_cpu_data.x86_model != 0x27 &&
216 boot_cpu_data.x86_model < 0x30) {
217 ideal_nops = k8_nops;
218 } else if (boot_cpu_has(X86_FEATURE_NOPL)) {
219 ideal_nops = p6_nops;
220 } else {
221#ifdef CONFIG_X86_64
222 ideal_nops = k8_nops;
223#else
224 ideal_nops = intel_nops;
225#endif
226 }
227 break;
228
229 case X86_VENDOR_HYGON:
230 ideal_nops = p6_nops;
231 return;
232
233 case X86_VENDOR_AMD:
234 if (boot_cpu_data.x86 > 0xf) {
235 ideal_nops = p6_nops;
236 return;
237 }
238
239 /* fall through */
240
241 default:
242#ifdef CONFIG_X86_64
243 ideal_nops = k8_nops;
244#else
245 if (boot_cpu_has(X86_FEATURE_K8))
246 ideal_nops = k8_nops;
247 else if (boot_cpu_has(X86_FEATURE_K7))
248 ideal_nops = k7_nops;
249 else
250 ideal_nops = intel_nops;
251#endif
252 }
253}
254
255/* Use this to add nops to a buffer, then text_poke the whole buffer. */
256static void __init_or_module add_nops(void *insns, unsigned int len)
257{
258 while (len > 0) {
259 unsigned int noplen = len;
260 if (noplen > ASM_NOP_MAX)
261 noplen = ASM_NOP_MAX;
262 memcpy(insns, ideal_nops[noplen], noplen);
263 insns += noplen;
264 len -= noplen;
265 }
266}
267
268extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
269extern s32 __smp_locks[], __smp_locks_end[];
270void text_poke_early(void *addr, const void *opcode, size_t len);
271
272/*
273 * Are we looking at a near JMP with a 1 or 4-byte displacement.
274 */
275static inline bool is_jmp(const u8 opcode)
276{
277 return opcode == 0xeb || opcode == 0xe9;
278}
279
280static void __init_or_module
281recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insn_buff)
282{
283 u8 *next_rip, *tgt_rip;
284 s32 n_dspl, o_dspl;
285 int repl_len;
286
287 if (a->replacementlen != 5)
288 return;
289
290 o_dspl = *(s32 *)(insn_buff + 1);
291
292 /* next_rip of the replacement JMP */
293 next_rip = repl_insn + a->replacementlen;
294 /* target rip of the replacement JMP */
295 tgt_rip = next_rip + o_dspl;
296 n_dspl = tgt_rip - orig_insn;
297
298 DPRINTK("target RIP: %px, new_displ: 0x%x", tgt_rip, n_dspl);
299
300 if (tgt_rip - orig_insn >= 0) {
301 if (n_dspl - 2 <= 127)
302 goto two_byte_jmp;
303 else
304 goto five_byte_jmp;
305 /* negative offset */
306 } else {
307 if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
308 goto two_byte_jmp;
309 else
310 goto five_byte_jmp;
311 }
312
313two_byte_jmp:
314 n_dspl -= 2;
315
316 insn_buff[0] = 0xeb;
317 insn_buff[1] = (s8)n_dspl;
318 add_nops(insn_buff + 2, 3);
319
320 repl_len = 2;
321 goto done;
322
323five_byte_jmp:
324 n_dspl -= 5;
325
326 insn_buff[0] = 0xe9;
327 *(s32 *)&insn_buff[1] = n_dspl;
328
329 repl_len = 5;
330
331done:
332
333 DPRINTK("final displ: 0x%08x, JMP 0x%lx",
334 n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
335}
336
337/*
338 * "noinline" to cause control flow change and thus invalidate I$ and
339 * cause refetch after modification.
340 */
341static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 *instr)
342{
343 unsigned long flags;
344 int i;
345
346 for (i = 0; i < a->padlen; i++) {
347 if (instr[i] != 0x90)
348 return;
349 }
350
351 local_irq_save(flags);
352 add_nops(instr + (a->instrlen - a->padlen), a->padlen);
353 local_irq_restore(flags);
354
355 DUMP_BYTES(instr, a->instrlen, "%px: [%d:%d) optimized NOPs: ",
356 instr, a->instrlen - a->padlen, a->padlen);
357}
358
359/*
360 * Replace instructions with better alternatives for this CPU type. This runs
361 * before SMP is initialized to avoid SMP problems with self modifying code.
362 * This implies that asymmetric systems where APs have less capabilities than
363 * the boot processor are not handled. Tough. Make sure you disable such
364 * features by hand.
365 *
366 * Marked "noinline" to cause control flow change and thus insn cache
367 * to refetch changed I$ lines.
368 */
369void __init_or_module noinline apply_alternatives(struct alt_instr *start,
370 struct alt_instr *end)
371{
372 struct alt_instr *a;
373 u8 *instr, *replacement;
374 u8 insn_buff[MAX_PATCH_LEN];
375
376 DPRINTK("alt table %px, -> %px", start, end);
377
378 /*
379 * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
380 * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
381 * During the process, KASAN becomes confused seeing partial LA57
382 * conversion and triggers a false-positive out-of-bound report.
383 *
384 * Disable KASAN until the patching is complete.
385 */
386 kasan_disable_current();
387
388 /*
389 * The scan order should be from start to end. A later scanned
390 * alternative code can overwrite previously scanned alternative code.
391 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
392 * patch code.
393 *
394 * So be careful if you want to change the scan order to any other
395 * order.
396 */
397 for (a = start; a < end; a++) {
398 int insn_buff_sz = 0;
399
400 instr = (u8 *)&a->instr_offset + a->instr_offset;
401 replacement = (u8 *)&a->repl_offset + a->repl_offset;
402 BUG_ON(a->instrlen > sizeof(insn_buff));
403 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
404 if (!boot_cpu_has(a->cpuid)) {
405 if (a->padlen > 1)
406 optimize_nops(a, instr);
407
408 continue;
409 }
410
411 DPRINTK("feat: %d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d), pad: %d",
412 a->cpuid >> 5,
413 a->cpuid & 0x1f,
414 instr, instr, a->instrlen,
415 replacement, a->replacementlen, a->padlen);
416
417 DUMP_BYTES(instr, a->instrlen, "%px: old_insn: ", instr);
418 DUMP_BYTES(replacement, a->replacementlen, "%px: rpl_insn: ", replacement);
419
420 memcpy(insn_buff, replacement, a->replacementlen);
421 insn_buff_sz = a->replacementlen;
422
423 /*
424 * 0xe8 is a relative jump; fix the offset.
425 *
426 * Instruction length is checked before the opcode to avoid
427 * accessing uninitialized bytes for zero-length replacements.
428 */
429 if (a->replacementlen == 5 && *insn_buff == 0xe8) {
430 *(s32 *)(insn_buff + 1) += replacement - instr;
431 DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
432 *(s32 *)(insn_buff + 1),
433 (unsigned long)instr + *(s32 *)(insn_buff + 1) + 5);
434 }
435
436 if (a->replacementlen && is_jmp(replacement[0]))
437 recompute_jump(a, instr, replacement, insn_buff);
438
439 if (a->instrlen > a->replacementlen) {
440 add_nops(insn_buff + a->replacementlen,
441 a->instrlen - a->replacementlen);
442 insn_buff_sz += a->instrlen - a->replacementlen;
443 }
444 DUMP_BYTES(insn_buff, insn_buff_sz, "%px: final_insn: ", instr);
445
446 text_poke_early(instr, insn_buff, insn_buff_sz);
447 }
448
449 kasan_enable_current();
450}
451
452#ifdef CONFIG_SMP
453static void alternatives_smp_lock(const s32 *start, const s32 *end,
454 u8 *text, u8 *text_end)
455{
456 const s32 *poff;
457
458 for (poff = start; poff < end; poff++) {
459 u8 *ptr = (u8 *)poff + *poff;
460
461 if (!*poff || ptr < text || ptr >= text_end)
462 continue;
463 /* turn DS segment override prefix into lock prefix */
464 if (*ptr == 0x3e)
465 text_poke(ptr, ((unsigned char []){0xf0}), 1);
466 }
467}
468
469static void alternatives_smp_unlock(const s32 *start, const s32 *end,
470 u8 *text, u8 *text_end)
471{
472 const s32 *poff;
473
474 for (poff = start; poff < end; poff++) {
475 u8 *ptr = (u8 *)poff + *poff;
476
477 if (!*poff || ptr < text || ptr >= text_end)
478 continue;
479 /* turn lock prefix into DS segment override prefix */
480 if (*ptr == 0xf0)
481 text_poke(ptr, ((unsigned char []){0x3E}), 1);
482 }
483}
484
485struct smp_alt_module {
486 /* what is this ??? */
487 struct module *mod;
488 char *name;
489
490 /* ptrs to lock prefixes */
491 const s32 *locks;
492 const s32 *locks_end;
493
494 /* .text segment, needed to avoid patching init code ;) */
495 u8 *text;
496 u8 *text_end;
497
498 struct list_head next;
499};
500static LIST_HEAD(smp_alt_modules);
501static bool uniproc_patched = false; /* protected by text_mutex */
502
503void __init_or_module alternatives_smp_module_add(struct module *mod,
504 char *name,
505 void *locks, void *locks_end,
506 void *text, void *text_end)
507{
508 struct smp_alt_module *smp;
509
510 mutex_lock(&text_mutex);
511 if (!uniproc_patched)
512 goto unlock;
513
514 if (num_possible_cpus() == 1)
515 /* Don't bother remembering, we'll never have to undo it. */
516 goto smp_unlock;
517
518 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
519 if (NULL == smp)
520 /* we'll run the (safe but slow) SMP code then ... */
521 goto unlock;
522
523 smp->mod = mod;
524 smp->name = name;
525 smp->locks = locks;
526 smp->locks_end = locks_end;
527 smp->text = text;
528 smp->text_end = text_end;
529 DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
530 smp->locks, smp->locks_end,
531 smp->text, smp->text_end, smp->name);
532
533 list_add_tail(&smp->next, &smp_alt_modules);
534smp_unlock:
535 alternatives_smp_unlock(locks, locks_end, text, text_end);
536unlock:
537 mutex_unlock(&text_mutex);
538}
539
540void __init_or_module alternatives_smp_module_del(struct module *mod)
541{
542 struct smp_alt_module *item;
543
544 mutex_lock(&text_mutex);
545 list_for_each_entry(item, &smp_alt_modules, next) {
546 if (mod != item->mod)
547 continue;
548 list_del(&item->next);
549 kfree(item);
550 break;
551 }
552 mutex_unlock(&text_mutex);
553}
554
555void alternatives_enable_smp(void)
556{
557 struct smp_alt_module *mod;
558
559 /* Why bother if there are no other CPUs? */
560 BUG_ON(num_possible_cpus() == 1);
561
562 mutex_lock(&text_mutex);
563
564 if (uniproc_patched) {
565 pr_info("switching to SMP code\n");
566 BUG_ON(num_online_cpus() != 1);
567 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
568 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
569 list_for_each_entry(mod, &smp_alt_modules, next)
570 alternatives_smp_lock(mod->locks, mod->locks_end,
571 mod->text, mod->text_end);
572 uniproc_patched = false;
573 }
574 mutex_unlock(&text_mutex);
575}
576
577/*
578 * Return 1 if the address range is reserved for SMP-alternatives.
579 * Must hold text_mutex.
580 */
581int alternatives_text_reserved(void *start, void *end)
582{
583 struct smp_alt_module *mod;
584 const s32 *poff;
585 u8 *text_start = start;
586 u8 *text_end = end;
587
588 lockdep_assert_held(&text_mutex);
589
590 list_for_each_entry(mod, &smp_alt_modules, next) {
591 if (mod->text > text_end || mod->text_end < text_start)
592 continue;
593 for (poff = mod->locks; poff < mod->locks_end; poff++) {
594 const u8 *ptr = (const u8 *)poff + *poff;
595
596 if (text_start <= ptr && text_end > ptr)
597 return 1;
598 }
599 }
600
601 return 0;
602}
603#endif /* CONFIG_SMP */
604
605#ifdef CONFIG_PARAVIRT
606void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
607 struct paravirt_patch_site *end)
608{
609 struct paravirt_patch_site *p;
610 char insn_buff[MAX_PATCH_LEN];
611
612 for (p = start; p < end; p++) {
613 unsigned int used;
614
615 BUG_ON(p->len > MAX_PATCH_LEN);
616 /* prep the buffer with the original instructions */
617 memcpy(insn_buff, p->instr, p->len);
618 used = pv_ops.init.patch(p->type, insn_buff, (unsigned long)p->instr, p->len);
619
620 BUG_ON(used > p->len);
621
622 /* Pad the rest with nops */
623 add_nops(insn_buff + used, p->len - used);
624 text_poke_early(p->instr, insn_buff, p->len);
625 }
626}
627extern struct paravirt_patch_site __start_parainstructions[],
628 __stop_parainstructions[];
629#endif /* CONFIG_PARAVIRT */
630
631/*
632 * Self-test for the INT3 based CALL emulation code.
633 *
634 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
635 * properly and that there is a stack gap between the INT3 frame and the
636 * previous context. Without this gap doing a virtual PUSH on the interrupted
637 * stack would corrupt the INT3 IRET frame.
638 *
639 * See entry_{32,64}.S for more details.
640 */
641
642/*
643 * We define the int3_magic() function in assembly to control the calling
644 * convention such that we can 'call' it from assembly.
645 */
646
647extern void int3_magic(unsigned int *ptr); /* defined in asm */
648
649asm (
650" .pushsection .init.text, \"ax\", @progbits\n"
651" .type int3_magic, @function\n"
652"int3_magic:\n"
653" movl $1, (%" _ASM_ARG1 ")\n"
654" ret\n"
655" .size int3_magic, .-int3_magic\n"
656" .popsection\n"
657);
658
659extern __initdata unsigned long int3_selftest_ip; /* defined in asm below */
660
661static int __init
662int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
663{
664 struct die_args *args = data;
665 struct pt_regs *regs = args->regs;
666
667 if (!regs || user_mode(regs))
668 return NOTIFY_DONE;
669
670 if (val != DIE_INT3)
671 return NOTIFY_DONE;
672
673 if (regs->ip - INT3_INSN_SIZE != int3_selftest_ip)
674 return NOTIFY_DONE;
675
676 int3_emulate_call(regs, (unsigned long)&int3_magic);
677 return NOTIFY_STOP;
678}
679
680static void __init int3_selftest(void)
681{
682 static __initdata struct notifier_block int3_exception_nb = {
683 .notifier_call = int3_exception_notify,
684 .priority = INT_MAX-1, /* last */
685 };
686 unsigned int val = 0;
687
688 BUG_ON(register_die_notifier(&int3_exception_nb));
689
690 /*
691 * Basically: int3_magic(&val); but really complicated :-)
692 *
693 * Stick the address of the INT3 instruction into int3_selftest_ip,
694 * then trigger the INT3, padded with NOPs to match a CALL instruction
695 * length.
696 */
697 asm volatile ("1: int3; nop; nop; nop; nop\n\t"
698 ".pushsection .init.data,\"aw\"\n\t"
699 ".align " __ASM_SEL(4, 8) "\n\t"
700 ".type int3_selftest_ip, @object\n\t"
701 ".size int3_selftest_ip, " __ASM_SEL(4, 8) "\n\t"
702 "int3_selftest_ip:\n\t"
703 __ASM_SEL(.long, .quad) " 1b\n\t"
704 ".popsection\n\t"
705 : ASM_CALL_CONSTRAINT
706 : __ASM_SEL_RAW(a, D) (&val)
707 : "memory");
708
709 BUG_ON(val != 1);
710
711 unregister_die_notifier(&int3_exception_nb);
712}
713
714void __init alternative_instructions(void)
715{
716 int3_selftest();
717
718 /*
719 * The patching is not fully atomic, so try to avoid local
720 * interruptions that might execute the to be patched code.
721 * Other CPUs are not running.
722 */
723 stop_nmi();
724
725 /*
726 * Don't stop machine check exceptions while patching.
727 * MCEs only happen when something got corrupted and in this
728 * case we must do something about the corruption.
729 * Ignoring it is worse than an unlikely patching race.
730 * Also machine checks tend to be broadcast and if one CPU
731 * goes into machine check the others follow quickly, so we don't
732 * expect a machine check to cause undue problems during to code
733 * patching.
734 */
735
736 apply_alternatives(__alt_instructions, __alt_instructions_end);
737
738#ifdef CONFIG_SMP
739 /* Patch to UP if other cpus not imminent. */
740 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
741 uniproc_patched = true;
742 alternatives_smp_module_add(NULL, "core kernel",
743 __smp_locks, __smp_locks_end,
744 _text, _etext);
745 }
746
747 if (!uniproc_patched || num_possible_cpus() == 1) {
748 free_init_pages("SMP alternatives",
749 (unsigned long)__smp_locks,
750 (unsigned long)__smp_locks_end);
751 }
752#endif
753
754 apply_paravirt(__parainstructions, __parainstructions_end);
755
756 restart_nmi();
757 alternatives_patched = 1;
758}
759
760/**
761 * text_poke_early - Update instructions on a live kernel at boot time
762 * @addr: address to modify
763 * @opcode: source of the copy
764 * @len: length to copy
765 *
766 * When you use this code to patch more than one byte of an instruction
767 * you need to make sure that other CPUs cannot execute this code in parallel.
768 * Also no thread must be currently preempted in the middle of these
769 * instructions. And on the local CPU you need to be protected against NMI or
770 * MCE handlers seeing an inconsistent instruction while you patch.
771 */
772void __init_or_module text_poke_early(void *addr, const void *opcode,
773 size_t len)
774{
775 unsigned long flags;
776
777 if (boot_cpu_has(X86_FEATURE_NX) &&
778 is_module_text_address((unsigned long)addr)) {
779 /*
780 * Modules text is marked initially as non-executable, so the
781 * code cannot be running and speculative code-fetches are
782 * prevented. Just change the code.
783 */
784 memcpy(addr, opcode, len);
785 } else {
786 local_irq_save(flags);
787 memcpy(addr, opcode, len);
788 sync_core();
789 local_irq_restore(flags);
790
791 /*
792 * Could also do a CLFLUSH here to speed up CPU recovery; but
793 * that causes hangs on some VIA CPUs.
794 */
795 }
796}
797
798__ro_after_init struct mm_struct *poking_mm;
799__ro_after_init unsigned long poking_addr;
800
801static void *__text_poke(void *addr, const void *opcode, size_t len)
802{
803 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
804 struct page *pages[2] = {NULL};
805 temp_mm_state_t prev;
806 unsigned long flags;
807 pte_t pte, *ptep;
808 spinlock_t *ptl;
809 pgprot_t pgprot;
810
811 /*
812 * While boot memory allocator is running we cannot use struct pages as
813 * they are not yet initialized. There is no way to recover.
814 */
815 BUG_ON(!after_bootmem);
816
817 if (!core_kernel_text((unsigned long)addr)) {
818 pages[0] = vmalloc_to_page(addr);
819 if (cross_page_boundary)
820 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
821 } else {
822 pages[0] = virt_to_page(addr);
823 WARN_ON(!PageReserved(pages[0]));
824 if (cross_page_boundary)
825 pages[1] = virt_to_page(addr + PAGE_SIZE);
826 }
827 /*
828 * If something went wrong, crash and burn since recovery paths are not
829 * implemented.
830 */
831 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1]));
832
833 local_irq_save(flags);
834
835 /*
836 * Map the page without the global bit, as TLB flushing is done with
837 * flush_tlb_mm_range(), which is intended for non-global PTEs.
838 */
839 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL);
840
841 /*
842 * The lock is not really needed, but this allows to avoid open-coding.
843 */
844 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
845
846 /*
847 * This must not fail; preallocated in poking_init().
848 */
849 VM_BUG_ON(!ptep);
850
851 pte = mk_pte(pages[0], pgprot);
852 set_pte_at(poking_mm, poking_addr, ptep, pte);
853
854 if (cross_page_boundary) {
855 pte = mk_pte(pages[1], pgprot);
856 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
857 }
858
859 /*
860 * Loading the temporary mm behaves as a compiler barrier, which
861 * guarantees that the PTE will be set at the time memcpy() is done.
862 */
863 prev = use_temporary_mm(poking_mm);
864
865 kasan_disable_current();
866 memcpy((u8 *)poking_addr + offset_in_page(addr), opcode, len);
867 kasan_enable_current();
868
869 /*
870 * Ensure that the PTE is only cleared after the instructions of memcpy
871 * were issued by using a compiler barrier.
872 */
873 barrier();
874
875 pte_clear(poking_mm, poking_addr, ptep);
876 if (cross_page_boundary)
877 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
878
879 /*
880 * Loading the previous page-table hierarchy requires a serializing
881 * instruction that already allows the core to see the updated version.
882 * Xen-PV is assumed to serialize execution in a similar manner.
883 */
884 unuse_temporary_mm(prev);
885
886 /*
887 * Flushing the TLB might involve IPIs, which would require enabled
888 * IRQs, but not if the mm is not used, as it is in this point.
889 */
890 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr +
891 (cross_page_boundary ? 2 : 1) * PAGE_SIZE,
892 PAGE_SHIFT, false);
893
894 /*
895 * If the text does not match what we just wrote then something is
896 * fundamentally screwy; there's nothing we can really do about that.
897 */
898 BUG_ON(memcmp(addr, opcode, len));
899
900 pte_unmap_unlock(ptep, ptl);
901 local_irq_restore(flags);
902 return addr;
903}
904
905/**
906 * text_poke - Update instructions on a live kernel
907 * @addr: address to modify
908 * @opcode: source of the copy
909 * @len: length to copy
910 *
911 * Only atomic text poke/set should be allowed when not doing early patching.
912 * It means the size must be writable atomically and the address must be aligned
913 * in a way that permits an atomic write. It also makes sure we fit on a single
914 * page.
915 *
916 * Note that the caller must ensure that if the modified code is part of a
917 * module, the module would not be removed during poking. This can be achieved
918 * by registering a module notifier, and ordering module removal and patching
919 * trough a mutex.
920 */
921void *text_poke(void *addr, const void *opcode, size_t len)
922{
923 lockdep_assert_held(&text_mutex);
924
925 return __text_poke(addr, opcode, len);
926}
927
928/**
929 * text_poke_kgdb - Update instructions on a live kernel by kgdb
930 * @addr: address to modify
931 * @opcode: source of the copy
932 * @len: length to copy
933 *
934 * Only atomic text poke/set should be allowed when not doing early patching.
935 * It means the size must be writable atomically and the address must be aligned
936 * in a way that permits an atomic write. It also makes sure we fit on a single
937 * page.
938 *
939 * Context: should only be used by kgdb, which ensures no other core is running,
940 * despite the fact it does not hold the text_mutex.
941 */
942void *text_poke_kgdb(void *addr, const void *opcode, size_t len)
943{
944 return __text_poke(addr, opcode, len);
945}
946
947static void do_sync_core(void *info)
948{
949 sync_core();
950}
951
952static struct bp_patching_desc {
953 struct text_poke_loc *vec;
954 int nr_entries;
955} bp_patching;
956
957static int patch_cmp(const void *key, const void *elt)
958{
959 struct text_poke_loc *tp = (struct text_poke_loc *) elt;
960
961 if (key < tp->addr)
962 return -1;
963 if (key > tp->addr)
964 return 1;
965 return 0;
966}
967NOKPROBE_SYMBOL(patch_cmp);
968
969int poke_int3_handler(struct pt_regs *regs)
970{
971 struct text_poke_loc *tp;
972 unsigned char int3 = 0xcc;
973 void *ip;
974
975 /*
976 * Having observed our INT3 instruction, we now must observe
977 * bp_patching.nr_entries.
978 *
979 * nr_entries != 0 INT3
980 * WMB RMB
981 * write INT3 if (nr_entries)
982 *
983 * Idem for other elements in bp_patching.
984 */
985 smp_rmb();
986
987 if (likely(!bp_patching.nr_entries))
988 return 0;
989
990 if (user_mode(regs))
991 return 0;
992
993 /*
994 * Discount the sizeof(int3). See text_poke_bp_batch().
995 */
996 ip = (void *) regs->ip - sizeof(int3);
997
998 /*
999 * Skip the binary search if there is a single member in the vector.
1000 */
1001 if (unlikely(bp_patching.nr_entries > 1)) {
1002 tp = bsearch(ip, bp_patching.vec, bp_patching.nr_entries,
1003 sizeof(struct text_poke_loc),
1004 patch_cmp);
1005 if (!tp)
1006 return 0;
1007 } else {
1008 tp = bp_patching.vec;
1009 if (tp->addr != ip)
1010 return 0;
1011 }
1012
1013 /* set up the specified breakpoint detour */
1014 regs->ip = (unsigned long) tp->detour;
1015
1016 return 1;
1017}
1018NOKPROBE_SYMBOL(poke_int3_handler);
1019
1020/**
1021 * text_poke_bp_batch() -- update instructions on live kernel on SMP
1022 * @tp: vector of instructions to patch
1023 * @nr_entries: number of entries in the vector
1024 *
1025 * Modify multi-byte instruction by using int3 breakpoint on SMP.
1026 * We completely avoid stop_machine() here, and achieve the
1027 * synchronization using int3 breakpoint.
1028 *
1029 * The way it is done:
1030 * - For each entry in the vector:
1031 * - add a int3 trap to the address that will be patched
1032 * - sync cores
1033 * - For each entry in the vector:
1034 * - update all but the first byte of the patched range
1035 * - sync cores
1036 * - For each entry in the vector:
1037 * - replace the first byte (int3) by the first byte of
1038 * replacing opcode
1039 * - sync cores
1040 */
1041void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries)
1042{
1043 int patched_all_but_first = 0;
1044 unsigned char int3 = 0xcc;
1045 unsigned int i;
1046
1047 lockdep_assert_held(&text_mutex);
1048
1049 bp_patching.vec = tp;
1050 bp_patching.nr_entries = nr_entries;
1051
1052 /*
1053 * Corresponding read barrier in int3 notifier for making sure the
1054 * nr_entries and handler are correctly ordered wrt. patching.
1055 */
1056 smp_wmb();
1057
1058 /*
1059 * First step: add a int3 trap to the address that will be patched.
1060 */
1061 for (i = 0; i < nr_entries; i++)
1062 text_poke(tp[i].addr, &int3, sizeof(int3));
1063
1064 on_each_cpu(do_sync_core, NULL, 1);
1065
1066 /*
1067 * Second step: update all but the first byte of the patched range.
1068 */
1069 for (i = 0; i < nr_entries; i++) {
1070 if (tp[i].len - sizeof(int3) > 0) {
1071 text_poke((char *)tp[i].addr + sizeof(int3),
1072 (const char *)tp[i].opcode + sizeof(int3),
1073 tp[i].len - sizeof(int3));
1074 patched_all_but_first++;
1075 }
1076 }
1077
1078 if (patched_all_but_first) {
1079 /*
1080 * According to Intel, this core syncing is very likely
1081 * not necessary and we'd be safe even without it. But
1082 * better safe than sorry (plus there's not only Intel).
1083 */
1084 on_each_cpu(do_sync_core, NULL, 1);
1085 }
1086
1087 /*
1088 * Third step: replace the first byte (int3) by the first byte of
1089 * replacing opcode.
1090 */
1091 for (i = 0; i < nr_entries; i++)
1092 text_poke(tp[i].addr, tp[i].opcode, sizeof(int3));
1093
1094 on_each_cpu(do_sync_core, NULL, 1);
1095 /*
1096 * sync_core() implies an smp_mb() and orders this store against
1097 * the writing of the new instruction.
1098 */
1099 bp_patching.vec = NULL;
1100 bp_patching.nr_entries = 0;
1101}
1102
1103/**
1104 * text_poke_bp() -- update instructions on live kernel on SMP
1105 * @addr: address to patch
1106 * @opcode: opcode of new instruction
1107 * @len: length to copy
1108 * @handler: address to jump to when the temporary breakpoint is hit
1109 *
1110 * Update a single instruction with the vector in the stack, avoiding
1111 * dynamically allocated memory. This function should be used when it is
1112 * not possible to allocate memory.
1113 */
1114void text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
1115{
1116 struct text_poke_loc tp = {
1117 .detour = handler,
1118 .addr = addr,
1119 .len = len,
1120 };
1121
1122 if (len > POKE_MAX_OPCODE_SIZE) {
1123 WARN_ONCE(1, "len is larger than %d\n", POKE_MAX_OPCODE_SIZE);
1124 return;
1125 }
1126
1127 memcpy((void *)tp.opcode, opcode, len);
1128
1129 text_poke_bp_batch(&tp, 1);
1130}