blob: fac50ebb122b5471966f34ecf474ff834da420eb [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0
2#include <linux/io.h>
3#include <linux/slab.h>
4#include <linux/memblock.h>
5#include <linux/mem_encrypt.h>
6
7#include <asm/set_memory.h>
8#include <asm/pgtable.h>
9#include <asm/realmode.h>
10#include <asm/tlbflush.h>
11#include <asm/crash.h>
12
13struct real_mode_header *real_mode_header;
14u32 *trampoline_cr4_features;
15
16/* Hold the pgd entry used on booting additional CPUs */
17pgd_t trampoline_pgd_entry;
18
19void load_trampoline_pgtable(void)
20{
21#ifdef CONFIG_X86_32
22 load_cr3(initial_page_table);
23#else
24 /*
25 * This function is called before exiting to real-mode and that will
26 * fail with CR4.PCIDE still set.
27 */
28 if (boot_cpu_has(X86_FEATURE_PCID))
29 cr4_clear_bits(X86_CR4_PCIDE);
30
31 write_cr3(real_mode_header->trampoline_pgd);
32#endif
33
34 /*
35 * The CR3 write above will not flush global TLB entries.
36 * Stale, global entries from previous page tables may still be
37 * present. Flush those stale entries.
38 *
39 * This ensures that memory accessed while running with
40 * trampoline_pgd is *actually* mapped into trampoline_pgd.
41 */
42 __flush_tlb_all();
43}
44
45void __init reserve_real_mode(void)
46{
47 phys_addr_t mem;
48 size_t size = real_mode_size_needed();
49
50 if (!size)
51 return;
52
53 WARN_ON(slab_is_available());
54
55 /* Has to be under 1M so we can execute real-mode AP code. */
56 mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE);
57 if (!mem) {
58 pr_info("No sub-1M memory is available for the trampoline\n");
59 return;
60 }
61
62 memblock_reserve(mem, size);
63 set_real_mode_mem(mem);
64 crash_reserve_low_1M();
65}
66
67static void __init setup_real_mode(void)
68{
69 u16 real_mode_seg;
70 const u32 *rel;
71 u32 count;
72 unsigned char *base;
73 unsigned long phys_base;
74 struct trampoline_header *trampoline_header;
75 size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
76#ifdef CONFIG_X86_64
77 u64 *trampoline_pgd;
78 u64 efer;
79 int i;
80#endif
81
82 base = (unsigned char *)real_mode_header;
83
84 /*
85 * If SME is active, the trampoline area will need to be in
86 * decrypted memory in order to bring up other processors
87 * successfully. This is not needed for SEV.
88 */
89 if (sme_active())
90 set_memory_decrypted((unsigned long)base, size >> PAGE_SHIFT);
91
92 memcpy(base, real_mode_blob, size);
93
94 phys_base = __pa(base);
95 real_mode_seg = phys_base >> 4;
96
97 rel = (u32 *) real_mode_relocs;
98
99 /* 16-bit segment relocations. */
100 count = *rel++;
101 while (count--) {
102 u16 *seg = (u16 *) (base + *rel++);
103 *seg = real_mode_seg;
104 }
105
106 /* 32-bit linear relocations. */
107 count = *rel++;
108 while (count--) {
109 u32 *ptr = (u32 *) (base + *rel++);
110 *ptr += phys_base;
111 }
112
113 /* Must be perfomed *after* relocation. */
114 trampoline_header = (struct trampoline_header *)
115 __va(real_mode_header->trampoline_header);
116
117#ifdef CONFIG_X86_32
118 trampoline_header->start = __pa_symbol(startup_32_smp);
119 trampoline_header->gdt_limit = __BOOT_DS + 7;
120 trampoline_header->gdt_base = __pa_symbol(boot_gdt);
121#else
122 /*
123 * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
124 * so we need to mask it out.
125 */
126 rdmsrl(MSR_EFER, efer);
127 trampoline_header->efer = efer & ~EFER_LMA;
128
129 trampoline_header->start = (u64) secondary_startup_64;
130 trampoline_cr4_features = &trampoline_header->cr4;
131 *trampoline_cr4_features = mmu_cr4_features;
132
133 trampoline_header->flags = 0;
134 if (sme_active())
135 trampoline_header->flags |= TH_FLAGS_SME_ACTIVE;
136
137 trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd);
138
139 /* Map the real mode stub as virtual == physical */
140 trampoline_pgd[0] = trampoline_pgd_entry.pgd;
141
142 /*
143 * Include the entirety of the kernel mapping into the trampoline
144 * PGD. This way, all mappings present in the normal kernel page
145 * tables are usable while running on trampoline_pgd.
146 */
147 for (i = pgd_index(__PAGE_OFFSET); i < PTRS_PER_PGD; i++)
148 trampoline_pgd[i] = init_top_pgt[i].pgd;
149#endif
150}
151
152/*
153 * reserve_real_mode() gets called very early, to guarantee the
154 * availability of low memory. This is before the proper kernel page
155 * tables are set up, so we cannot set page permissions in that
156 * function. Also trampoline code will be executed by APs so we
157 * need to mark it executable at do_pre_smp_initcalls() at least,
158 * thus run it as a early_initcall().
159 */
160static void __init set_real_mode_permissions(void)
161{
162 unsigned char *base = (unsigned char *) real_mode_header;
163 size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
164
165 size_t ro_size =
166 PAGE_ALIGN(real_mode_header->ro_end) -
167 __pa(base);
168
169 size_t text_size =
170 PAGE_ALIGN(real_mode_header->ro_end) -
171 real_mode_header->text_start;
172
173 unsigned long text_start =
174 (unsigned long) __va(real_mode_header->text_start);
175
176 set_memory_nx((unsigned long) base, size >> PAGE_SHIFT);
177 set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT);
178 set_memory_x((unsigned long) text_start, text_size >> PAGE_SHIFT);
179}
180
181static int __init init_real_mode(void)
182{
183 if (!real_mode_header)
184 panic("Real mode trampoline was not allocated");
185
186 setup_real_mode();
187 set_real_mode_permissions();
188
189 return 0;
190}
191early_initcall(init_real_mode);