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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / ata / ahci.h
blob: bb1e52212f644c2407fe17f7ac070bbf4fa66a09 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * ahci.h - Common AHCI SATA definitions and declarations
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#ifndef _AHCI_H
20#define _AHCI_H
21
22#include <linux/pci.h>
23#include <linux/clk.h>
24#include <linux/libata.h>
25#include <linux/phy/phy.h>
26#include <linux/regulator/consumer.h>
27#include <linux/bits.h>
28
29/* Enclosure Management Control */
30#define EM_CTRL_MSG_TYPE 0x000f0000
31
32/* Enclosure Management LED Message Type */
33#define EM_MSG_LED_HBA_PORT 0x0000000f
34#define EM_MSG_LED_PMP_SLOT 0x0000ff00
35#define EM_MSG_LED_VALUE 0xffff0000
36#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
37#define EM_MSG_LED_VALUE_OFF 0xfff80000
38#define EM_MSG_LED_VALUE_ON 0x00010000
39
40enum {
41 AHCI_MAX_PORTS = 32,
42 AHCI_MAX_CLKS = 5,
43 AHCI_MAX_SG = 168, /* hardware max is 64K */
44 AHCI_DMA_BOUNDARY = 0xffffffff,
45 AHCI_MAX_CMDS = 32,
46 AHCI_CMD_SZ = 32,
47 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
48 AHCI_RX_FIS_SZ = 256,
49 AHCI_CMD_TBL_CDB = 0x40,
50 AHCI_CMD_TBL_HDR_SZ = 0x80,
51 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
52 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
53 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
54 AHCI_RX_FIS_SZ,
55 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
56 AHCI_CMD_TBL_AR_SZ +
57 (AHCI_RX_FIS_SZ * 16),
58 AHCI_IRQ_ON_SG = BIT(31),
59 AHCI_CMD_ATAPI = BIT(5),
60 AHCI_CMD_WRITE = BIT(6),
61 AHCI_CMD_PREFETCH = BIT(7),
62 AHCI_CMD_RESET = BIT(8),
63 AHCI_CMD_CLR_BUSY = BIT(10),
64
65 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
66 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
67 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
68 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
69
70 /* global controller registers */
71 HOST_CAP = 0x00, /* host capabilities */
72 HOST_CTL = 0x04, /* global host control */
73 HOST_IRQ_STAT = 0x08, /* interrupt status */
74 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
75 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
76 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
77 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
78 HOST_CAP2 = 0x24, /* host capabilities, extended */
79
80 /* HOST_CTL bits */
81 HOST_RESET = BIT(0), /* reset controller; self-clear */
82 HOST_IRQ_EN = BIT(1), /* global IRQ enable */
83 HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
84 HOST_AHCI_EN = BIT(31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_SXS = BIT(5), /* Supports External SATA */
88 HOST_CAP_EMS = BIT(6), /* Enclosure Management support */
89 HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */
90 HOST_CAP_PART = BIT(13), /* Partial state capable */
91 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
92 HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */
93 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
94 HOST_CAP_PMP = BIT(17), /* Port Multiplier support */
95 HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */
96 HOST_CAP_CLO = BIT(24), /* Command List Override support */
97 HOST_CAP_LED = BIT(25), /* Supports activity LED */
98 HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */
99 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
100 HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */
101 HOST_CAP_SNTF = BIT(29), /* SNotification register */
102 HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */
103 HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
104
105 /* HOST_CAP2 bits */
106 HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */
107 HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */
108 HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */
109 HOST_CAP2_SDS = BIT(3), /* Support device sleep */
110 HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */
111 HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */
112
113 /* registers for each SATA port */
114 PORT_LST_ADDR = 0x00, /* command list DMA addr */
115 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
116 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
117 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
118 PORT_IRQ_STAT = 0x10, /* interrupt status */
119 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
120 PORT_CMD = 0x18, /* port command */
121 PORT_TFDATA = 0x20, /* taskfile data */
122 PORT_SIG = 0x24, /* device TF signature */
123 PORT_CMD_ISSUE = 0x38, /* command issue */
124 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
125 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
126 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
127 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
128 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
129 PORT_FBS = 0x40, /* FIS-based Switching */
130 PORT_DEVSLP = 0x44, /* device sleep */
131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = BIT(30), /* task file error */
135 PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */
137 PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */
144 PORT_IRQ_CONNECT = BIT(6), /* port connect change status */
145 PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */
151
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
155 PORT_IRQ_PHYRDY |
156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
164
165 /* PORT_CMD bits */
166 PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */
169 PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */
170 PORT_CMD_ESP = BIT(21), /* External Sata Port */
171 PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */
172 PORT_CMD_PMP = BIT(17), /* PMP attached */
173 PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */
174 PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */
175 PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */
176 PORT_CMD_CLO = BIT(3), /* Command list override */
177 PORT_CMD_POWER_ON = BIT(2), /* Power up device */
178 PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */
179 PORT_CMD_START = BIT(0), /* Enable port DMA engine */
180
181 PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */
182 PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */
183 PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */
184 PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */
185
186 /* PORT_FBS bits */
187 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
188 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
189 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
190 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
191 PORT_FBS_SDE = BIT(2), /* FBS single device error */
192 PORT_FBS_DEC = BIT(1), /* FBS device error clear */
193 PORT_FBS_EN = BIT(0), /* Enable FBS */
194
195 /* PORT_DEVSLP bits */
196 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
197 PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
198 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
199 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
200 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
201 PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */
202 PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */
203
204 /* hpriv->flags bits */
205
206#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
207
208 AHCI_HFLAG_NO_NCQ = BIT(0),
209 AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */
210 AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */
211 AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */
212 AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */
213 AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */
214 AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */
215 AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */
216 AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */
217 AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */
218 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as
219 link offline */
220 AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */
221 AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */
222 AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */
223 AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on
224 port start (wait until
225 error-handling stage) */
226 AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */
227 AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */
228
229#ifdef CONFIG_PCI_MSI
230 AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */
231#else
232 /* compile out MSI infrastructure */
233 AHCI_HFLAG_MULTI_MSI = 0,
234#endif
235 AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */
236 AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */
237 AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read
238 only registers */
239 AHCI_HFLAG_IS_MOBILE = BIT(25), /* mobile chipset, use
240 SATA_MOBILE_LPM_POLICY
241 as default lpm_policy */
242 AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during
243 suspend/resume */
244 AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = BIT(27), /* ignore -EOPNOTSUPP
245 from phy_power_on() */
246 AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */
247 AHCI_HFLAG_43BIT_ONLY = BIT(29), /* 43bit DMA addr limit */
248
249 /* ap->flags bits */
250
251 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
252 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
253
254 ICH_MAP = 0x90, /* ICH MAP register */
255 PCS_6 = 0x92, /* 6 port PCS */
256 PCS_7 = 0x94, /* 7+ port PCS (Denverton) */
257
258 /* em constants */
259 EM_MAX_SLOTS = SATA_PMP_MAX_PORTS,
260 EM_MAX_RETRY = 5,
261
262 /* em_ctl bits */
263 EM_CTL_RST = BIT(9), /* Reset */
264 EM_CTL_TM = BIT(8), /* Transmit Message */
265 EM_CTL_MR = BIT(0), /* Message Received */
266 EM_CTL_ALHD = BIT(26), /* Activity LED */
267 EM_CTL_XMT = BIT(25), /* Transmit Only */
268 EM_CTL_SMB = BIT(24), /* Single Message Buffer */
269 EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */
270 EM_CTL_SES = BIT(18), /* SES-2 messages supported */
271 EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */
272 EM_CTL_LED = BIT(16), /* LED messages supported */
273
274 /* em message type */
275 EM_MSG_TYPE_LED = BIT(0), /* LED */
276 EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */
277 EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */
278 EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */
279};
280
281struct ahci_cmd_hdr {
282 __le32 opts;
283 __le32 status;
284 __le32 tbl_addr;
285 __le32 tbl_addr_hi;
286 __le32 reserved[4];
287};
288
289struct ahci_sg {
290 __le32 addr;
291 __le32 addr_hi;
292 __le32 reserved;
293 __le32 flags_size;
294};
295
296struct ahci_em_priv {
297 enum sw_activity blink_policy;
298 struct timer_list timer;
299 unsigned long saved_activity;
300 unsigned long activity;
301 unsigned long led_state;
302 struct ata_link *link;
303};
304
305struct ahci_port_priv {
306 struct ata_link *active_link;
307 struct ahci_cmd_hdr *cmd_slot;
308 dma_addr_t cmd_slot_dma;
309 void *cmd_tbl;
310 dma_addr_t cmd_tbl_dma;
311 void *rx_fis;
312 dma_addr_t rx_fis_dma;
313 /* for NCQ spurious interrupt analysis */
314 unsigned int ncq_saw_d2h:1;
315 unsigned int ncq_saw_dmas:1;
316 unsigned int ncq_saw_sdb:1;
317 spinlock_t lock; /* protects parent ata_port */
318 u32 intr_mask; /* interrupts to enable */
319 bool fbs_supported; /* set iff FBS is supported */
320 bool fbs_enabled; /* set iff FBS is enabled */
321 int fbs_last_dev; /* save FBS.DEV of last FIS */
322 /* enclosure management info per PM slot */
323 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
324 char *irq_desc; /* desc in /proc/interrupts */
325};
326
327struct ahci_host_priv {
328 /* Input fields */
329 unsigned int flags; /* AHCI_HFLAG_* */
330 u32 force_port_map; /* force port map */
331 u32 mask_port_map; /* mask out particular bits */
332
333 void __iomem * mmio; /* bus-independent mem map */
334 u32 cap; /* cap to use */
335 u32 cap2; /* cap2 to use */
336 u32 version; /* cached version */
337 u32 port_map; /* port map to use */
338 u32 saved_cap; /* saved initial cap */
339 u32 saved_cap2; /* saved initial cap2 */
340 u32 saved_port_map; /* saved initial port_map */
341 u32 em_loc; /* enclosure management location */
342 u32 em_buf_sz; /* EM buffer size in byte */
343 u32 em_msg_type; /* EM message type */
344 bool got_runtime_pm; /* Did we do pm_runtime_get? */
345 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
346 struct reset_control *rsts; /* Optional */
347 struct regulator **target_pwrs; /* Optional */
348 struct regulator *ahci_regulator;/* Optional */
349 struct regulator *phy_regulator;/* Optional */
350 /*
351 * If platform uses PHYs. There is a 1:1 relation between the port number and
352 * the PHY position in this array.
353 */
354 struct phy **phys;
355 unsigned nports; /* Number of ports */
356 void *plat_data; /* Other platform data */
357 unsigned int irq; /* interrupt line */
358 /*
359 * Optional ahci_start_engine override, if not set this gets set to the
360 * default ahci_start_engine during ahci_save_initial_config, this can
361 * be overridden anytime before the host is activated.
362 */
363 void (*start_engine)(struct ata_port *ap);
364 /*
365 * Optional ahci_stop_engine override, if not set this gets set to the
366 * default ahci_stop_engine during ahci_save_initial_config, this can
367 * be overridden anytime before the host is activated.
368 */
369 int (*stop_engine)(struct ata_port *ap);
370
371 irqreturn_t (*irq_handler)(int irq, void *dev_instance);
372
373 /* only required for per-port MSI(-X) support */
374 int (*get_irq_vector)(struct ata_host *host,
375 int port);
376};
377
378extern int ahci_ignore_sss;
379
380extern struct device_attribute *ahci_shost_attrs[];
381extern struct device_attribute *ahci_sdev_attrs[];
382
383/*
384 * This must be instantiated by the edge drivers. Read the comments
385 * for ATA_BASE_SHT
386 */
387#define AHCI_SHT(drv_name) \
388 ATA_NCQ_SHT(drv_name), \
389 .can_queue = AHCI_MAX_CMDS, \
390 .sg_tablesize = AHCI_MAX_SG, \
391 .dma_boundary = AHCI_DMA_BOUNDARY, \
392 .shost_attrs = ahci_shost_attrs, \
393 .sdev_attrs = ahci_sdev_attrs
394
395extern struct ata_port_operations ahci_ops;
396extern struct ata_port_operations ahci_platform_ops;
397extern struct ata_port_operations ahci_pmp_retry_srst_ops;
398
399unsigned int ahci_dev_classify(struct ata_port *ap);
400void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
401 u32 opts);
402void ahci_save_initial_config(struct device *dev,
403 struct ahci_host_priv *hpriv);
404void ahci_init_controller(struct ata_host *host);
405int ahci_reset_controller(struct ata_host *host);
406
407int ahci_do_softreset(struct ata_link *link, unsigned int *class,
408 int pmp, unsigned long deadline,
409 int (*check_ready)(struct ata_link *link));
410
411int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
412 unsigned long deadline, bool *online);
413
414unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
415int ahci_stop_engine(struct ata_port *ap);
416void ahci_start_fis_rx(struct ata_port *ap);
417void ahci_start_engine(struct ata_port *ap);
418int ahci_check_ready(struct ata_link *link);
419int ahci_kick_engine(struct ata_port *ap);
420int ahci_port_resume(struct ata_port *ap);
421void ahci_set_em_messages(struct ahci_host_priv *hpriv,
422 struct ata_port_info *pi);
423int ahci_reset_em(struct ata_host *host);
424void ahci_print_info(struct ata_host *host, const char *scc_s);
425int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
426void ahci_error_handler(struct ata_port *ap);
427u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
428
429static inline void __iomem *__ahci_port_base(struct ata_host *host,
430 unsigned int port_no)
431{
432 struct ahci_host_priv *hpriv = host->private_data;
433 void __iomem *mmio = hpriv->mmio;
434
435 return mmio + 0x100 + (port_no * 0x80);
436}
437
438static inline void __iomem *ahci_port_base(struct ata_port *ap)
439{
440 return __ahci_port_base(ap->host, ap->port_no);
441}
442
443static inline int ahci_nr_ports(u32 cap)
444{
445 return (cap & 0x1f) + 1;
446}
447
448#endif /* _AHCI_H */