| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Amlogic Meson-AXG Clock Controller Driver |
| 4 | * |
| 5 | * Copyright (c) 2016 BayLibre, SAS. |
| 6 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 7 | * |
| 8 | * Copyright (c) 2018 Amlogic, inc. |
| 9 | * Author: Qiufang Dai <qiufang.dai@amlogic.com> |
| 10 | * Author: Yixun Lan <yixun.lan@amlogic.com> |
| 11 | */ |
| 12 | |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/reset-controller.h> |
| 15 | #include <linux/mfd/syscon.h> |
| 16 | #include <linux/of_device.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include "meson-aoclk.h" |
| 19 | |
| 20 | static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev, |
| 21 | unsigned long id) |
| 22 | { |
| 23 | struct meson_aoclk_reset_controller *rstc = |
| 24 | container_of(rcdev, struct meson_aoclk_reset_controller, reset); |
| 25 | |
| 26 | return regmap_write(rstc->regmap, rstc->data->reset_reg, |
| 27 | BIT(rstc->data->reset[id])); |
| 28 | } |
| 29 | |
| 30 | static const struct reset_control_ops meson_aoclk_reset_ops = { |
| 31 | .reset = meson_aoclk_do_reset, |
| 32 | }; |
| 33 | |
| 34 | int meson_aoclkc_probe(struct platform_device *pdev) |
| 35 | { |
| 36 | struct meson_aoclk_reset_controller *rstc; |
| 37 | struct meson_aoclk_data *data; |
| 38 | struct device *dev = &pdev->dev; |
| 39 | struct device_node *np; |
| 40 | struct regmap *regmap; |
| 41 | int ret, clkid; |
| 42 | |
| 43 | data = (struct meson_aoclk_data *) of_device_get_match_data(dev); |
| 44 | if (!data) |
| 45 | return -ENODEV; |
| 46 | |
| 47 | rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); |
| 48 | if (!rstc) |
| 49 | return -ENOMEM; |
| 50 | |
| 51 | np = of_get_parent(dev->of_node); |
| 52 | regmap = syscon_node_to_regmap(np); |
| 53 | of_node_put(np); |
| 54 | if (IS_ERR(regmap)) { |
| 55 | dev_err(dev, "failed to get regmap\n"); |
| 56 | return PTR_ERR(regmap); |
| 57 | } |
| 58 | |
| 59 | /* Reset Controller */ |
| 60 | rstc->data = data; |
| 61 | rstc->regmap = regmap; |
| 62 | rstc->reset.ops = &meson_aoclk_reset_ops; |
| 63 | rstc->reset.nr_resets = data->num_reset, |
| 64 | rstc->reset.of_node = dev->of_node; |
| 65 | ret = devm_reset_controller_register(dev, &rstc->reset); |
| 66 | if (ret) { |
| 67 | dev_err(dev, "failed to register reset controller\n"); |
| 68 | return ret; |
| 69 | } |
| 70 | |
| 71 | /* Populate regmap */ |
| 72 | for (clkid = 0; clkid < data->num_clks; clkid++) |
| 73 | data->clks[clkid]->map = regmap; |
| 74 | |
| 75 | /* Register all clks */ |
| 76 | for (clkid = 0; clkid < data->hw_data->num; clkid++) { |
| 77 | if (!data->hw_data->hws[clkid]) |
| 78 | continue; |
| 79 | |
| 80 | ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]); |
| 81 | if (ret) { |
| 82 | dev_err(dev, "Clock registration failed\n"); |
| 83 | return ret; |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, |
| 88 | (void *) data->hw_data); |
| 89 | } |