blob: 04ab3f587ee2b906fc6e43db6aa5ac152b91f208 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001/* SPDX-License-Identifier: GPL-2.0 */
2//
3// Spreadtrum composite clock driver
4//
5// Copyright (C) 2017 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7
8#ifndef _SPRD_COMPOSITE_H_
9#define _SPRD_COMPOSITE_H_
10
11#include "common.h"
12#include "mux.h"
13#include "div.h"
14
15struct sprd_comp {
16 struct sprd_mux_ssel mux;
17 struct sprd_div_internal div;
18 struct sprd_clk_common common;
19};
20
21#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
22 _mshift, _mwidth, _dshift, _dwidth, _flags) \
23 struct sprd_comp _struct = { \
24 .mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
25 .div = _SPRD_DIV_CLK(_dshift, _dwidth), \
26 .common = { \
27 .regmap = NULL, \
28 .reg = _reg, \
29 .hw.init = CLK_HW_INIT_PARENTS(_name, \
30 _parent, \
31 &sprd_comp_ops, \
32 _flags), \
33 } \
34 }
35
36#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
37 _mwidth, _dshift, _dwidth, _flags) \
38 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
39 NULL, _mshift, _mwidth, \
40 _dshift, _dwidth, _flags)
41
42static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
43{
44 struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
45
46 return container_of(common, struct sprd_comp, common);
47}
48
49extern const struct clk_ops sprd_comp_ops;
50
51#endif /* _SPRD_COMPOSITE_H_ */