marvell/linux/drivers/crypto/asr/te200/asr-cipher.h

#ifndef ASR_CIPHER_H
#define ASR_CIPHER_H

#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/crypto.h>
#include <crypto/aes.h>
#include <crypto/scatterwalk.h>
#include <crypto/algapi.h>
#include <crypto/internal/skcipher.h>

/* CIHER flags */
#define FLAGS_ENCRYPT		(1 << 0)
#define FLAGS_ECB			(0 << 1)
#define FLAGS_CBC			(1 << 1)
#define FLAGS_CTR			(2 << 1)
#define FLAGS_OPMODE_MASK 	(3 << 1)
#define FLAGS_BUSY			(1 << 3)
#define FLAGS_AES			(0 << 4)
#define FLAGS_SM4			(1 << 4)

#define CIPHER_FLAGS_PERSISTENT	FLAGS_BUSY

#define ASR_CIPHER_QUEUE_LENGTH	50
#define ASR_CIPHER_PRIORITY		300

#define ASR_CIPHER_BUFFER_ORDER	2
#define ASR_CIPHER_BUFFER_SIZE	(PAGE_SIZE << ASR_CIPHER_BUFFER_ORDER)

enum SCA_MODE {
	NORMAL_AES = 0,
	SM4
};

enum SCA_ALG_STANDARD {
	ECB = 0,
	CTR,
	CBC,
	CBC_MAC,
	CMAC,
	GHASH,
};

struct sca_data {
	int encrypt;
	int alg_type;
	int mode;
	int is_last_blk;
	bool use_rkek;
};

struct asr_te200_cipher;

typedef int (*asr_cipher_fn_t)(struct asr_te200_cipher *dd);
typedef irqreturn_t (*asr_cipher_irq_t)(void *);


struct asr_cipher_ctx {
	struct asr_te200_cipher	*dd;
	asr_cipher_fn_t		    start;
	int			            keylen;
	u32			            key[AES_KEYSIZE_256 / sizeof(u32)];
	u16			            block_size;
	bool		            use_rkek;
};

struct asr_cipher_reqctx {
	unsigned long		mode;
	bool		use_rkek;
	u32			lastc[AES_BLOCK_SIZE / sizeof(u32)];
};

struct asr_te200_cipher {
	struct device		*dev;
	struct crypto_async_request	*areq;

	void __iomem		*io_base;
	unsigned long		phys_base;

	struct asr_cipher_ctx	*ctx;

	bool			is_async;
	bool			rkek_burned;
	unsigned long		flags;

	spinlock_t		lock;
	struct mutex cipher_lock;
	struct crypto_queue	queue;
	struct tasklet_struct	queue_task;

	asr_cipher_fn_t		resume;
	struct tasklet_struct	done_task;

	size_t			total;
	size_t			datalen;
	u32			*data;

	size_t			buflen;
	void			*buf;

	struct scatterlist	aligned_sg;
	struct scatterlist	*real_dst;
};

#endif