marvell/linux/drivers/crypto/asr/te200/asr-te200.h

#ifndef _TE200_H_
#define _TE200_H_

#include "asr-cipher.h"
#include "asr-sha.h"
#include "./asr-aca/se_rsa.h"

#define TE200_CTRL                 0x0000
#define TE200_CLOCK_CTRL           (TE200_CTRL+0x00)
#define TE200_RESET_CTRL           (TE200_CTRL+0x04)

#define TE200_STATUS               0x0100
#define TE200_INIT_STATUS_HOST0    (TE200_STATUS+0x10)

#define DMA_AHB_CLK_EN      	   (1 << 5)
#define TMG_CLK_EN          	   (1 << 4)
#define OTP_CLK_EN          	   (1 << 3)
#define ACA_CLK_EN          	   (1 << 2)
#define SCA_CLK_EN          	   (1 << 1)
#define HASH_CLK_EN         	   (1 << 0)

/* OTP registers */
#define TE200_OTP_MANAGER          0x0400
#define TE200_OTP_SPACE            0x1000
#define TE200_OTP_DUMMY_CFG		   (TE200_OTP_MANAGER+0x28)

/* SECURE SCA registers */
#define TE200_SSCA_QUEUE           0x3200
#define TE200_SSCA_CTRL	           0x3204
#define TE200_SSCA_STAT            0x3208
#define TE200_SSCA_INTR_STAT       0x320C
#define TE200_SSCA_INTR_MSK        0x3210
#define TE200_SSCA_SUSP_MSK        0x3214

/* sca queue register bits */
#define SCA_INIT_CMD       (0x80 << 24)
#define SCA_PROCESS_CMD    (0x40 << 24)
#define SCA_FINISH_CMD     (0x20 << 24)

/* sca intr msk register */
#define WM_INTR_MSK         (1 << 4)
#define BUS_RROR_MSK        (1 << 3)
#define INVALID_KEY_MSK     (1 << 2)
#define INVALID_CMD_MSK     (1 << 1)
#define CMD_INIR_MSK        (1 << 0)

/* sca queue registers bits */
#define SCA_INTER_TRIGGERD     (1 << 0)

/* sca ctrl registers bits */
#define SCA_RUN             (1 << 0)

/* sca intr stat registers bits */
#define SCA_WM_INTR         (1 << 4)
#define SCA_BUS_ERROR       (1 << 3)
#define SCA_INVALID_KEY     (1 << 2)
#define SCA_INVALID_CMD     (1 << 1)
#define SCA_CMD_INTR        (1 << 0)

/* sca queue: sca init */
#define SCA_MODEL_KEY           (~(1 << 22))
#define SCA_DEVICE_ROOT_KEY     (1 << 22)
#define SCA_EXTERNAL_KEY        (2 << 22)

#define SCA_KEY_128_BITS        (~(1 << 20))
#define SCA_KEY_192_BITS        (1 << 20)
#define SCA_KEY_256_BITS        (2 << 20)

#define SCA_NORMAL_AES          (~(1 << 19))
#define SCA_SM4                 (1 << 19)
#define SCA_KEY_IS_ADDR         (1 << 18)
#define SCA_SET_IV              (1 << 15)
#define SCA_SET_IV_ADDR         (1 << 14)

#define SCA_MODE_ECB            (~(1 << 4))
#define SCA_MODE_CTR            (1 << 4)
#define SCA_MODE_CBC            (2 << 4)
#define SCA_MODE_CBC_MAC        (3 << 4)
#define SCA_MODE_CMAC           (4 << 4)
#define SCA_MODE_GHASH          (5 << 4)

/* sca queue: sca process */
#define SCA_LAST_ONE_SESSION    (1 << 6)
#define SCA_ENCRYPTION          (1 << 5)

/* SECURE HASH registers  */
#define TE200_SHASH_QUEUE  		 	0x3280
#define TE200_SHASH_CTRL			0x3284
#define TE200_SHASH_STAT			0x3288
#define TE200_SHASH_INTR_STAT		0x328C
#define TE200_SHASH_INTR_MSK		0x3290
#define TE200_SHASH_SUSP_MSK		0x3294

/* hash queue register bits */
#define HASH_INIT_CMD       (0x80 << 24)
#define HASH_PROCESS_CMD    (0x40 << 24)
#define HASH_FINISH_CMD     (0x20 << 24)

/* hash queue registers bits */
#define HASH_INTER_TRIGGERD     (1 << 0)

/* scahash ctrl registers bits */
#define HASH_RUN             	(1 << 0)

/* hash queue: hash init */
#define HASH_MODE_SHA1			(~(1 << 5))
#define HASH_MODE_SHA224		(1 << 5)
#define HASH_MODE_SHA256		(2 << 5)
#define HASH_MODE_SM3			(3 << 5)

#define HASH_SET_EXT_IV	        (1 << 4)
#define HASH_PARAM_IS_ADDR      (1 << 3)

/* hash queue: hash process */
#define HASH_LITTLE_ENDIAN		(1 << 1)

/* hash queue: hash finish */
#define HASH_PADDING			(1 << 7)

/* hash intr stat registers bits */
#define HASH_WM_INTR         (1 << 4)
#define HASH_BUS_ERROR       (1 << 3)
#define HASH_PADDING_ERROR   (1 << 2)
#define HASH_INVALID_CMD     (1 << 1)
#define HASH_CMD_INTR        (1 << 0)



struct asr_te200_dev {
	unsigned long		phys_base;
	void __iomem		*io_base;
	struct mutex		te200_lock;
	struct device		*dev;

	struct clk		*te200_clk;
	int			clk_synced;
	refcount_t	refcount;

	struct asr_te200_cipher asr_cipher;
	struct asr_te200_sha asr_sha;
	struct asr_te200_rsa asr_rsa;

	struct asr_te200_ops	*te200_ops;
};

struct asr_te200_ops {
	int (*dev_get)(struct asr_te200_dev *);
	int (*dev_put)(struct asr_te200_dev *);
};

int asr_te200_cipher_register(struct asr_te200_dev *te200_dd);
int asr_te200_cipher_unregister(struct asr_te200_dev *te200_dd);

int asr_te200_sha_register(struct asr_te200_dev *te200_dd);
int asr_te200_sha_unregister(struct asr_te200_dev *te200_dd);

int asr_te200_rsa_register(struct asr_te200_dev *te200_dd);
int asr_te200_rsa_unregister(struct asr_te200_dev *te200_dd);
#endif