blob: 2db88213f13e28478016af5c1ed0b59b470a6ba1 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * caam - Freescale FSL CAAM support for crypto API
4 *
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Copyright 2016-2019 NXP
7 *
8 * Based on talitos crypto API driver.
9 *
10 * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
11 *
12 * --------------- ---------------
13 * | JobDesc #1 |-------------------->| ShareDesc |
14 * | *(packet 1) | | (PDB) |
15 * --------------- |------------->| (hashKey) |
16 * . | | (cipherKey) |
17 * . | |-------->| (operation) |
18 * --------------- | | ---------------
19 * | JobDesc #2 |------| |
20 * | *(packet 2) | |
21 * --------------- |
22 * . |
23 * . |
24 * --------------- |
25 * | JobDesc #3 |------------
26 * | *(packet 3) |
27 * ---------------
28 *
29 * The SharedDesc never changes for a connection unless rekeyed, but
30 * each packet will likely be in a different place. So all we need
31 * to know to process the packet is where the input is, where the
32 * output goes, and what context we want to process with. Context is
33 * in the SharedDesc, packet references in the JobDesc.
34 *
35 * So, a job desc looks like:
36 *
37 * ---------------------
38 * | Header |
39 * | ShareDesc Pointer |
40 * | SEQ_OUT_PTR |
41 * | (output buffer) |
42 * | (output length) |
43 * | SEQ_IN_PTR |
44 * | (input buffer) |
45 * | (input length) |
46 * ---------------------
47 */
48
49#include "compat.h"
50
51#include "regs.h"
52#include "intern.h"
53#include "desc_constr.h"
54#include "jr.h"
55#include "error.h"
56#include "sg_sw_sec4.h"
57#include "key_gen.h"
58#include "caamalg_desc.h"
59
60/*
61 * crypto alg
62 */
63#define CAAM_CRA_PRIORITY 3000
64/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
65#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
66 CTR_RFC3686_NONCE_SIZE + \
67 SHA512_DIGEST_SIZE * 2)
68
69#define AEAD_DESC_JOB_IO_LEN (DESC_JOB_IO_LEN + CAAM_CMD_SZ * 2)
70#define GCM_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
71 CAAM_CMD_SZ * 4)
72#define AUTHENC_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + \
73 CAAM_CMD_SZ * 5)
74
75#define CHACHAPOLY_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + CAAM_CMD_SZ * 6)
76
77#define DESC_MAX_USED_BYTES (CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN)
78#define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
79
80struct caam_alg_entry {
81 int class1_alg_type;
82 int class2_alg_type;
83 bool rfc3686;
84 bool geniv;
85 bool nodkp;
86};
87
88struct caam_aead_alg {
89 struct aead_alg aead;
90 struct caam_alg_entry caam;
91 bool registered;
92};
93
94struct caam_skcipher_alg {
95 struct skcipher_alg skcipher;
96 struct caam_alg_entry caam;
97 bool registered;
98};
99
100/*
101 * per-session context
102 */
103struct caam_ctx {
104 u32 sh_desc_enc[DESC_MAX_USED_LEN];
105 u32 sh_desc_dec[DESC_MAX_USED_LEN];
106 u8 key[CAAM_MAX_KEY_SIZE];
107 dma_addr_t sh_desc_enc_dma;
108 dma_addr_t sh_desc_dec_dma;
109 dma_addr_t key_dma;
110 enum dma_data_direction dir;
111 struct device *jrdev;
112 struct alginfo adata;
113 struct alginfo cdata;
114 unsigned int authsize;
115};
116
117static int aead_null_set_sh_desc(struct crypto_aead *aead)
118{
119 struct caam_ctx *ctx = crypto_aead_ctx(aead);
120 struct device *jrdev = ctx->jrdev;
121 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
122 u32 *desc;
123 int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN -
124 ctx->adata.keylen_pad;
125
126 /*
127 * Job Descriptor and Shared Descriptors
128 * must all fit into the 64-word Descriptor h/w Buffer
129 */
130 if (rem_bytes >= DESC_AEAD_NULL_ENC_LEN) {
131 ctx->adata.key_inline = true;
132 ctx->adata.key_virt = ctx->key;
133 } else {
134 ctx->adata.key_inline = false;
135 ctx->adata.key_dma = ctx->key_dma;
136 }
137
138 /* aead_encrypt shared descriptor */
139 desc = ctx->sh_desc_enc;
140 cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize,
141 ctrlpriv->era);
142 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
143 desc_bytes(desc), ctx->dir);
144
145 /*
146 * Job Descriptor and Shared Descriptors
147 * must all fit into the 64-word Descriptor h/w Buffer
148 */
149 if (rem_bytes >= DESC_AEAD_NULL_DEC_LEN) {
150 ctx->adata.key_inline = true;
151 ctx->adata.key_virt = ctx->key;
152 } else {
153 ctx->adata.key_inline = false;
154 ctx->adata.key_dma = ctx->key_dma;
155 }
156
157 /* aead_decrypt shared descriptor */
158 desc = ctx->sh_desc_dec;
159 cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize,
160 ctrlpriv->era);
161 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
162 desc_bytes(desc), ctx->dir);
163
164 return 0;
165}
166
167static int aead_set_sh_desc(struct crypto_aead *aead)
168{
169 struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
170 struct caam_aead_alg, aead);
171 unsigned int ivsize = crypto_aead_ivsize(aead);
172 struct caam_ctx *ctx = crypto_aead_ctx(aead);
173 struct device *jrdev = ctx->jrdev;
174 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
175 u32 ctx1_iv_off = 0;
176 u32 *desc, *nonce = NULL;
177 u32 inl_mask;
178 unsigned int data_len[2];
179 const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
180 OP_ALG_AAI_CTR_MOD128);
181 const bool is_rfc3686 = alg->caam.rfc3686;
182
183 if (!ctx->authsize)
184 return 0;
185
186 /* NULL encryption / decryption */
187 if (!ctx->cdata.keylen)
188 return aead_null_set_sh_desc(aead);
189
190 /*
191 * AES-CTR needs to load IV in CONTEXT1 reg
192 * at an offset of 128bits (16bytes)
193 * CONTEXT1[255:128] = IV
194 */
195 if (ctr_mode)
196 ctx1_iv_off = 16;
197
198 /*
199 * RFC3686 specific:
200 * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
201 */
202 if (is_rfc3686) {
203 ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
204 nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
205 ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
206 }
207
208 /*
209 * In case |user key| > |derived key|, using DKP<imm,imm>
210 * would result in invalid opcodes (last bytes of user key) in
211 * the resulting descriptor. Use DKP<ptr,imm> instead => both
212 * virtual and dma key addresses are needed.
213 */
214 ctx->adata.key_virt = ctx->key;
215 ctx->adata.key_dma = ctx->key_dma;
216
217 ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
218 ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
219
220 data_len[0] = ctx->adata.keylen_pad;
221 data_len[1] = ctx->cdata.keylen;
222
223 if (alg->caam.geniv)
224 goto skip_enc;
225
226 /*
227 * Job Descriptor and Shared Descriptors
228 * must all fit into the 64-word Descriptor h/w Buffer
229 */
230 if (desc_inline_query(DESC_AEAD_ENC_LEN +
231 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
232 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
233 ARRAY_SIZE(data_len)) < 0)
234 return -EINVAL;
235
236 ctx->adata.key_inline = !!(inl_mask & 1);
237 ctx->cdata.key_inline = !!(inl_mask & 2);
238
239 /* aead_encrypt shared descriptor */
240 desc = ctx->sh_desc_enc;
241 cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
242 ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
243 false, ctrlpriv->era);
244 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
245 desc_bytes(desc), ctx->dir);
246
247skip_enc:
248 /*
249 * Job Descriptor and Shared Descriptors
250 * must all fit into the 64-word Descriptor h/w Buffer
251 */
252 if (desc_inline_query(DESC_AEAD_DEC_LEN +
253 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
254 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
255 ARRAY_SIZE(data_len)) < 0)
256 return -EINVAL;
257
258 ctx->adata.key_inline = !!(inl_mask & 1);
259 ctx->cdata.key_inline = !!(inl_mask & 2);
260
261 /* aead_decrypt shared descriptor */
262 desc = ctx->sh_desc_dec;
263 cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
264 ctx->authsize, alg->caam.geniv, is_rfc3686,
265 nonce, ctx1_iv_off, false, ctrlpriv->era);
266 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
267 desc_bytes(desc), ctx->dir);
268
269 if (!alg->caam.geniv)
270 goto skip_givenc;
271
272 /*
273 * Job Descriptor and Shared Descriptors
274 * must all fit into the 64-word Descriptor h/w Buffer
275 */
276 if (desc_inline_query(DESC_AEAD_GIVENC_LEN +
277 (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
278 AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
279 ARRAY_SIZE(data_len)) < 0)
280 return -EINVAL;
281
282 ctx->adata.key_inline = !!(inl_mask & 1);
283 ctx->cdata.key_inline = !!(inl_mask & 2);
284
285 /* aead_givencrypt shared descriptor */
286 desc = ctx->sh_desc_enc;
287 cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
288 ctx->authsize, is_rfc3686, nonce,
289 ctx1_iv_off, false, ctrlpriv->era);
290 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
291 desc_bytes(desc), ctx->dir);
292
293skip_givenc:
294 return 0;
295}
296
297static int aead_setauthsize(struct crypto_aead *authenc,
298 unsigned int authsize)
299{
300 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
301
302 ctx->authsize = authsize;
303 aead_set_sh_desc(authenc);
304
305 return 0;
306}
307
308static int gcm_set_sh_desc(struct crypto_aead *aead)
309{
310 struct caam_ctx *ctx = crypto_aead_ctx(aead);
311 struct device *jrdev = ctx->jrdev;
312 unsigned int ivsize = crypto_aead_ivsize(aead);
313 u32 *desc;
314 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
315 ctx->cdata.keylen;
316
317 if (!ctx->cdata.keylen || !ctx->authsize)
318 return 0;
319
320 /*
321 * AES GCM encrypt shared descriptor
322 * Job Descriptor and Shared Descriptor
323 * must fit into the 64-word Descriptor h/w Buffer
324 */
325 if (rem_bytes >= DESC_GCM_ENC_LEN) {
326 ctx->cdata.key_inline = true;
327 ctx->cdata.key_virt = ctx->key;
328 } else {
329 ctx->cdata.key_inline = false;
330 ctx->cdata.key_dma = ctx->key_dma;
331 }
332
333 desc = ctx->sh_desc_enc;
334 cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
335 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
336 desc_bytes(desc), ctx->dir);
337
338 /*
339 * Job Descriptor and Shared Descriptors
340 * must all fit into the 64-word Descriptor h/w Buffer
341 */
342 if (rem_bytes >= DESC_GCM_DEC_LEN) {
343 ctx->cdata.key_inline = true;
344 ctx->cdata.key_virt = ctx->key;
345 } else {
346 ctx->cdata.key_inline = false;
347 ctx->cdata.key_dma = ctx->key_dma;
348 }
349
350 desc = ctx->sh_desc_dec;
351 cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
352 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
353 desc_bytes(desc), ctx->dir);
354
355 return 0;
356}
357
358static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
359{
360 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
361 int err;
362
363 err = crypto_gcm_check_authsize(authsize);
364 if (err)
365 return err;
366
367 ctx->authsize = authsize;
368 gcm_set_sh_desc(authenc);
369
370 return 0;
371}
372
373static int rfc4106_set_sh_desc(struct crypto_aead *aead)
374{
375 struct caam_ctx *ctx = crypto_aead_ctx(aead);
376 struct device *jrdev = ctx->jrdev;
377 unsigned int ivsize = crypto_aead_ivsize(aead);
378 u32 *desc;
379 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
380 ctx->cdata.keylen;
381
382 if (!ctx->cdata.keylen || !ctx->authsize)
383 return 0;
384
385 /*
386 * RFC4106 encrypt shared descriptor
387 * Job Descriptor and Shared Descriptor
388 * must fit into the 64-word Descriptor h/w Buffer
389 */
390 if (rem_bytes >= DESC_RFC4106_ENC_LEN) {
391 ctx->cdata.key_inline = true;
392 ctx->cdata.key_virt = ctx->key;
393 } else {
394 ctx->cdata.key_inline = false;
395 ctx->cdata.key_dma = ctx->key_dma;
396 }
397
398 desc = ctx->sh_desc_enc;
399 cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
400 false);
401 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
402 desc_bytes(desc), ctx->dir);
403
404 /*
405 * Job Descriptor and Shared Descriptors
406 * must all fit into the 64-word Descriptor h/w Buffer
407 */
408 if (rem_bytes >= DESC_RFC4106_DEC_LEN) {
409 ctx->cdata.key_inline = true;
410 ctx->cdata.key_virt = ctx->key;
411 } else {
412 ctx->cdata.key_inline = false;
413 ctx->cdata.key_dma = ctx->key_dma;
414 }
415
416 desc = ctx->sh_desc_dec;
417 cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
418 false);
419 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
420 desc_bytes(desc), ctx->dir);
421
422 return 0;
423}
424
425static int rfc4106_setauthsize(struct crypto_aead *authenc,
426 unsigned int authsize)
427{
428 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
429 int err;
430
431 err = crypto_rfc4106_check_authsize(authsize);
432 if (err)
433 return err;
434
435 ctx->authsize = authsize;
436 rfc4106_set_sh_desc(authenc);
437
438 return 0;
439}
440
441static int rfc4543_set_sh_desc(struct crypto_aead *aead)
442{
443 struct caam_ctx *ctx = crypto_aead_ctx(aead);
444 struct device *jrdev = ctx->jrdev;
445 unsigned int ivsize = crypto_aead_ivsize(aead);
446 u32 *desc;
447 int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
448 ctx->cdata.keylen;
449
450 if (!ctx->cdata.keylen || !ctx->authsize)
451 return 0;
452
453 /*
454 * RFC4543 encrypt shared descriptor
455 * Job Descriptor and Shared Descriptor
456 * must fit into the 64-word Descriptor h/w Buffer
457 */
458 if (rem_bytes >= DESC_RFC4543_ENC_LEN) {
459 ctx->cdata.key_inline = true;
460 ctx->cdata.key_virt = ctx->key;
461 } else {
462 ctx->cdata.key_inline = false;
463 ctx->cdata.key_dma = ctx->key_dma;
464 }
465
466 desc = ctx->sh_desc_enc;
467 cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
468 false);
469 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
470 desc_bytes(desc), ctx->dir);
471
472 /*
473 * Job Descriptor and Shared Descriptors
474 * must all fit into the 64-word Descriptor h/w Buffer
475 */
476 if (rem_bytes >= DESC_RFC4543_DEC_LEN) {
477 ctx->cdata.key_inline = true;
478 ctx->cdata.key_virt = ctx->key;
479 } else {
480 ctx->cdata.key_inline = false;
481 ctx->cdata.key_dma = ctx->key_dma;
482 }
483
484 desc = ctx->sh_desc_dec;
485 cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
486 false);
487 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
488 desc_bytes(desc), ctx->dir);
489
490 return 0;
491}
492
493static int rfc4543_setauthsize(struct crypto_aead *authenc,
494 unsigned int authsize)
495{
496 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
497
498 if (authsize != 16)
499 return -EINVAL;
500
501 ctx->authsize = authsize;
502 rfc4543_set_sh_desc(authenc);
503
504 return 0;
505}
506
507static int chachapoly_set_sh_desc(struct crypto_aead *aead)
508{
509 struct caam_ctx *ctx = crypto_aead_ctx(aead);
510 struct device *jrdev = ctx->jrdev;
511 unsigned int ivsize = crypto_aead_ivsize(aead);
512 u32 *desc;
513
514 if (!ctx->cdata.keylen || !ctx->authsize)
515 return 0;
516
517 desc = ctx->sh_desc_enc;
518 cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
519 ctx->authsize, true, false);
520 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
521 desc_bytes(desc), ctx->dir);
522
523 desc = ctx->sh_desc_dec;
524 cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
525 ctx->authsize, false, false);
526 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
527 desc_bytes(desc), ctx->dir);
528
529 return 0;
530}
531
532static int chachapoly_setauthsize(struct crypto_aead *aead,
533 unsigned int authsize)
534{
535 struct caam_ctx *ctx = crypto_aead_ctx(aead);
536
537 if (authsize != POLY1305_DIGEST_SIZE)
538 return -EINVAL;
539
540 ctx->authsize = authsize;
541 return chachapoly_set_sh_desc(aead);
542}
543
544static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key,
545 unsigned int keylen)
546{
547 struct caam_ctx *ctx = crypto_aead_ctx(aead);
548 unsigned int ivsize = crypto_aead_ivsize(aead);
549 unsigned int saltlen = CHACHAPOLY_IV_SIZE - ivsize;
550
551 if (keylen != CHACHA_KEY_SIZE + saltlen) {
552 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
553 return -EINVAL;
554 }
555
556 memcpy(ctx->key, key, keylen);
557 ctx->cdata.key_virt = ctx->key;
558 ctx->cdata.keylen = keylen - saltlen;
559
560 return chachapoly_set_sh_desc(aead);
561}
562
563static int aead_setkey(struct crypto_aead *aead,
564 const u8 *key, unsigned int keylen)
565{
566 struct caam_ctx *ctx = crypto_aead_ctx(aead);
567 struct device *jrdev = ctx->jrdev;
568 struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
569 struct crypto_authenc_keys keys;
570 int ret = 0;
571
572 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
573 goto badkey;
574
575 dev_dbg(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
576 keys.authkeylen + keys.enckeylen, keys.enckeylen,
577 keys.authkeylen);
578 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
579 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
580
581 /*
582 * If DKP is supported, use it in the shared descriptor to generate
583 * the split key.
584 */
585 if (ctrlpriv->era >= 6) {
586 ctx->adata.keylen = keys.authkeylen;
587 ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
588 OP_ALG_ALGSEL_MASK);
589
590 if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
591 goto badkey;
592
593 memcpy(ctx->key, keys.authkey, keys.authkeylen);
594 memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
595 keys.enckeylen);
596 dma_sync_single_for_device(jrdev, ctx->key_dma,
597 ctx->adata.keylen_pad +
598 keys.enckeylen, ctx->dir);
599 goto skip_split_key;
600 }
601
602 ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey,
603 keys.authkeylen, CAAM_MAX_KEY_SIZE -
604 keys.enckeylen);
605 if (ret) {
606 goto badkey;
607 }
608
609 /* postpend encryption key to auth split key */
610 memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
611 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
612 keys.enckeylen, ctx->dir);
613
614 print_hex_dump_debug("ctx.key@"__stringify(__LINE__)": ",
615 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
616 ctx->adata.keylen_pad + keys.enckeylen, 1);
617
618skip_split_key:
619 ctx->cdata.keylen = keys.enckeylen;
620 memzero_explicit(&keys, sizeof(keys));
621 return aead_set_sh_desc(aead);
622badkey:
623 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
624 memzero_explicit(&keys, sizeof(keys));
625 return -EINVAL;
626}
627
628static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key,
629 unsigned int keylen)
630{
631 struct crypto_authenc_keys keys;
632 int err;
633
634 err = crypto_authenc_extractkeys(&keys, key, keylen);
635 if (unlikely(err))
636 return err;
637
638 err = verify_aead_des3_key(aead, keys.enckey, keys.enckeylen) ?:
639 aead_setkey(aead, key, keylen);
640
641 memzero_explicit(&keys, sizeof(keys));
642 return err;
643}
644
645static int gcm_setkey(struct crypto_aead *aead,
646 const u8 *key, unsigned int keylen)
647{
648 struct caam_ctx *ctx = crypto_aead_ctx(aead);
649 struct device *jrdev = ctx->jrdev;
650 int err;
651
652 err = aes_check_keylen(keylen);
653 if (err) {
654 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
655 return err;
656 }
657
658 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
659 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
660
661 memcpy(ctx->key, key, keylen);
662 dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
663 ctx->cdata.keylen = keylen;
664
665 return gcm_set_sh_desc(aead);
666}
667
668static int rfc4106_setkey(struct crypto_aead *aead,
669 const u8 *key, unsigned int keylen)
670{
671 struct caam_ctx *ctx = crypto_aead_ctx(aead);
672 struct device *jrdev = ctx->jrdev;
673 int err;
674
675 err = aes_check_keylen(keylen - 4);
676 if (err) {
677 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
678 return err;
679 }
680
681 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
682 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
683
684 memcpy(ctx->key, key, keylen);
685
686 /*
687 * The last four bytes of the key material are used as the salt value
688 * in the nonce. Update the AES key length.
689 */
690 ctx->cdata.keylen = keylen - 4;
691 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
692 ctx->dir);
693 return rfc4106_set_sh_desc(aead);
694}
695
696static int rfc4543_setkey(struct crypto_aead *aead,
697 const u8 *key, unsigned int keylen)
698{
699 struct caam_ctx *ctx = crypto_aead_ctx(aead);
700 struct device *jrdev = ctx->jrdev;
701 int err;
702
703 err = aes_check_keylen(keylen - 4);
704 if (err) {
705 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
706 return err;
707 }
708
709 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
710 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
711
712 memcpy(ctx->key, key, keylen);
713
714 /*
715 * The last four bytes of the key material are used as the salt value
716 * in the nonce. Update the AES key length.
717 */
718 ctx->cdata.keylen = keylen - 4;
719 dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
720 ctx->dir);
721 return rfc4543_set_sh_desc(aead);
722}
723
724static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
725 unsigned int keylen, const u32 ctx1_iv_off)
726{
727 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
728 struct caam_skcipher_alg *alg =
729 container_of(crypto_skcipher_alg(skcipher), typeof(*alg),
730 skcipher);
731 struct device *jrdev = ctx->jrdev;
732 unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
733 u32 *desc;
734 const bool is_rfc3686 = alg->caam.rfc3686;
735
736 print_hex_dump_debug("key in @"__stringify(__LINE__)": ",
737 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
738
739 ctx->cdata.keylen = keylen;
740 ctx->cdata.key_virt = key;
741 ctx->cdata.key_inline = true;
742
743 /* skcipher_encrypt shared descriptor */
744 desc = ctx->sh_desc_enc;
745 cnstr_shdsc_skcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
746 ctx1_iv_off);
747 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
748 desc_bytes(desc), ctx->dir);
749
750 /* skcipher_decrypt shared descriptor */
751 desc = ctx->sh_desc_dec;
752 cnstr_shdsc_skcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
753 ctx1_iv_off);
754 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
755 desc_bytes(desc), ctx->dir);
756
757 return 0;
758}
759
760static int aes_skcipher_setkey(struct crypto_skcipher *skcipher,
761 const u8 *key, unsigned int keylen)
762{
763 int err;
764
765 err = aes_check_keylen(keylen);
766 if (err) {
767 crypto_skcipher_set_flags(skcipher,
768 CRYPTO_TFM_RES_BAD_KEY_LEN);
769 return err;
770 }
771
772 return skcipher_setkey(skcipher, key, keylen, 0);
773}
774
775static int rfc3686_skcipher_setkey(struct crypto_skcipher *skcipher,
776 const u8 *key, unsigned int keylen)
777{
778 u32 ctx1_iv_off;
779 int err;
780
781 /*
782 * RFC3686 specific:
783 * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
784 * | *key = {KEY, NONCE}
785 */
786 ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
787 keylen -= CTR_RFC3686_NONCE_SIZE;
788
789 err = aes_check_keylen(keylen);
790 if (err) {
791 crypto_skcipher_set_flags(skcipher,
792 CRYPTO_TFM_RES_BAD_KEY_LEN);
793 return err;
794 }
795
796 return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
797}
798
799static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher,
800 const u8 *key, unsigned int keylen)
801{
802 u32 ctx1_iv_off;
803 int err;
804
805 /*
806 * AES-CTR needs to load IV in CONTEXT1 reg
807 * at an offset of 128bits (16bytes)
808 * CONTEXT1[255:128] = IV
809 */
810 ctx1_iv_off = 16;
811
812 err = aes_check_keylen(keylen);
813 if (err) {
814 crypto_skcipher_set_flags(skcipher,
815 CRYPTO_TFM_RES_BAD_KEY_LEN);
816 return err;
817 }
818
819 return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
820}
821
822static int des_skcipher_setkey(struct crypto_skcipher *skcipher,
823 const u8 *key, unsigned int keylen)
824{
825 return verify_skcipher_des_key(skcipher, key) ?:
826 skcipher_setkey(skcipher, key, keylen, 0);
827}
828
829static int des3_skcipher_setkey(struct crypto_skcipher *skcipher,
830 const u8 *key, unsigned int keylen)
831{
832 return verify_skcipher_des3_key(skcipher, key) ?:
833 skcipher_setkey(skcipher, key, keylen, 0);
834}
835
836static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
837 unsigned int keylen)
838{
839 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
840 struct device *jrdev = ctx->jrdev;
841 u32 *desc;
842
843 if (keylen != 2 * AES_MIN_KEY_SIZE && keylen != 2 * AES_MAX_KEY_SIZE) {
844 crypto_skcipher_set_flags(skcipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
845 dev_err(jrdev, "key size mismatch\n");
846 return -EINVAL;
847 }
848
849 ctx->cdata.keylen = keylen;
850 ctx->cdata.key_virt = key;
851 ctx->cdata.key_inline = true;
852
853 /* xts_skcipher_encrypt shared descriptor */
854 desc = ctx->sh_desc_enc;
855 cnstr_shdsc_xts_skcipher_encap(desc, &ctx->cdata);
856 dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
857 desc_bytes(desc), ctx->dir);
858
859 /* xts_skcipher_decrypt shared descriptor */
860 desc = ctx->sh_desc_dec;
861 cnstr_shdsc_xts_skcipher_decap(desc, &ctx->cdata);
862 dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
863 desc_bytes(desc), ctx->dir);
864
865 return 0;
866}
867
868/*
869 * aead_edesc - s/w-extended aead descriptor
870 * @src_nents: number of segments in input s/w scatterlist
871 * @dst_nents: number of segments in output s/w scatterlist
872 * @mapped_src_nents: number of segments in input h/w link table
873 * @mapped_dst_nents: number of segments in output h/w link table
874 * @sec4_sg_bytes: length of dma mapped sec4_sg space
875 * @sec4_sg_dma: bus physical mapped address of h/w link table
876 * @sec4_sg: pointer to h/w link table
877 * @hw_desc: the h/w job descriptor followed by any referenced link tables
878 */
879struct aead_edesc {
880 int src_nents;
881 int dst_nents;
882 int mapped_src_nents;
883 int mapped_dst_nents;
884 int sec4_sg_bytes;
885 dma_addr_t sec4_sg_dma;
886 struct sec4_sg_entry *sec4_sg;
887 u32 hw_desc[];
888};
889
890/*
891 * skcipher_edesc - s/w-extended skcipher descriptor
892 * @src_nents: number of segments in input s/w scatterlist
893 * @dst_nents: number of segments in output s/w scatterlist
894 * @mapped_src_nents: number of segments in input h/w link table
895 * @mapped_dst_nents: number of segments in output h/w link table
896 * @iv_dma: dma address of iv for checking continuity and link table
897 * @sec4_sg_bytes: length of dma mapped sec4_sg space
898 * @sec4_sg_dma: bus physical mapped address of h/w link table
899 * @sec4_sg: pointer to h/w link table
900 * @hw_desc: the h/w job descriptor followed by any referenced link tables
901 * and IV
902 */
903struct skcipher_edesc {
904 int src_nents;
905 int dst_nents;
906 int mapped_src_nents;
907 int mapped_dst_nents;
908 dma_addr_t iv_dma;
909 int sec4_sg_bytes;
910 dma_addr_t sec4_sg_dma;
911 struct sec4_sg_entry *sec4_sg;
912 u32 hw_desc[0];
913};
914
915static void caam_unmap(struct device *dev, struct scatterlist *src,
916 struct scatterlist *dst, int src_nents,
917 int dst_nents,
918 dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
919 int sec4_sg_bytes)
920{
921 if (dst != src) {
922 if (src_nents)
923 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
924 if (dst_nents)
925 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
926 } else {
927 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
928 }
929
930 if (iv_dma)
931 dma_unmap_single(dev, iv_dma, ivsize, DMA_BIDIRECTIONAL);
932 if (sec4_sg_bytes)
933 dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
934 DMA_TO_DEVICE);
935}
936
937static void aead_unmap(struct device *dev,
938 struct aead_edesc *edesc,
939 struct aead_request *req)
940{
941 caam_unmap(dev, req->src, req->dst,
942 edesc->src_nents, edesc->dst_nents, 0, 0,
943 edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
944}
945
946static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc,
947 struct skcipher_request *req)
948{
949 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
950 int ivsize = crypto_skcipher_ivsize(skcipher);
951
952 caam_unmap(dev, req->src, req->dst,
953 edesc->src_nents, edesc->dst_nents,
954 edesc->iv_dma, ivsize,
955 edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
956}
957
958static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
959 void *context)
960{
961 struct aead_request *req = context;
962 struct aead_edesc *edesc;
963 int ecode = 0;
964
965 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
966
967 edesc = container_of(desc, struct aead_edesc, hw_desc[0]);
968
969 if (err)
970 ecode = caam_jr_strstatus(jrdev, err);
971
972 aead_unmap(jrdev, edesc, req);
973
974 kfree(edesc);
975
976 aead_request_complete(req, ecode);
977}
978
979static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
980 void *context)
981{
982 struct aead_request *req = context;
983 struct aead_edesc *edesc;
984 int ecode = 0;
985
986 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
987
988 edesc = container_of(desc, struct aead_edesc, hw_desc[0]);
989
990 if (err)
991 ecode = caam_jr_strstatus(jrdev, err);
992
993 aead_unmap(jrdev, edesc, req);
994
995 kfree(edesc);
996
997 aead_request_complete(req, ecode);
998}
999
1000static void skcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
1001 void *context)
1002{
1003 struct skcipher_request *req = context;
1004 struct skcipher_edesc *edesc;
1005 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1006 int ivsize = crypto_skcipher_ivsize(skcipher);
1007 int ecode = 0;
1008
1009 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
1010
1011 edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]);
1012
1013 if (err)
1014 ecode = caam_jr_strstatus(jrdev, err);
1015
1016 skcipher_unmap(jrdev, edesc, req);
1017
1018 /*
1019 * The crypto API expects us to set the IV (req->iv) to the last
1020 * ciphertext block (CBC mode) or last counter (CTR mode).
1021 * This is used e.g. by the CTS mode.
1022 */
1023 if (ivsize && !ecode) {
1024 memcpy(req->iv, (u8 *)edesc->sec4_sg + edesc->sec4_sg_bytes,
1025 ivsize);
1026 print_hex_dump_debug("dstiv @"__stringify(__LINE__)": ",
1027 DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
1028 edesc->src_nents > 1 ? 100 : ivsize, 1);
1029 }
1030
1031 caam_dump_sg("dst @" __stringify(__LINE__)": ",
1032 DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
1033 edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
1034
1035 kfree(edesc);
1036
1037 skcipher_request_complete(req, ecode);
1038}
1039
1040static void skcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
1041 void *context)
1042{
1043 struct skcipher_request *req = context;
1044 struct skcipher_edesc *edesc;
1045 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1046 int ivsize = crypto_skcipher_ivsize(skcipher);
1047 int ecode = 0;
1048
1049 dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
1050
1051 edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]);
1052 if (err)
1053 ecode = caam_jr_strstatus(jrdev, err);
1054
1055 skcipher_unmap(jrdev, edesc, req);
1056
1057 /*
1058 * The crypto API expects us to set the IV (req->iv) to the last
1059 * ciphertext block (CBC mode) or last counter (CTR mode).
1060 * This is used e.g. by the CTS mode.
1061 */
1062 if (ivsize && !ecode) {
1063 memcpy(req->iv, (u8 *)edesc->sec4_sg + edesc->sec4_sg_bytes,
1064 ivsize);
1065
1066 print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ",
1067 DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
1068 ivsize, 1);
1069 }
1070
1071 caam_dump_sg("dst @" __stringify(__LINE__)": ",
1072 DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
1073 edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
1074
1075 kfree(edesc);
1076
1077 skcipher_request_complete(req, ecode);
1078}
1079
1080/*
1081 * Fill in aead job descriptor
1082 */
1083static void init_aead_job(struct aead_request *req,
1084 struct aead_edesc *edesc,
1085 bool all_contig, bool encrypt)
1086{
1087 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1088 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1089 int authsize = ctx->authsize;
1090 u32 *desc = edesc->hw_desc;
1091 u32 out_options, in_options;
1092 dma_addr_t dst_dma, src_dma;
1093 int len, sec4_sg_index = 0;
1094 dma_addr_t ptr;
1095 u32 *sh_desc;
1096
1097 sh_desc = encrypt ? ctx->sh_desc_enc : ctx->sh_desc_dec;
1098 ptr = encrypt ? ctx->sh_desc_enc_dma : ctx->sh_desc_dec_dma;
1099
1100 len = desc_len(sh_desc);
1101 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1102
1103 if (all_contig) {
1104 src_dma = edesc->mapped_src_nents ? sg_dma_address(req->src) :
1105 0;
1106 in_options = 0;
1107 } else {
1108 src_dma = edesc->sec4_sg_dma;
1109 sec4_sg_index += edesc->mapped_src_nents;
1110 in_options = LDST_SGF;
1111 }
1112
1113 append_seq_in_ptr(desc, src_dma, req->assoclen + req->cryptlen,
1114 in_options);
1115
1116 dst_dma = src_dma;
1117 out_options = in_options;
1118
1119 if (unlikely(req->src != req->dst)) {
1120 if (!edesc->mapped_dst_nents) {
1121 dst_dma = 0;
1122 out_options = 0;
1123 } else if (edesc->mapped_dst_nents == 1) {
1124 dst_dma = sg_dma_address(req->dst);
1125 out_options = 0;
1126 } else {
1127 dst_dma = edesc->sec4_sg_dma +
1128 sec4_sg_index *
1129 sizeof(struct sec4_sg_entry);
1130 out_options = LDST_SGF;
1131 }
1132 }
1133
1134 if (encrypt)
1135 append_seq_out_ptr(desc, dst_dma,
1136 req->assoclen + req->cryptlen + authsize,
1137 out_options);
1138 else
1139 append_seq_out_ptr(desc, dst_dma,
1140 req->assoclen + req->cryptlen - authsize,
1141 out_options);
1142}
1143
1144static void init_gcm_job(struct aead_request *req,
1145 struct aead_edesc *edesc,
1146 bool all_contig, bool encrypt)
1147{
1148 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1149 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1150 unsigned int ivsize = crypto_aead_ivsize(aead);
1151 u32 *desc = edesc->hw_desc;
1152 bool generic_gcm = (ivsize == GCM_AES_IV_SIZE);
1153 unsigned int last;
1154
1155 init_aead_job(req, edesc, all_contig, encrypt);
1156 append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
1157
1158 /* BUG This should not be specific to generic GCM. */
1159 last = 0;
1160 if (encrypt && generic_gcm && !(req->assoclen + req->cryptlen))
1161 last = FIFOLD_TYPE_LAST1;
1162
1163 /* Read GCM IV */
1164 append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
1165 FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | GCM_AES_IV_SIZE | last);
1166 /* Append Salt */
1167 if (!generic_gcm)
1168 append_data(desc, ctx->key + ctx->cdata.keylen, 4);
1169 /* Append IV */
1170 append_data(desc, req->iv, ivsize);
1171 /* End of blank commands */
1172}
1173
1174static void init_chachapoly_job(struct aead_request *req,
1175 struct aead_edesc *edesc, bool all_contig,
1176 bool encrypt)
1177{
1178 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1179 unsigned int ivsize = crypto_aead_ivsize(aead);
1180 unsigned int assoclen = req->assoclen;
1181 u32 *desc = edesc->hw_desc;
1182 u32 ctx_iv_off = 4;
1183
1184 init_aead_job(req, edesc, all_contig, encrypt);
1185
1186 if (ivsize != CHACHAPOLY_IV_SIZE) {
1187 /* IPsec specific: CONTEXT1[223:128] = {NONCE, IV} */
1188 ctx_iv_off += 4;
1189
1190 /*
1191 * The associated data comes already with the IV but we need
1192 * to skip it when we authenticate or encrypt...
1193 */
1194 assoclen -= ivsize;
1195 }
1196
1197 append_math_add_imm_u32(desc, REG3, ZERO, IMM, assoclen);
1198
1199 /*
1200 * For IPsec load the IV further in the same register.
1201 * For RFC7539 simply load the 12 bytes nonce in a single operation
1202 */
1203 append_load_as_imm(desc, req->iv, ivsize, LDST_CLASS_1_CCB |
1204 LDST_SRCDST_BYTE_CONTEXT |
1205 ctx_iv_off << LDST_OFFSET_SHIFT);
1206}
1207
1208static void init_authenc_job(struct aead_request *req,
1209 struct aead_edesc *edesc,
1210 bool all_contig, bool encrypt)
1211{
1212 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1213 struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
1214 struct caam_aead_alg, aead);
1215 unsigned int ivsize = crypto_aead_ivsize(aead);
1216 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1217 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
1218 const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
1219 OP_ALG_AAI_CTR_MOD128);
1220 const bool is_rfc3686 = alg->caam.rfc3686;
1221 u32 *desc = edesc->hw_desc;
1222 u32 ivoffset = 0;
1223
1224 /*
1225 * AES-CTR needs to load IV in CONTEXT1 reg
1226 * at an offset of 128bits (16bytes)
1227 * CONTEXT1[255:128] = IV
1228 */
1229 if (ctr_mode)
1230 ivoffset = 16;
1231
1232 /*
1233 * RFC3686 specific:
1234 * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
1235 */
1236 if (is_rfc3686)
1237 ivoffset = 16 + CTR_RFC3686_NONCE_SIZE;
1238
1239 init_aead_job(req, edesc, all_contig, encrypt);
1240
1241 /*
1242 * {REG3, DPOVRD} = assoclen, depending on whether MATH command supports
1243 * having DPOVRD as destination.
1244 */
1245 if (ctrlpriv->era < 3)
1246 append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
1247 else
1248 append_math_add_imm_u32(desc, DPOVRD, ZERO, IMM, req->assoclen);
1249
1250 if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv))
1251 append_load_as_imm(desc, req->iv, ivsize,
1252 LDST_CLASS_1_CCB |
1253 LDST_SRCDST_BYTE_CONTEXT |
1254 (ivoffset << LDST_OFFSET_SHIFT));
1255}
1256
1257/*
1258 * Fill in skcipher job descriptor
1259 */
1260static void init_skcipher_job(struct skcipher_request *req,
1261 struct skcipher_edesc *edesc,
1262 const bool encrypt)
1263{
1264 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1265 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1266 struct device *jrdev = ctx->jrdev;
1267 int ivsize = crypto_skcipher_ivsize(skcipher);
1268 u32 *desc = edesc->hw_desc;
1269 u32 *sh_desc;
1270 u32 in_options = 0, out_options = 0;
1271 dma_addr_t src_dma, dst_dma, ptr;
1272 int len, sec4_sg_index = 0;
1273
1274 print_hex_dump_debug("presciv@"__stringify(__LINE__)": ",
1275 DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
1276 dev_dbg(jrdev, "asked=%d, cryptlen%d\n",
1277 (int)edesc->src_nents > 1 ? 100 : req->cryptlen, req->cryptlen);
1278
1279 caam_dump_sg("src @" __stringify(__LINE__)": ",
1280 DUMP_PREFIX_ADDRESS, 16, 4, req->src,
1281 edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
1282
1283 sh_desc = encrypt ? ctx->sh_desc_enc : ctx->sh_desc_dec;
1284 ptr = encrypt ? ctx->sh_desc_enc_dma : ctx->sh_desc_dec_dma;
1285
1286 len = desc_len(sh_desc);
1287 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1288
1289 if (ivsize || edesc->mapped_src_nents > 1) {
1290 src_dma = edesc->sec4_sg_dma;
1291 sec4_sg_index = edesc->mapped_src_nents + !!ivsize;
1292 in_options = LDST_SGF;
1293 } else {
1294 src_dma = sg_dma_address(req->src);
1295 }
1296
1297 append_seq_in_ptr(desc, src_dma, req->cryptlen + ivsize, in_options);
1298
1299 if (likely(req->src == req->dst)) {
1300 dst_dma = src_dma + !!ivsize * sizeof(struct sec4_sg_entry);
1301 out_options = in_options;
1302 } else if (!ivsize && edesc->mapped_dst_nents == 1) {
1303 dst_dma = sg_dma_address(req->dst);
1304 } else {
1305 dst_dma = edesc->sec4_sg_dma + sec4_sg_index *
1306 sizeof(struct sec4_sg_entry);
1307 out_options = LDST_SGF;
1308 }
1309
1310 append_seq_out_ptr(desc, dst_dma, req->cryptlen + ivsize, out_options);
1311}
1312
1313/*
1314 * allocate and map the aead extended descriptor
1315 */
1316static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
1317 int desc_bytes, bool *all_contig_ptr,
1318 bool encrypt)
1319{
1320 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1321 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1322 struct device *jrdev = ctx->jrdev;
1323 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
1324 GFP_KERNEL : GFP_ATOMIC;
1325 int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
1326 int src_len, dst_len = 0;
1327 struct aead_edesc *edesc;
1328 int sec4_sg_index, sec4_sg_len, sec4_sg_bytes;
1329 unsigned int authsize = ctx->authsize;
1330
1331 if (unlikely(req->dst != req->src)) {
1332 src_len = req->assoclen + req->cryptlen;
1333 dst_len = src_len + (encrypt ? authsize : (-authsize));
1334
1335 src_nents = sg_nents_for_len(req->src, src_len);
1336 if (unlikely(src_nents < 0)) {
1337 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1338 src_len);
1339 return ERR_PTR(src_nents);
1340 }
1341
1342 dst_nents = sg_nents_for_len(req->dst, dst_len);
1343 if (unlikely(dst_nents < 0)) {
1344 dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
1345 dst_len);
1346 return ERR_PTR(dst_nents);
1347 }
1348 } else {
1349 src_len = req->assoclen + req->cryptlen +
1350 (encrypt ? authsize : 0);
1351
1352 src_nents = sg_nents_for_len(req->src, src_len);
1353 if (unlikely(src_nents < 0)) {
1354 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1355 src_len);
1356 return ERR_PTR(src_nents);
1357 }
1358 }
1359
1360 if (likely(req->src == req->dst)) {
1361 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1362 DMA_BIDIRECTIONAL);
1363 if (unlikely(!mapped_src_nents)) {
1364 dev_err(jrdev, "unable to map source\n");
1365 return ERR_PTR(-ENOMEM);
1366 }
1367 } else {
1368 /* Cover also the case of null (zero length) input data */
1369 if (src_nents) {
1370 mapped_src_nents = dma_map_sg(jrdev, req->src,
1371 src_nents, DMA_TO_DEVICE);
1372 if (unlikely(!mapped_src_nents)) {
1373 dev_err(jrdev, "unable to map source\n");
1374 return ERR_PTR(-ENOMEM);
1375 }
1376 } else {
1377 mapped_src_nents = 0;
1378 }
1379
1380 /* Cover also the case of null (zero length) output data */
1381 if (dst_nents) {
1382 mapped_dst_nents = dma_map_sg(jrdev, req->dst,
1383 dst_nents,
1384 DMA_FROM_DEVICE);
1385 if (unlikely(!mapped_dst_nents)) {
1386 dev_err(jrdev, "unable to map destination\n");
1387 dma_unmap_sg(jrdev, req->src, src_nents,
1388 DMA_TO_DEVICE);
1389 return ERR_PTR(-ENOMEM);
1390 }
1391 } else {
1392 mapped_dst_nents = 0;
1393 }
1394 }
1395
1396 /*
1397 * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
1398 * the end of the table by allocating more S/G entries.
1399 */
1400 sec4_sg_len = mapped_src_nents > 1 ? mapped_src_nents : 0;
1401 if (mapped_dst_nents > 1)
1402 sec4_sg_len += pad_sg_nents(mapped_dst_nents);
1403 else
1404 sec4_sg_len = pad_sg_nents(sec4_sg_len);
1405
1406 sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
1407
1408 /* allocate space for base edesc and hw desc commands, link tables */
1409 edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
1410 GFP_DMA | flags);
1411 if (!edesc) {
1412 caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
1413 0, 0, 0);
1414 return ERR_PTR(-ENOMEM);
1415 }
1416
1417 edesc->src_nents = src_nents;
1418 edesc->dst_nents = dst_nents;
1419 edesc->mapped_src_nents = mapped_src_nents;
1420 edesc->mapped_dst_nents = mapped_dst_nents;
1421 edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
1422 desc_bytes;
1423 *all_contig_ptr = !(mapped_src_nents > 1);
1424
1425 sec4_sg_index = 0;
1426 if (mapped_src_nents > 1) {
1427 sg_to_sec4_sg_last(req->src, src_len,
1428 edesc->sec4_sg + sec4_sg_index, 0);
1429 sec4_sg_index += mapped_src_nents;
1430 }
1431 if (mapped_dst_nents > 1) {
1432 sg_to_sec4_sg_last(req->dst, dst_len,
1433 edesc->sec4_sg + sec4_sg_index, 0);
1434 }
1435
1436 if (!sec4_sg_bytes)
1437 return edesc;
1438
1439 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1440 sec4_sg_bytes, DMA_TO_DEVICE);
1441 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1442 dev_err(jrdev, "unable to map S/G table\n");
1443 aead_unmap(jrdev, edesc, req);
1444 kfree(edesc);
1445 return ERR_PTR(-ENOMEM);
1446 }
1447
1448 edesc->sec4_sg_bytes = sec4_sg_bytes;
1449
1450 return edesc;
1451}
1452
1453static int gcm_encrypt(struct aead_request *req)
1454{
1455 struct aead_edesc *edesc;
1456 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1457 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1458 struct device *jrdev = ctx->jrdev;
1459 bool all_contig;
1460 u32 *desc;
1461 int ret = 0;
1462
1463 /* allocate extended descriptor */
1464 edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, true);
1465 if (IS_ERR(edesc))
1466 return PTR_ERR(edesc);
1467
1468 /* Create and submit job descriptor */
1469 init_gcm_job(req, edesc, all_contig, true);
1470
1471 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1472 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1473 desc_bytes(edesc->hw_desc), 1);
1474
1475 desc = edesc->hw_desc;
1476 ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
1477 if (!ret) {
1478 ret = -EINPROGRESS;
1479 } else {
1480 aead_unmap(jrdev, edesc, req);
1481 kfree(edesc);
1482 }
1483
1484 return ret;
1485}
1486
1487static int chachapoly_encrypt(struct aead_request *req)
1488{
1489 struct aead_edesc *edesc;
1490 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1491 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1492 struct device *jrdev = ctx->jrdev;
1493 bool all_contig;
1494 u32 *desc;
1495 int ret;
1496
1497 edesc = aead_edesc_alloc(req, CHACHAPOLY_DESC_JOB_IO_LEN, &all_contig,
1498 true);
1499 if (IS_ERR(edesc))
1500 return PTR_ERR(edesc);
1501
1502 desc = edesc->hw_desc;
1503
1504 init_chachapoly_job(req, edesc, all_contig, true);
1505 print_hex_dump_debug("chachapoly jobdesc@" __stringify(__LINE__)": ",
1506 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
1507 1);
1508
1509 ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
1510 if (!ret) {
1511 ret = -EINPROGRESS;
1512 } else {
1513 aead_unmap(jrdev, edesc, req);
1514 kfree(edesc);
1515 }
1516
1517 return ret;
1518}
1519
1520static int chachapoly_decrypt(struct aead_request *req)
1521{
1522 struct aead_edesc *edesc;
1523 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1524 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1525 struct device *jrdev = ctx->jrdev;
1526 bool all_contig;
1527 u32 *desc;
1528 int ret;
1529
1530 edesc = aead_edesc_alloc(req, CHACHAPOLY_DESC_JOB_IO_LEN, &all_contig,
1531 false);
1532 if (IS_ERR(edesc))
1533 return PTR_ERR(edesc);
1534
1535 desc = edesc->hw_desc;
1536
1537 init_chachapoly_job(req, edesc, all_contig, false);
1538 print_hex_dump_debug("chachapoly jobdesc@" __stringify(__LINE__)": ",
1539 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
1540 1);
1541
1542 ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
1543 if (!ret) {
1544 ret = -EINPROGRESS;
1545 } else {
1546 aead_unmap(jrdev, edesc, req);
1547 kfree(edesc);
1548 }
1549
1550 return ret;
1551}
1552
1553static int ipsec_gcm_encrypt(struct aead_request *req)
1554{
1555 return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req);
1556}
1557
1558static int aead_encrypt(struct aead_request *req)
1559{
1560 struct aead_edesc *edesc;
1561 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1562 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1563 struct device *jrdev = ctx->jrdev;
1564 bool all_contig;
1565 u32 *desc;
1566 int ret = 0;
1567
1568 /* allocate extended descriptor */
1569 edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
1570 &all_contig, true);
1571 if (IS_ERR(edesc))
1572 return PTR_ERR(edesc);
1573
1574 /* Create and submit job descriptor */
1575 init_authenc_job(req, edesc, all_contig, true);
1576
1577 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1578 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1579 desc_bytes(edesc->hw_desc), 1);
1580
1581 desc = edesc->hw_desc;
1582 ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
1583 if (!ret) {
1584 ret = -EINPROGRESS;
1585 } else {
1586 aead_unmap(jrdev, edesc, req);
1587 kfree(edesc);
1588 }
1589
1590 return ret;
1591}
1592
1593static int gcm_decrypt(struct aead_request *req)
1594{
1595 struct aead_edesc *edesc;
1596 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1597 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1598 struct device *jrdev = ctx->jrdev;
1599 bool all_contig;
1600 u32 *desc;
1601 int ret = 0;
1602
1603 /* allocate extended descriptor */
1604 edesc = aead_edesc_alloc(req, GCM_DESC_JOB_IO_LEN, &all_contig, false);
1605 if (IS_ERR(edesc))
1606 return PTR_ERR(edesc);
1607
1608 /* Create and submit job descriptor*/
1609 init_gcm_job(req, edesc, all_contig, false);
1610
1611 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1612 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1613 desc_bytes(edesc->hw_desc), 1);
1614
1615 desc = edesc->hw_desc;
1616 ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
1617 if (!ret) {
1618 ret = -EINPROGRESS;
1619 } else {
1620 aead_unmap(jrdev, edesc, req);
1621 kfree(edesc);
1622 }
1623
1624 return ret;
1625}
1626
1627static int ipsec_gcm_decrypt(struct aead_request *req)
1628{
1629 return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req);
1630}
1631
1632static int aead_decrypt(struct aead_request *req)
1633{
1634 struct aead_edesc *edesc;
1635 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1636 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1637 struct device *jrdev = ctx->jrdev;
1638 bool all_contig;
1639 u32 *desc;
1640 int ret = 0;
1641
1642 caam_dump_sg("dec src@" __stringify(__LINE__)": ",
1643 DUMP_PREFIX_ADDRESS, 16, 4, req->src,
1644 req->assoclen + req->cryptlen, 1);
1645
1646 /* allocate extended descriptor */
1647 edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
1648 &all_contig, false);
1649 if (IS_ERR(edesc))
1650 return PTR_ERR(edesc);
1651
1652 /* Create and submit job descriptor*/
1653 init_authenc_job(req, edesc, all_contig, false);
1654
1655 print_hex_dump_debug("aead jobdesc@"__stringify(__LINE__)": ",
1656 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1657 desc_bytes(edesc->hw_desc), 1);
1658
1659 desc = edesc->hw_desc;
1660 ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
1661 if (!ret) {
1662 ret = -EINPROGRESS;
1663 } else {
1664 aead_unmap(jrdev, edesc, req);
1665 kfree(edesc);
1666 }
1667
1668 return ret;
1669}
1670
1671/*
1672 * allocate and map the skcipher extended descriptor for skcipher
1673 */
1674static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req,
1675 int desc_bytes)
1676{
1677 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1678 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1679 struct device *jrdev = ctx->jrdev;
1680 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
1681 GFP_KERNEL : GFP_ATOMIC;
1682 int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
1683 struct skcipher_edesc *edesc;
1684 dma_addr_t iv_dma = 0;
1685 u8 *iv;
1686 int ivsize = crypto_skcipher_ivsize(skcipher);
1687 int dst_sg_idx, sec4_sg_ents, sec4_sg_bytes;
1688
1689 src_nents = sg_nents_for_len(req->src, req->cryptlen);
1690 if (unlikely(src_nents < 0)) {
1691 dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
1692 req->cryptlen);
1693 return ERR_PTR(src_nents);
1694 }
1695
1696 if (req->dst != req->src) {
1697 dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
1698 if (unlikely(dst_nents < 0)) {
1699 dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
1700 req->cryptlen);
1701 return ERR_PTR(dst_nents);
1702 }
1703 }
1704
1705 if (likely(req->src == req->dst)) {
1706 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1707 DMA_BIDIRECTIONAL);
1708 if (unlikely(!mapped_src_nents)) {
1709 dev_err(jrdev, "unable to map source\n");
1710 return ERR_PTR(-ENOMEM);
1711 }
1712 } else {
1713 mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
1714 DMA_TO_DEVICE);
1715 if (unlikely(!mapped_src_nents)) {
1716 dev_err(jrdev, "unable to map source\n");
1717 return ERR_PTR(-ENOMEM);
1718 }
1719 mapped_dst_nents = dma_map_sg(jrdev, req->dst, dst_nents,
1720 DMA_FROM_DEVICE);
1721 if (unlikely(!mapped_dst_nents)) {
1722 dev_err(jrdev, "unable to map destination\n");
1723 dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
1724 return ERR_PTR(-ENOMEM);
1725 }
1726 }
1727
1728 if (!ivsize && mapped_src_nents == 1)
1729 sec4_sg_ents = 0; // no need for an input hw s/g table
1730 else
1731 sec4_sg_ents = mapped_src_nents + !!ivsize;
1732 dst_sg_idx = sec4_sg_ents;
1733
1734 /*
1735 * Input, output HW S/G tables: [IV, src][dst, IV]
1736 * IV entries point to the same buffer
1737 * If src == dst, S/G entries are reused (S/G tables overlap)
1738 *
1739 * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
1740 * the end of the table by allocating more S/G entries. Logic:
1741 * if (output S/G)
1742 * pad output S/G, if needed
1743 * else if (input S/G) ...
1744 * pad input S/G, if needed
1745 */
1746 if (ivsize || mapped_dst_nents > 1) {
1747 if (req->src == req->dst)
1748 sec4_sg_ents = !!ivsize + pad_sg_nents(sec4_sg_ents);
1749 else
1750 sec4_sg_ents += pad_sg_nents(mapped_dst_nents +
1751 !!ivsize);
1752 } else {
1753 sec4_sg_ents = pad_sg_nents(sec4_sg_ents);
1754 }
1755
1756 sec4_sg_bytes = sec4_sg_ents * sizeof(struct sec4_sg_entry);
1757
1758 /*
1759 * allocate space for base edesc and hw desc commands, link tables, IV
1760 */
1761 edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes + ivsize,
1762 GFP_DMA | flags);
1763 if (!edesc) {
1764 dev_err(jrdev, "could not allocate extended descriptor\n");
1765 caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
1766 0, 0, 0);
1767 return ERR_PTR(-ENOMEM);
1768 }
1769
1770 edesc->src_nents = src_nents;
1771 edesc->dst_nents = dst_nents;
1772 edesc->mapped_src_nents = mapped_src_nents;
1773 edesc->mapped_dst_nents = mapped_dst_nents;
1774 edesc->sec4_sg_bytes = sec4_sg_bytes;
1775 edesc->sec4_sg = (struct sec4_sg_entry *)((u8 *)edesc->hw_desc +
1776 desc_bytes);
1777
1778 /* Make sure IV is located in a DMAable area */
1779 if (ivsize) {
1780 iv = (u8 *)edesc->sec4_sg + sec4_sg_bytes;
1781 memcpy(iv, req->iv, ivsize);
1782
1783 iv_dma = dma_map_single(jrdev, iv, ivsize, DMA_BIDIRECTIONAL);
1784 if (dma_mapping_error(jrdev, iv_dma)) {
1785 dev_err(jrdev, "unable to map IV\n");
1786 caam_unmap(jrdev, req->src, req->dst, src_nents,
1787 dst_nents, 0, 0, 0, 0);
1788 kfree(edesc);
1789 return ERR_PTR(-ENOMEM);
1790 }
1791
1792 dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
1793 }
1794 if (dst_sg_idx)
1795 sg_to_sec4_sg(req->src, req->cryptlen, edesc->sec4_sg +
1796 !!ivsize, 0);
1797
1798 if (req->src != req->dst && (ivsize || mapped_dst_nents > 1))
1799 sg_to_sec4_sg(req->dst, req->cryptlen, edesc->sec4_sg +
1800 dst_sg_idx, 0);
1801
1802 if (ivsize)
1803 dma_to_sec4_sg_one(edesc->sec4_sg + dst_sg_idx +
1804 mapped_dst_nents, iv_dma, ivsize, 0);
1805
1806 if (ivsize || mapped_dst_nents > 1)
1807 sg_to_sec4_set_last(edesc->sec4_sg + dst_sg_idx +
1808 mapped_dst_nents - 1 + !!ivsize);
1809
1810 if (sec4_sg_bytes) {
1811 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1812 sec4_sg_bytes,
1813 DMA_TO_DEVICE);
1814 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1815 dev_err(jrdev, "unable to map S/G table\n");
1816 caam_unmap(jrdev, req->src, req->dst, src_nents,
1817 dst_nents, iv_dma, ivsize, 0, 0);
1818 kfree(edesc);
1819 return ERR_PTR(-ENOMEM);
1820 }
1821 }
1822
1823 edesc->iv_dma = iv_dma;
1824
1825 print_hex_dump_debug("skcipher sec4_sg@" __stringify(__LINE__)": ",
1826 DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
1827 sec4_sg_bytes, 1);
1828
1829 return edesc;
1830}
1831
1832static int skcipher_encrypt(struct skcipher_request *req)
1833{
1834 struct skcipher_edesc *edesc;
1835 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1836 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1837 struct device *jrdev = ctx->jrdev;
1838 u32 *desc;
1839 int ret = 0;
1840
1841 if (!req->cryptlen)
1842 return 0;
1843
1844 /* allocate extended descriptor */
1845 edesc = skcipher_edesc_alloc(req, DESC_JOB_IO_LEN * CAAM_CMD_SZ);
1846 if (IS_ERR(edesc))
1847 return PTR_ERR(edesc);
1848
1849 /* Create and submit job descriptor*/
1850 init_skcipher_job(req, edesc, true);
1851
1852 print_hex_dump_debug("skcipher jobdesc@" __stringify(__LINE__)": ",
1853 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1854 desc_bytes(edesc->hw_desc), 1);
1855
1856 desc = edesc->hw_desc;
1857 ret = caam_jr_enqueue(jrdev, desc, skcipher_encrypt_done, req);
1858
1859 if (!ret) {
1860 ret = -EINPROGRESS;
1861 } else {
1862 skcipher_unmap(jrdev, edesc, req);
1863 kfree(edesc);
1864 }
1865
1866 return ret;
1867}
1868
1869static int skcipher_decrypt(struct skcipher_request *req)
1870{
1871 struct skcipher_edesc *edesc;
1872 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
1873 struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
1874 struct device *jrdev = ctx->jrdev;
1875 u32 *desc;
1876 int ret = 0;
1877
1878 if (!req->cryptlen)
1879 return 0;
1880
1881 /* allocate extended descriptor */
1882 edesc = skcipher_edesc_alloc(req, DESC_JOB_IO_LEN * CAAM_CMD_SZ);
1883 if (IS_ERR(edesc))
1884 return PTR_ERR(edesc);
1885
1886 /* Create and submit job descriptor*/
1887 init_skcipher_job(req, edesc, false);
1888 desc = edesc->hw_desc;
1889
1890 print_hex_dump_debug("skcipher jobdesc@" __stringify(__LINE__)": ",
1891 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1892 desc_bytes(edesc->hw_desc), 1);
1893
1894 ret = caam_jr_enqueue(jrdev, desc, skcipher_decrypt_done, req);
1895 if (!ret) {
1896 ret = -EINPROGRESS;
1897 } else {
1898 skcipher_unmap(jrdev, edesc, req);
1899 kfree(edesc);
1900 }
1901
1902 return ret;
1903}
1904
1905static struct caam_skcipher_alg driver_algs[] = {
1906 {
1907 .skcipher = {
1908 .base = {
1909 .cra_name = "cbc(aes)",
1910 .cra_driver_name = "cbc-aes-caam",
1911 .cra_blocksize = AES_BLOCK_SIZE,
1912 },
1913 .setkey = aes_skcipher_setkey,
1914 .encrypt = skcipher_encrypt,
1915 .decrypt = skcipher_decrypt,
1916 .min_keysize = AES_MIN_KEY_SIZE,
1917 .max_keysize = AES_MAX_KEY_SIZE,
1918 .ivsize = AES_BLOCK_SIZE,
1919 },
1920 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1921 },
1922 {
1923 .skcipher = {
1924 .base = {
1925 .cra_name = "cbc(des3_ede)",
1926 .cra_driver_name = "cbc-3des-caam",
1927 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1928 },
1929 .setkey = des3_skcipher_setkey,
1930 .encrypt = skcipher_encrypt,
1931 .decrypt = skcipher_decrypt,
1932 .min_keysize = DES3_EDE_KEY_SIZE,
1933 .max_keysize = DES3_EDE_KEY_SIZE,
1934 .ivsize = DES3_EDE_BLOCK_SIZE,
1935 },
1936 .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1937 },
1938 {
1939 .skcipher = {
1940 .base = {
1941 .cra_name = "cbc(des)",
1942 .cra_driver_name = "cbc-des-caam",
1943 .cra_blocksize = DES_BLOCK_SIZE,
1944 },
1945 .setkey = des_skcipher_setkey,
1946 .encrypt = skcipher_encrypt,
1947 .decrypt = skcipher_decrypt,
1948 .min_keysize = DES_KEY_SIZE,
1949 .max_keysize = DES_KEY_SIZE,
1950 .ivsize = DES_BLOCK_SIZE,
1951 },
1952 .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1953 },
1954 {
1955 .skcipher = {
1956 .base = {
1957 .cra_name = "ctr(aes)",
1958 .cra_driver_name = "ctr-aes-caam",
1959 .cra_blocksize = 1,
1960 },
1961 .setkey = ctr_skcipher_setkey,
1962 .encrypt = skcipher_encrypt,
1963 .decrypt = skcipher_decrypt,
1964 .min_keysize = AES_MIN_KEY_SIZE,
1965 .max_keysize = AES_MAX_KEY_SIZE,
1966 .ivsize = AES_BLOCK_SIZE,
1967 .chunksize = AES_BLOCK_SIZE,
1968 },
1969 .caam.class1_alg_type = OP_ALG_ALGSEL_AES |
1970 OP_ALG_AAI_CTR_MOD128,
1971 },
1972 {
1973 .skcipher = {
1974 .base = {
1975 .cra_name = "rfc3686(ctr(aes))",
1976 .cra_driver_name = "rfc3686-ctr-aes-caam",
1977 .cra_blocksize = 1,
1978 },
1979 .setkey = rfc3686_skcipher_setkey,
1980 .encrypt = skcipher_encrypt,
1981 .decrypt = skcipher_decrypt,
1982 .min_keysize = AES_MIN_KEY_SIZE +
1983 CTR_RFC3686_NONCE_SIZE,
1984 .max_keysize = AES_MAX_KEY_SIZE +
1985 CTR_RFC3686_NONCE_SIZE,
1986 .ivsize = CTR_RFC3686_IV_SIZE,
1987 .chunksize = AES_BLOCK_SIZE,
1988 },
1989 .caam = {
1990 .class1_alg_type = OP_ALG_ALGSEL_AES |
1991 OP_ALG_AAI_CTR_MOD128,
1992 .rfc3686 = true,
1993 },
1994 },
1995 {
1996 .skcipher = {
1997 .base = {
1998 .cra_name = "xts(aes)",
1999 .cra_driver_name = "xts-aes-caam",
2000 .cra_blocksize = AES_BLOCK_SIZE,
2001 },
2002 .setkey = xts_skcipher_setkey,
2003 .encrypt = skcipher_encrypt,
2004 .decrypt = skcipher_decrypt,
2005 .min_keysize = 2 * AES_MIN_KEY_SIZE,
2006 .max_keysize = 2 * AES_MAX_KEY_SIZE,
2007 .ivsize = AES_BLOCK_SIZE,
2008 },
2009 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
2010 },
2011 {
2012 .skcipher = {
2013 .base = {
2014 .cra_name = "ecb(des)",
2015 .cra_driver_name = "ecb-des-caam",
2016 .cra_blocksize = DES_BLOCK_SIZE,
2017 },
2018 .setkey = des_skcipher_setkey,
2019 .encrypt = skcipher_encrypt,
2020 .decrypt = skcipher_decrypt,
2021 .min_keysize = DES_KEY_SIZE,
2022 .max_keysize = DES_KEY_SIZE,
2023 },
2024 .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB,
2025 },
2026 {
2027 .skcipher = {
2028 .base = {
2029 .cra_name = "ecb(aes)",
2030 .cra_driver_name = "ecb-aes-caam",
2031 .cra_blocksize = AES_BLOCK_SIZE,
2032 },
2033 .setkey = aes_skcipher_setkey,
2034 .encrypt = skcipher_encrypt,
2035 .decrypt = skcipher_decrypt,
2036 .min_keysize = AES_MIN_KEY_SIZE,
2037 .max_keysize = AES_MAX_KEY_SIZE,
2038 },
2039 .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB,
2040 },
2041 {
2042 .skcipher = {
2043 .base = {
2044 .cra_name = "ecb(des3_ede)",
2045 .cra_driver_name = "ecb-des3-caam",
2046 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2047 },
2048 .setkey = des3_skcipher_setkey,
2049 .encrypt = skcipher_encrypt,
2050 .decrypt = skcipher_decrypt,
2051 .min_keysize = DES3_EDE_KEY_SIZE,
2052 .max_keysize = DES3_EDE_KEY_SIZE,
2053 },
2054 .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB,
2055 },
2056};
2057
2058static struct caam_aead_alg driver_aeads[] = {
2059 {
2060 .aead = {
2061 .base = {
2062 .cra_name = "rfc4106(gcm(aes))",
2063 .cra_driver_name = "rfc4106-gcm-aes-caam",
2064 .cra_blocksize = 1,
2065 },
2066 .setkey = rfc4106_setkey,
2067 .setauthsize = rfc4106_setauthsize,
2068 .encrypt = ipsec_gcm_encrypt,
2069 .decrypt = ipsec_gcm_decrypt,
2070 .ivsize = GCM_RFC4106_IV_SIZE,
2071 .maxauthsize = AES_BLOCK_SIZE,
2072 },
2073 .caam = {
2074 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2075 .nodkp = true,
2076 },
2077 },
2078 {
2079 .aead = {
2080 .base = {
2081 .cra_name = "rfc4543(gcm(aes))",
2082 .cra_driver_name = "rfc4543-gcm-aes-caam",
2083 .cra_blocksize = 1,
2084 },
2085 .setkey = rfc4543_setkey,
2086 .setauthsize = rfc4543_setauthsize,
2087 .encrypt = ipsec_gcm_encrypt,
2088 .decrypt = ipsec_gcm_decrypt,
2089 .ivsize = GCM_RFC4543_IV_SIZE,
2090 .maxauthsize = AES_BLOCK_SIZE,
2091 },
2092 .caam = {
2093 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2094 .nodkp = true,
2095 },
2096 },
2097 /* Galois Counter Mode */
2098 {
2099 .aead = {
2100 .base = {
2101 .cra_name = "gcm(aes)",
2102 .cra_driver_name = "gcm-aes-caam",
2103 .cra_blocksize = 1,
2104 },
2105 .setkey = gcm_setkey,
2106 .setauthsize = gcm_setauthsize,
2107 .encrypt = gcm_encrypt,
2108 .decrypt = gcm_decrypt,
2109 .ivsize = GCM_AES_IV_SIZE,
2110 .maxauthsize = AES_BLOCK_SIZE,
2111 },
2112 .caam = {
2113 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2114 .nodkp = true,
2115 },
2116 },
2117 /* single-pass ipsec_esp descriptor */
2118 {
2119 .aead = {
2120 .base = {
2121 .cra_name = "authenc(hmac(md5),"
2122 "ecb(cipher_null))",
2123 .cra_driver_name = "authenc-hmac-md5-"
2124 "ecb-cipher_null-caam",
2125 .cra_blocksize = NULL_BLOCK_SIZE,
2126 },
2127 .setkey = aead_setkey,
2128 .setauthsize = aead_setauthsize,
2129 .encrypt = aead_encrypt,
2130 .decrypt = aead_decrypt,
2131 .ivsize = NULL_IV_SIZE,
2132 .maxauthsize = MD5_DIGEST_SIZE,
2133 },
2134 .caam = {
2135 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2136 OP_ALG_AAI_HMAC_PRECOMP,
2137 },
2138 },
2139 {
2140 .aead = {
2141 .base = {
2142 .cra_name = "authenc(hmac(sha1),"
2143 "ecb(cipher_null))",
2144 .cra_driver_name = "authenc-hmac-sha1-"
2145 "ecb-cipher_null-caam",
2146 .cra_blocksize = NULL_BLOCK_SIZE,
2147 },
2148 .setkey = aead_setkey,
2149 .setauthsize = aead_setauthsize,
2150 .encrypt = aead_encrypt,
2151 .decrypt = aead_decrypt,
2152 .ivsize = NULL_IV_SIZE,
2153 .maxauthsize = SHA1_DIGEST_SIZE,
2154 },
2155 .caam = {
2156 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2157 OP_ALG_AAI_HMAC_PRECOMP,
2158 },
2159 },
2160 {
2161 .aead = {
2162 .base = {
2163 .cra_name = "authenc(hmac(sha224),"
2164 "ecb(cipher_null))",
2165 .cra_driver_name = "authenc-hmac-sha224-"
2166 "ecb-cipher_null-caam",
2167 .cra_blocksize = NULL_BLOCK_SIZE,
2168 },
2169 .setkey = aead_setkey,
2170 .setauthsize = aead_setauthsize,
2171 .encrypt = aead_encrypt,
2172 .decrypt = aead_decrypt,
2173 .ivsize = NULL_IV_SIZE,
2174 .maxauthsize = SHA224_DIGEST_SIZE,
2175 },
2176 .caam = {
2177 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2178 OP_ALG_AAI_HMAC_PRECOMP,
2179 },
2180 },
2181 {
2182 .aead = {
2183 .base = {
2184 .cra_name = "authenc(hmac(sha256),"
2185 "ecb(cipher_null))",
2186 .cra_driver_name = "authenc-hmac-sha256-"
2187 "ecb-cipher_null-caam",
2188 .cra_blocksize = NULL_BLOCK_SIZE,
2189 },
2190 .setkey = aead_setkey,
2191 .setauthsize = aead_setauthsize,
2192 .encrypt = aead_encrypt,
2193 .decrypt = aead_decrypt,
2194 .ivsize = NULL_IV_SIZE,
2195 .maxauthsize = SHA256_DIGEST_SIZE,
2196 },
2197 .caam = {
2198 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2199 OP_ALG_AAI_HMAC_PRECOMP,
2200 },
2201 },
2202 {
2203 .aead = {
2204 .base = {
2205 .cra_name = "authenc(hmac(sha384),"
2206 "ecb(cipher_null))",
2207 .cra_driver_name = "authenc-hmac-sha384-"
2208 "ecb-cipher_null-caam",
2209 .cra_blocksize = NULL_BLOCK_SIZE,
2210 },
2211 .setkey = aead_setkey,
2212 .setauthsize = aead_setauthsize,
2213 .encrypt = aead_encrypt,
2214 .decrypt = aead_decrypt,
2215 .ivsize = NULL_IV_SIZE,
2216 .maxauthsize = SHA384_DIGEST_SIZE,
2217 },
2218 .caam = {
2219 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2220 OP_ALG_AAI_HMAC_PRECOMP,
2221 },
2222 },
2223 {
2224 .aead = {
2225 .base = {
2226 .cra_name = "authenc(hmac(sha512),"
2227 "ecb(cipher_null))",
2228 .cra_driver_name = "authenc-hmac-sha512-"
2229 "ecb-cipher_null-caam",
2230 .cra_blocksize = NULL_BLOCK_SIZE,
2231 },
2232 .setkey = aead_setkey,
2233 .setauthsize = aead_setauthsize,
2234 .encrypt = aead_encrypt,
2235 .decrypt = aead_decrypt,
2236 .ivsize = NULL_IV_SIZE,
2237 .maxauthsize = SHA512_DIGEST_SIZE,
2238 },
2239 .caam = {
2240 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2241 OP_ALG_AAI_HMAC_PRECOMP,
2242 },
2243 },
2244 {
2245 .aead = {
2246 .base = {
2247 .cra_name = "authenc(hmac(md5),cbc(aes))",
2248 .cra_driver_name = "authenc-hmac-md5-"
2249 "cbc-aes-caam",
2250 .cra_blocksize = AES_BLOCK_SIZE,
2251 },
2252 .setkey = aead_setkey,
2253 .setauthsize = aead_setauthsize,
2254 .encrypt = aead_encrypt,
2255 .decrypt = aead_decrypt,
2256 .ivsize = AES_BLOCK_SIZE,
2257 .maxauthsize = MD5_DIGEST_SIZE,
2258 },
2259 .caam = {
2260 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2261 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2262 OP_ALG_AAI_HMAC_PRECOMP,
2263 },
2264 },
2265 {
2266 .aead = {
2267 .base = {
2268 .cra_name = "echainiv(authenc(hmac(md5),"
2269 "cbc(aes)))",
2270 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2271 "cbc-aes-caam",
2272 .cra_blocksize = AES_BLOCK_SIZE,
2273 },
2274 .setkey = aead_setkey,
2275 .setauthsize = aead_setauthsize,
2276 .encrypt = aead_encrypt,
2277 .decrypt = aead_decrypt,
2278 .ivsize = AES_BLOCK_SIZE,
2279 .maxauthsize = MD5_DIGEST_SIZE,
2280 },
2281 .caam = {
2282 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2283 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2284 OP_ALG_AAI_HMAC_PRECOMP,
2285 .geniv = true,
2286 },
2287 },
2288 {
2289 .aead = {
2290 .base = {
2291 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2292 .cra_driver_name = "authenc-hmac-sha1-"
2293 "cbc-aes-caam",
2294 .cra_blocksize = AES_BLOCK_SIZE,
2295 },
2296 .setkey = aead_setkey,
2297 .setauthsize = aead_setauthsize,
2298 .encrypt = aead_encrypt,
2299 .decrypt = aead_decrypt,
2300 .ivsize = AES_BLOCK_SIZE,
2301 .maxauthsize = SHA1_DIGEST_SIZE,
2302 },
2303 .caam = {
2304 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2305 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2306 OP_ALG_AAI_HMAC_PRECOMP,
2307 },
2308 },
2309 {
2310 .aead = {
2311 .base = {
2312 .cra_name = "echainiv(authenc(hmac(sha1),"
2313 "cbc(aes)))",
2314 .cra_driver_name = "echainiv-authenc-"
2315 "hmac-sha1-cbc-aes-caam",
2316 .cra_blocksize = AES_BLOCK_SIZE,
2317 },
2318 .setkey = aead_setkey,
2319 .setauthsize = aead_setauthsize,
2320 .encrypt = aead_encrypt,
2321 .decrypt = aead_decrypt,
2322 .ivsize = AES_BLOCK_SIZE,
2323 .maxauthsize = SHA1_DIGEST_SIZE,
2324 },
2325 .caam = {
2326 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2327 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2328 OP_ALG_AAI_HMAC_PRECOMP,
2329 .geniv = true,
2330 },
2331 },
2332 {
2333 .aead = {
2334 .base = {
2335 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2336 .cra_driver_name = "authenc-hmac-sha224-"
2337 "cbc-aes-caam",
2338 .cra_blocksize = AES_BLOCK_SIZE,
2339 },
2340 .setkey = aead_setkey,
2341 .setauthsize = aead_setauthsize,
2342 .encrypt = aead_encrypt,
2343 .decrypt = aead_decrypt,
2344 .ivsize = AES_BLOCK_SIZE,
2345 .maxauthsize = SHA224_DIGEST_SIZE,
2346 },
2347 .caam = {
2348 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2349 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2350 OP_ALG_AAI_HMAC_PRECOMP,
2351 },
2352 },
2353 {
2354 .aead = {
2355 .base = {
2356 .cra_name = "echainiv(authenc(hmac(sha224),"
2357 "cbc(aes)))",
2358 .cra_driver_name = "echainiv-authenc-"
2359 "hmac-sha224-cbc-aes-caam",
2360 .cra_blocksize = AES_BLOCK_SIZE,
2361 },
2362 .setkey = aead_setkey,
2363 .setauthsize = aead_setauthsize,
2364 .encrypt = aead_encrypt,
2365 .decrypt = aead_decrypt,
2366 .ivsize = AES_BLOCK_SIZE,
2367 .maxauthsize = SHA224_DIGEST_SIZE,
2368 },
2369 .caam = {
2370 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2371 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2372 OP_ALG_AAI_HMAC_PRECOMP,
2373 .geniv = true,
2374 },
2375 },
2376 {
2377 .aead = {
2378 .base = {
2379 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2380 .cra_driver_name = "authenc-hmac-sha256-"
2381 "cbc-aes-caam",
2382 .cra_blocksize = AES_BLOCK_SIZE,
2383 },
2384 .setkey = aead_setkey,
2385 .setauthsize = aead_setauthsize,
2386 .encrypt = aead_encrypt,
2387 .decrypt = aead_decrypt,
2388 .ivsize = AES_BLOCK_SIZE,
2389 .maxauthsize = SHA256_DIGEST_SIZE,
2390 },
2391 .caam = {
2392 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2393 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2394 OP_ALG_AAI_HMAC_PRECOMP,
2395 },
2396 },
2397 {
2398 .aead = {
2399 .base = {
2400 .cra_name = "echainiv(authenc(hmac(sha256),"
2401 "cbc(aes)))",
2402 .cra_driver_name = "echainiv-authenc-"
2403 "hmac-sha256-cbc-aes-caam",
2404 .cra_blocksize = AES_BLOCK_SIZE,
2405 },
2406 .setkey = aead_setkey,
2407 .setauthsize = aead_setauthsize,
2408 .encrypt = aead_encrypt,
2409 .decrypt = aead_decrypt,
2410 .ivsize = AES_BLOCK_SIZE,
2411 .maxauthsize = SHA256_DIGEST_SIZE,
2412 },
2413 .caam = {
2414 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2415 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2416 OP_ALG_AAI_HMAC_PRECOMP,
2417 .geniv = true,
2418 },
2419 },
2420 {
2421 .aead = {
2422 .base = {
2423 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2424 .cra_driver_name = "authenc-hmac-sha384-"
2425 "cbc-aes-caam",
2426 .cra_blocksize = AES_BLOCK_SIZE,
2427 },
2428 .setkey = aead_setkey,
2429 .setauthsize = aead_setauthsize,
2430 .encrypt = aead_encrypt,
2431 .decrypt = aead_decrypt,
2432 .ivsize = AES_BLOCK_SIZE,
2433 .maxauthsize = SHA384_DIGEST_SIZE,
2434 },
2435 .caam = {
2436 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2437 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2438 OP_ALG_AAI_HMAC_PRECOMP,
2439 },
2440 },
2441 {
2442 .aead = {
2443 .base = {
2444 .cra_name = "echainiv(authenc(hmac(sha384),"
2445 "cbc(aes)))",
2446 .cra_driver_name = "echainiv-authenc-"
2447 "hmac-sha384-cbc-aes-caam",
2448 .cra_blocksize = AES_BLOCK_SIZE,
2449 },
2450 .setkey = aead_setkey,
2451 .setauthsize = aead_setauthsize,
2452 .encrypt = aead_encrypt,
2453 .decrypt = aead_decrypt,
2454 .ivsize = AES_BLOCK_SIZE,
2455 .maxauthsize = SHA384_DIGEST_SIZE,
2456 },
2457 .caam = {
2458 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2459 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2460 OP_ALG_AAI_HMAC_PRECOMP,
2461 .geniv = true,
2462 },
2463 },
2464 {
2465 .aead = {
2466 .base = {
2467 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2468 .cra_driver_name = "authenc-hmac-sha512-"
2469 "cbc-aes-caam",
2470 .cra_blocksize = AES_BLOCK_SIZE,
2471 },
2472 .setkey = aead_setkey,
2473 .setauthsize = aead_setauthsize,
2474 .encrypt = aead_encrypt,
2475 .decrypt = aead_decrypt,
2476 .ivsize = AES_BLOCK_SIZE,
2477 .maxauthsize = SHA512_DIGEST_SIZE,
2478 },
2479 .caam = {
2480 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2481 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2482 OP_ALG_AAI_HMAC_PRECOMP,
2483 },
2484 },
2485 {
2486 .aead = {
2487 .base = {
2488 .cra_name = "echainiv(authenc(hmac(sha512),"
2489 "cbc(aes)))",
2490 .cra_driver_name = "echainiv-authenc-"
2491 "hmac-sha512-cbc-aes-caam",
2492 .cra_blocksize = AES_BLOCK_SIZE,
2493 },
2494 .setkey = aead_setkey,
2495 .setauthsize = aead_setauthsize,
2496 .encrypt = aead_encrypt,
2497 .decrypt = aead_decrypt,
2498 .ivsize = AES_BLOCK_SIZE,
2499 .maxauthsize = SHA512_DIGEST_SIZE,
2500 },
2501 .caam = {
2502 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
2503 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2504 OP_ALG_AAI_HMAC_PRECOMP,
2505 .geniv = true,
2506 },
2507 },
2508 {
2509 .aead = {
2510 .base = {
2511 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2512 .cra_driver_name = "authenc-hmac-md5-"
2513 "cbc-des3_ede-caam",
2514 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2515 },
2516 .setkey = des3_aead_setkey,
2517 .setauthsize = aead_setauthsize,
2518 .encrypt = aead_encrypt,
2519 .decrypt = aead_decrypt,
2520 .ivsize = DES3_EDE_BLOCK_SIZE,
2521 .maxauthsize = MD5_DIGEST_SIZE,
2522 },
2523 .caam = {
2524 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2525 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2526 OP_ALG_AAI_HMAC_PRECOMP,
2527 }
2528 },
2529 {
2530 .aead = {
2531 .base = {
2532 .cra_name = "echainiv(authenc(hmac(md5),"
2533 "cbc(des3_ede)))",
2534 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2535 "cbc-des3_ede-caam",
2536 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2537 },
2538 .setkey = des3_aead_setkey,
2539 .setauthsize = aead_setauthsize,
2540 .encrypt = aead_encrypt,
2541 .decrypt = aead_decrypt,
2542 .ivsize = DES3_EDE_BLOCK_SIZE,
2543 .maxauthsize = MD5_DIGEST_SIZE,
2544 },
2545 .caam = {
2546 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2547 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2548 OP_ALG_AAI_HMAC_PRECOMP,
2549 .geniv = true,
2550 }
2551 },
2552 {
2553 .aead = {
2554 .base = {
2555 .cra_name = "authenc(hmac(sha1),"
2556 "cbc(des3_ede))",
2557 .cra_driver_name = "authenc-hmac-sha1-"
2558 "cbc-des3_ede-caam",
2559 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2560 },
2561 .setkey = des3_aead_setkey,
2562 .setauthsize = aead_setauthsize,
2563 .encrypt = aead_encrypt,
2564 .decrypt = aead_decrypt,
2565 .ivsize = DES3_EDE_BLOCK_SIZE,
2566 .maxauthsize = SHA1_DIGEST_SIZE,
2567 },
2568 .caam = {
2569 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2570 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2571 OP_ALG_AAI_HMAC_PRECOMP,
2572 },
2573 },
2574 {
2575 .aead = {
2576 .base = {
2577 .cra_name = "echainiv(authenc(hmac(sha1),"
2578 "cbc(des3_ede)))",
2579 .cra_driver_name = "echainiv-authenc-"
2580 "hmac-sha1-"
2581 "cbc-des3_ede-caam",
2582 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2583 },
2584 .setkey = des3_aead_setkey,
2585 .setauthsize = aead_setauthsize,
2586 .encrypt = aead_encrypt,
2587 .decrypt = aead_decrypt,
2588 .ivsize = DES3_EDE_BLOCK_SIZE,
2589 .maxauthsize = SHA1_DIGEST_SIZE,
2590 },
2591 .caam = {
2592 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2593 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2594 OP_ALG_AAI_HMAC_PRECOMP,
2595 .geniv = true,
2596 },
2597 },
2598 {
2599 .aead = {
2600 .base = {
2601 .cra_name = "authenc(hmac(sha224),"
2602 "cbc(des3_ede))",
2603 .cra_driver_name = "authenc-hmac-sha224-"
2604 "cbc-des3_ede-caam",
2605 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2606 },
2607 .setkey = des3_aead_setkey,
2608 .setauthsize = aead_setauthsize,
2609 .encrypt = aead_encrypt,
2610 .decrypt = aead_decrypt,
2611 .ivsize = DES3_EDE_BLOCK_SIZE,
2612 .maxauthsize = SHA224_DIGEST_SIZE,
2613 },
2614 .caam = {
2615 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2616 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2617 OP_ALG_AAI_HMAC_PRECOMP,
2618 },
2619 },
2620 {
2621 .aead = {
2622 .base = {
2623 .cra_name = "echainiv(authenc(hmac(sha224),"
2624 "cbc(des3_ede)))",
2625 .cra_driver_name = "echainiv-authenc-"
2626 "hmac-sha224-"
2627 "cbc-des3_ede-caam",
2628 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2629 },
2630 .setkey = des3_aead_setkey,
2631 .setauthsize = aead_setauthsize,
2632 .encrypt = aead_encrypt,
2633 .decrypt = aead_decrypt,
2634 .ivsize = DES3_EDE_BLOCK_SIZE,
2635 .maxauthsize = SHA224_DIGEST_SIZE,
2636 },
2637 .caam = {
2638 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2639 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2640 OP_ALG_AAI_HMAC_PRECOMP,
2641 .geniv = true,
2642 },
2643 },
2644 {
2645 .aead = {
2646 .base = {
2647 .cra_name = "authenc(hmac(sha256),"
2648 "cbc(des3_ede))",
2649 .cra_driver_name = "authenc-hmac-sha256-"
2650 "cbc-des3_ede-caam",
2651 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2652 },
2653 .setkey = des3_aead_setkey,
2654 .setauthsize = aead_setauthsize,
2655 .encrypt = aead_encrypt,
2656 .decrypt = aead_decrypt,
2657 .ivsize = DES3_EDE_BLOCK_SIZE,
2658 .maxauthsize = SHA256_DIGEST_SIZE,
2659 },
2660 .caam = {
2661 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2662 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2663 OP_ALG_AAI_HMAC_PRECOMP,
2664 },
2665 },
2666 {
2667 .aead = {
2668 .base = {
2669 .cra_name = "echainiv(authenc(hmac(sha256),"
2670 "cbc(des3_ede)))",
2671 .cra_driver_name = "echainiv-authenc-"
2672 "hmac-sha256-"
2673 "cbc-des3_ede-caam",
2674 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2675 },
2676 .setkey = des3_aead_setkey,
2677 .setauthsize = aead_setauthsize,
2678 .encrypt = aead_encrypt,
2679 .decrypt = aead_decrypt,
2680 .ivsize = DES3_EDE_BLOCK_SIZE,
2681 .maxauthsize = SHA256_DIGEST_SIZE,
2682 },
2683 .caam = {
2684 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2685 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2686 OP_ALG_AAI_HMAC_PRECOMP,
2687 .geniv = true,
2688 },
2689 },
2690 {
2691 .aead = {
2692 .base = {
2693 .cra_name = "authenc(hmac(sha384),"
2694 "cbc(des3_ede))",
2695 .cra_driver_name = "authenc-hmac-sha384-"
2696 "cbc-des3_ede-caam",
2697 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2698 },
2699 .setkey = des3_aead_setkey,
2700 .setauthsize = aead_setauthsize,
2701 .encrypt = aead_encrypt,
2702 .decrypt = aead_decrypt,
2703 .ivsize = DES3_EDE_BLOCK_SIZE,
2704 .maxauthsize = SHA384_DIGEST_SIZE,
2705 },
2706 .caam = {
2707 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2708 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2709 OP_ALG_AAI_HMAC_PRECOMP,
2710 },
2711 },
2712 {
2713 .aead = {
2714 .base = {
2715 .cra_name = "echainiv(authenc(hmac(sha384),"
2716 "cbc(des3_ede)))",
2717 .cra_driver_name = "echainiv-authenc-"
2718 "hmac-sha384-"
2719 "cbc-des3_ede-caam",
2720 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2721 },
2722 .setkey = des3_aead_setkey,
2723 .setauthsize = aead_setauthsize,
2724 .encrypt = aead_encrypt,
2725 .decrypt = aead_decrypt,
2726 .ivsize = DES3_EDE_BLOCK_SIZE,
2727 .maxauthsize = SHA384_DIGEST_SIZE,
2728 },
2729 .caam = {
2730 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2731 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2732 OP_ALG_AAI_HMAC_PRECOMP,
2733 .geniv = true,
2734 },
2735 },
2736 {
2737 .aead = {
2738 .base = {
2739 .cra_name = "authenc(hmac(sha512),"
2740 "cbc(des3_ede))",
2741 .cra_driver_name = "authenc-hmac-sha512-"
2742 "cbc-des3_ede-caam",
2743 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2744 },
2745 .setkey = des3_aead_setkey,
2746 .setauthsize = aead_setauthsize,
2747 .encrypt = aead_encrypt,
2748 .decrypt = aead_decrypt,
2749 .ivsize = DES3_EDE_BLOCK_SIZE,
2750 .maxauthsize = SHA512_DIGEST_SIZE,
2751 },
2752 .caam = {
2753 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2754 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2755 OP_ALG_AAI_HMAC_PRECOMP,
2756 },
2757 },
2758 {
2759 .aead = {
2760 .base = {
2761 .cra_name = "echainiv(authenc(hmac(sha512),"
2762 "cbc(des3_ede)))",
2763 .cra_driver_name = "echainiv-authenc-"
2764 "hmac-sha512-"
2765 "cbc-des3_ede-caam",
2766 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2767 },
2768 .setkey = des3_aead_setkey,
2769 .setauthsize = aead_setauthsize,
2770 .encrypt = aead_encrypt,
2771 .decrypt = aead_decrypt,
2772 .ivsize = DES3_EDE_BLOCK_SIZE,
2773 .maxauthsize = SHA512_DIGEST_SIZE,
2774 },
2775 .caam = {
2776 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2777 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
2778 OP_ALG_AAI_HMAC_PRECOMP,
2779 .geniv = true,
2780 },
2781 },
2782 {
2783 .aead = {
2784 .base = {
2785 .cra_name = "authenc(hmac(md5),cbc(des))",
2786 .cra_driver_name = "authenc-hmac-md5-"
2787 "cbc-des-caam",
2788 .cra_blocksize = DES_BLOCK_SIZE,
2789 },
2790 .setkey = aead_setkey,
2791 .setauthsize = aead_setauthsize,
2792 .encrypt = aead_encrypt,
2793 .decrypt = aead_decrypt,
2794 .ivsize = DES_BLOCK_SIZE,
2795 .maxauthsize = MD5_DIGEST_SIZE,
2796 },
2797 .caam = {
2798 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2799 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2800 OP_ALG_AAI_HMAC_PRECOMP,
2801 },
2802 },
2803 {
2804 .aead = {
2805 .base = {
2806 .cra_name = "echainiv(authenc(hmac(md5),"
2807 "cbc(des)))",
2808 .cra_driver_name = "echainiv-authenc-hmac-md5-"
2809 "cbc-des-caam",
2810 .cra_blocksize = DES_BLOCK_SIZE,
2811 },
2812 .setkey = aead_setkey,
2813 .setauthsize = aead_setauthsize,
2814 .encrypt = aead_encrypt,
2815 .decrypt = aead_decrypt,
2816 .ivsize = DES_BLOCK_SIZE,
2817 .maxauthsize = MD5_DIGEST_SIZE,
2818 },
2819 .caam = {
2820 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2821 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
2822 OP_ALG_AAI_HMAC_PRECOMP,
2823 .geniv = true,
2824 },
2825 },
2826 {
2827 .aead = {
2828 .base = {
2829 .cra_name = "authenc(hmac(sha1),cbc(des))",
2830 .cra_driver_name = "authenc-hmac-sha1-"
2831 "cbc-des-caam",
2832 .cra_blocksize = DES_BLOCK_SIZE,
2833 },
2834 .setkey = aead_setkey,
2835 .setauthsize = aead_setauthsize,
2836 .encrypt = aead_encrypt,
2837 .decrypt = aead_decrypt,
2838 .ivsize = DES_BLOCK_SIZE,
2839 .maxauthsize = SHA1_DIGEST_SIZE,
2840 },
2841 .caam = {
2842 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2843 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2844 OP_ALG_AAI_HMAC_PRECOMP,
2845 },
2846 },
2847 {
2848 .aead = {
2849 .base = {
2850 .cra_name = "echainiv(authenc(hmac(sha1),"
2851 "cbc(des)))",
2852 .cra_driver_name = "echainiv-authenc-"
2853 "hmac-sha1-cbc-des-caam",
2854 .cra_blocksize = DES_BLOCK_SIZE,
2855 },
2856 .setkey = aead_setkey,
2857 .setauthsize = aead_setauthsize,
2858 .encrypt = aead_encrypt,
2859 .decrypt = aead_decrypt,
2860 .ivsize = DES_BLOCK_SIZE,
2861 .maxauthsize = SHA1_DIGEST_SIZE,
2862 },
2863 .caam = {
2864 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2865 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
2866 OP_ALG_AAI_HMAC_PRECOMP,
2867 .geniv = true,
2868 },
2869 },
2870 {
2871 .aead = {
2872 .base = {
2873 .cra_name = "authenc(hmac(sha224),cbc(des))",
2874 .cra_driver_name = "authenc-hmac-sha224-"
2875 "cbc-des-caam",
2876 .cra_blocksize = DES_BLOCK_SIZE,
2877 },
2878 .setkey = aead_setkey,
2879 .setauthsize = aead_setauthsize,
2880 .encrypt = aead_encrypt,
2881 .decrypt = aead_decrypt,
2882 .ivsize = DES_BLOCK_SIZE,
2883 .maxauthsize = SHA224_DIGEST_SIZE,
2884 },
2885 .caam = {
2886 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2887 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2888 OP_ALG_AAI_HMAC_PRECOMP,
2889 },
2890 },
2891 {
2892 .aead = {
2893 .base = {
2894 .cra_name = "echainiv(authenc(hmac(sha224),"
2895 "cbc(des)))",
2896 .cra_driver_name = "echainiv-authenc-"
2897 "hmac-sha224-cbc-des-caam",
2898 .cra_blocksize = DES_BLOCK_SIZE,
2899 },
2900 .setkey = aead_setkey,
2901 .setauthsize = aead_setauthsize,
2902 .encrypt = aead_encrypt,
2903 .decrypt = aead_decrypt,
2904 .ivsize = DES_BLOCK_SIZE,
2905 .maxauthsize = SHA224_DIGEST_SIZE,
2906 },
2907 .caam = {
2908 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2909 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
2910 OP_ALG_AAI_HMAC_PRECOMP,
2911 .geniv = true,
2912 },
2913 },
2914 {
2915 .aead = {
2916 .base = {
2917 .cra_name = "authenc(hmac(sha256),cbc(des))",
2918 .cra_driver_name = "authenc-hmac-sha256-"
2919 "cbc-des-caam",
2920 .cra_blocksize = DES_BLOCK_SIZE,
2921 },
2922 .setkey = aead_setkey,
2923 .setauthsize = aead_setauthsize,
2924 .encrypt = aead_encrypt,
2925 .decrypt = aead_decrypt,
2926 .ivsize = DES_BLOCK_SIZE,
2927 .maxauthsize = SHA256_DIGEST_SIZE,
2928 },
2929 .caam = {
2930 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2931 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2932 OP_ALG_AAI_HMAC_PRECOMP,
2933 },
2934 },
2935 {
2936 .aead = {
2937 .base = {
2938 .cra_name = "echainiv(authenc(hmac(sha256),"
2939 "cbc(des)))",
2940 .cra_driver_name = "echainiv-authenc-"
2941 "hmac-sha256-cbc-des-caam",
2942 .cra_blocksize = DES_BLOCK_SIZE,
2943 },
2944 .setkey = aead_setkey,
2945 .setauthsize = aead_setauthsize,
2946 .encrypt = aead_encrypt,
2947 .decrypt = aead_decrypt,
2948 .ivsize = DES_BLOCK_SIZE,
2949 .maxauthsize = SHA256_DIGEST_SIZE,
2950 },
2951 .caam = {
2952 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2953 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
2954 OP_ALG_AAI_HMAC_PRECOMP,
2955 .geniv = true,
2956 },
2957 },
2958 {
2959 .aead = {
2960 .base = {
2961 .cra_name = "authenc(hmac(sha384),cbc(des))",
2962 .cra_driver_name = "authenc-hmac-sha384-"
2963 "cbc-des-caam",
2964 .cra_blocksize = DES_BLOCK_SIZE,
2965 },
2966 .setkey = aead_setkey,
2967 .setauthsize = aead_setauthsize,
2968 .encrypt = aead_encrypt,
2969 .decrypt = aead_decrypt,
2970 .ivsize = DES_BLOCK_SIZE,
2971 .maxauthsize = SHA384_DIGEST_SIZE,
2972 },
2973 .caam = {
2974 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2975 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2976 OP_ALG_AAI_HMAC_PRECOMP,
2977 },
2978 },
2979 {
2980 .aead = {
2981 .base = {
2982 .cra_name = "echainiv(authenc(hmac(sha384),"
2983 "cbc(des)))",
2984 .cra_driver_name = "echainiv-authenc-"
2985 "hmac-sha384-cbc-des-caam",
2986 .cra_blocksize = DES_BLOCK_SIZE,
2987 },
2988 .setkey = aead_setkey,
2989 .setauthsize = aead_setauthsize,
2990 .encrypt = aead_encrypt,
2991 .decrypt = aead_decrypt,
2992 .ivsize = DES_BLOCK_SIZE,
2993 .maxauthsize = SHA384_DIGEST_SIZE,
2994 },
2995 .caam = {
2996 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2997 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
2998 OP_ALG_AAI_HMAC_PRECOMP,
2999 .geniv = true,
3000 },
3001 },
3002 {
3003 .aead = {
3004 .base = {
3005 .cra_name = "authenc(hmac(sha512),cbc(des))",
3006 .cra_driver_name = "authenc-hmac-sha512-"
3007 "cbc-des-caam",
3008 .cra_blocksize = DES_BLOCK_SIZE,
3009 },
3010 .setkey = aead_setkey,
3011 .setauthsize = aead_setauthsize,
3012 .encrypt = aead_encrypt,
3013 .decrypt = aead_decrypt,
3014 .ivsize = DES_BLOCK_SIZE,
3015 .maxauthsize = SHA512_DIGEST_SIZE,
3016 },
3017 .caam = {
3018 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
3019 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3020 OP_ALG_AAI_HMAC_PRECOMP,
3021 },
3022 },
3023 {
3024 .aead = {
3025 .base = {
3026 .cra_name = "echainiv(authenc(hmac(sha512),"
3027 "cbc(des)))",
3028 .cra_driver_name = "echainiv-authenc-"
3029 "hmac-sha512-cbc-des-caam",
3030 .cra_blocksize = DES_BLOCK_SIZE,
3031 },
3032 .setkey = aead_setkey,
3033 .setauthsize = aead_setauthsize,
3034 .encrypt = aead_encrypt,
3035 .decrypt = aead_decrypt,
3036 .ivsize = DES_BLOCK_SIZE,
3037 .maxauthsize = SHA512_DIGEST_SIZE,
3038 },
3039 .caam = {
3040 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
3041 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3042 OP_ALG_AAI_HMAC_PRECOMP,
3043 .geniv = true,
3044 },
3045 },
3046 {
3047 .aead = {
3048 .base = {
3049 .cra_name = "authenc(hmac(md5),"
3050 "rfc3686(ctr(aes)))",
3051 .cra_driver_name = "authenc-hmac-md5-"
3052 "rfc3686-ctr-aes-caam",
3053 .cra_blocksize = 1,
3054 },
3055 .setkey = aead_setkey,
3056 .setauthsize = aead_setauthsize,
3057 .encrypt = aead_encrypt,
3058 .decrypt = aead_decrypt,
3059 .ivsize = CTR_RFC3686_IV_SIZE,
3060 .maxauthsize = MD5_DIGEST_SIZE,
3061 },
3062 .caam = {
3063 .class1_alg_type = OP_ALG_ALGSEL_AES |
3064 OP_ALG_AAI_CTR_MOD128,
3065 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
3066 OP_ALG_AAI_HMAC_PRECOMP,
3067 .rfc3686 = true,
3068 },
3069 },
3070 {
3071 .aead = {
3072 .base = {
3073 .cra_name = "seqiv(authenc("
3074 "hmac(md5),rfc3686(ctr(aes))))",
3075 .cra_driver_name = "seqiv-authenc-hmac-md5-"
3076 "rfc3686-ctr-aes-caam",
3077 .cra_blocksize = 1,
3078 },
3079 .setkey = aead_setkey,
3080 .setauthsize = aead_setauthsize,
3081 .encrypt = aead_encrypt,
3082 .decrypt = aead_decrypt,
3083 .ivsize = CTR_RFC3686_IV_SIZE,
3084 .maxauthsize = MD5_DIGEST_SIZE,
3085 },
3086 .caam = {
3087 .class1_alg_type = OP_ALG_ALGSEL_AES |
3088 OP_ALG_AAI_CTR_MOD128,
3089 .class2_alg_type = OP_ALG_ALGSEL_MD5 |
3090 OP_ALG_AAI_HMAC_PRECOMP,
3091 .rfc3686 = true,
3092 .geniv = true,
3093 },
3094 },
3095 {
3096 .aead = {
3097 .base = {
3098 .cra_name = "authenc(hmac(sha1),"
3099 "rfc3686(ctr(aes)))",
3100 .cra_driver_name = "authenc-hmac-sha1-"
3101 "rfc3686-ctr-aes-caam",
3102 .cra_blocksize = 1,
3103 },
3104 .setkey = aead_setkey,
3105 .setauthsize = aead_setauthsize,
3106 .encrypt = aead_encrypt,
3107 .decrypt = aead_decrypt,
3108 .ivsize = CTR_RFC3686_IV_SIZE,
3109 .maxauthsize = SHA1_DIGEST_SIZE,
3110 },
3111 .caam = {
3112 .class1_alg_type = OP_ALG_ALGSEL_AES |
3113 OP_ALG_AAI_CTR_MOD128,
3114 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
3115 OP_ALG_AAI_HMAC_PRECOMP,
3116 .rfc3686 = true,
3117 },
3118 },
3119 {
3120 .aead = {
3121 .base = {
3122 .cra_name = "seqiv(authenc("
3123 "hmac(sha1),rfc3686(ctr(aes))))",
3124 .cra_driver_name = "seqiv-authenc-hmac-sha1-"
3125 "rfc3686-ctr-aes-caam",
3126 .cra_blocksize = 1,
3127 },
3128 .setkey = aead_setkey,
3129 .setauthsize = aead_setauthsize,
3130 .encrypt = aead_encrypt,
3131 .decrypt = aead_decrypt,
3132 .ivsize = CTR_RFC3686_IV_SIZE,
3133 .maxauthsize = SHA1_DIGEST_SIZE,
3134 },
3135 .caam = {
3136 .class1_alg_type = OP_ALG_ALGSEL_AES |
3137 OP_ALG_AAI_CTR_MOD128,
3138 .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
3139 OP_ALG_AAI_HMAC_PRECOMP,
3140 .rfc3686 = true,
3141 .geniv = true,
3142 },
3143 },
3144 {
3145 .aead = {
3146 .base = {
3147 .cra_name = "authenc(hmac(sha224),"
3148 "rfc3686(ctr(aes)))",
3149 .cra_driver_name = "authenc-hmac-sha224-"
3150 "rfc3686-ctr-aes-caam",
3151 .cra_blocksize = 1,
3152 },
3153 .setkey = aead_setkey,
3154 .setauthsize = aead_setauthsize,
3155 .encrypt = aead_encrypt,
3156 .decrypt = aead_decrypt,
3157 .ivsize = CTR_RFC3686_IV_SIZE,
3158 .maxauthsize = SHA224_DIGEST_SIZE,
3159 },
3160 .caam = {
3161 .class1_alg_type = OP_ALG_ALGSEL_AES |
3162 OP_ALG_AAI_CTR_MOD128,
3163 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
3164 OP_ALG_AAI_HMAC_PRECOMP,
3165 .rfc3686 = true,
3166 },
3167 },
3168 {
3169 .aead = {
3170 .base = {
3171 .cra_name = "seqiv(authenc("
3172 "hmac(sha224),rfc3686(ctr(aes))))",
3173 .cra_driver_name = "seqiv-authenc-hmac-sha224-"
3174 "rfc3686-ctr-aes-caam",
3175 .cra_blocksize = 1,
3176 },
3177 .setkey = aead_setkey,
3178 .setauthsize = aead_setauthsize,
3179 .encrypt = aead_encrypt,
3180 .decrypt = aead_decrypt,
3181 .ivsize = CTR_RFC3686_IV_SIZE,
3182 .maxauthsize = SHA224_DIGEST_SIZE,
3183 },
3184 .caam = {
3185 .class1_alg_type = OP_ALG_ALGSEL_AES |
3186 OP_ALG_AAI_CTR_MOD128,
3187 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
3188 OP_ALG_AAI_HMAC_PRECOMP,
3189 .rfc3686 = true,
3190 .geniv = true,
3191 },
3192 },
3193 {
3194 .aead = {
3195 .base = {
3196 .cra_name = "authenc(hmac(sha256),"
3197 "rfc3686(ctr(aes)))",
3198 .cra_driver_name = "authenc-hmac-sha256-"
3199 "rfc3686-ctr-aes-caam",
3200 .cra_blocksize = 1,
3201 },
3202 .setkey = aead_setkey,
3203 .setauthsize = aead_setauthsize,
3204 .encrypt = aead_encrypt,
3205 .decrypt = aead_decrypt,
3206 .ivsize = CTR_RFC3686_IV_SIZE,
3207 .maxauthsize = SHA256_DIGEST_SIZE,
3208 },
3209 .caam = {
3210 .class1_alg_type = OP_ALG_ALGSEL_AES |
3211 OP_ALG_AAI_CTR_MOD128,
3212 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
3213 OP_ALG_AAI_HMAC_PRECOMP,
3214 .rfc3686 = true,
3215 },
3216 },
3217 {
3218 .aead = {
3219 .base = {
3220 .cra_name = "seqiv(authenc(hmac(sha256),"
3221 "rfc3686(ctr(aes))))",
3222 .cra_driver_name = "seqiv-authenc-hmac-sha256-"
3223 "rfc3686-ctr-aes-caam",
3224 .cra_blocksize = 1,
3225 },
3226 .setkey = aead_setkey,
3227 .setauthsize = aead_setauthsize,
3228 .encrypt = aead_encrypt,
3229 .decrypt = aead_decrypt,
3230 .ivsize = CTR_RFC3686_IV_SIZE,
3231 .maxauthsize = SHA256_DIGEST_SIZE,
3232 },
3233 .caam = {
3234 .class1_alg_type = OP_ALG_ALGSEL_AES |
3235 OP_ALG_AAI_CTR_MOD128,
3236 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
3237 OP_ALG_AAI_HMAC_PRECOMP,
3238 .rfc3686 = true,
3239 .geniv = true,
3240 },
3241 },
3242 {
3243 .aead = {
3244 .base = {
3245 .cra_name = "authenc(hmac(sha384),"
3246 "rfc3686(ctr(aes)))",
3247 .cra_driver_name = "authenc-hmac-sha384-"
3248 "rfc3686-ctr-aes-caam",
3249 .cra_blocksize = 1,
3250 },
3251 .setkey = aead_setkey,
3252 .setauthsize = aead_setauthsize,
3253 .encrypt = aead_encrypt,
3254 .decrypt = aead_decrypt,
3255 .ivsize = CTR_RFC3686_IV_SIZE,
3256 .maxauthsize = SHA384_DIGEST_SIZE,
3257 },
3258 .caam = {
3259 .class1_alg_type = OP_ALG_ALGSEL_AES |
3260 OP_ALG_AAI_CTR_MOD128,
3261 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
3262 OP_ALG_AAI_HMAC_PRECOMP,
3263 .rfc3686 = true,
3264 },
3265 },
3266 {
3267 .aead = {
3268 .base = {
3269 .cra_name = "seqiv(authenc(hmac(sha384),"
3270 "rfc3686(ctr(aes))))",
3271 .cra_driver_name = "seqiv-authenc-hmac-sha384-"
3272 "rfc3686-ctr-aes-caam",
3273 .cra_blocksize = 1,
3274 },
3275 .setkey = aead_setkey,
3276 .setauthsize = aead_setauthsize,
3277 .encrypt = aead_encrypt,
3278 .decrypt = aead_decrypt,
3279 .ivsize = CTR_RFC3686_IV_SIZE,
3280 .maxauthsize = SHA384_DIGEST_SIZE,
3281 },
3282 .caam = {
3283 .class1_alg_type = OP_ALG_ALGSEL_AES |
3284 OP_ALG_AAI_CTR_MOD128,
3285 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
3286 OP_ALG_AAI_HMAC_PRECOMP,
3287 .rfc3686 = true,
3288 .geniv = true,
3289 },
3290 },
3291 {
3292 .aead = {
3293 .base = {
3294 .cra_name = "authenc(hmac(sha512),"
3295 "rfc3686(ctr(aes)))",
3296 .cra_driver_name = "authenc-hmac-sha512-"
3297 "rfc3686-ctr-aes-caam",
3298 .cra_blocksize = 1,
3299 },
3300 .setkey = aead_setkey,
3301 .setauthsize = aead_setauthsize,
3302 .encrypt = aead_encrypt,
3303 .decrypt = aead_decrypt,
3304 .ivsize = CTR_RFC3686_IV_SIZE,
3305 .maxauthsize = SHA512_DIGEST_SIZE,
3306 },
3307 .caam = {
3308 .class1_alg_type = OP_ALG_ALGSEL_AES |
3309 OP_ALG_AAI_CTR_MOD128,
3310 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3311 OP_ALG_AAI_HMAC_PRECOMP,
3312 .rfc3686 = true,
3313 },
3314 },
3315 {
3316 .aead = {
3317 .base = {
3318 .cra_name = "seqiv(authenc(hmac(sha512),"
3319 "rfc3686(ctr(aes))))",
3320 .cra_driver_name = "seqiv-authenc-hmac-sha512-"
3321 "rfc3686-ctr-aes-caam",
3322 .cra_blocksize = 1,
3323 },
3324 .setkey = aead_setkey,
3325 .setauthsize = aead_setauthsize,
3326 .encrypt = aead_encrypt,
3327 .decrypt = aead_decrypt,
3328 .ivsize = CTR_RFC3686_IV_SIZE,
3329 .maxauthsize = SHA512_DIGEST_SIZE,
3330 },
3331 .caam = {
3332 .class1_alg_type = OP_ALG_ALGSEL_AES |
3333 OP_ALG_AAI_CTR_MOD128,
3334 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
3335 OP_ALG_AAI_HMAC_PRECOMP,
3336 .rfc3686 = true,
3337 .geniv = true,
3338 },
3339 },
3340 {
3341 .aead = {
3342 .base = {
3343 .cra_name = "rfc7539(chacha20,poly1305)",
3344 .cra_driver_name = "rfc7539-chacha20-poly1305-"
3345 "caam",
3346 .cra_blocksize = 1,
3347 },
3348 .setkey = chachapoly_setkey,
3349 .setauthsize = chachapoly_setauthsize,
3350 .encrypt = chachapoly_encrypt,
3351 .decrypt = chachapoly_decrypt,
3352 .ivsize = CHACHAPOLY_IV_SIZE,
3353 .maxauthsize = POLY1305_DIGEST_SIZE,
3354 },
3355 .caam = {
3356 .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
3357 OP_ALG_AAI_AEAD,
3358 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3359 OP_ALG_AAI_AEAD,
3360 .nodkp = true,
3361 },
3362 },
3363 {
3364 .aead = {
3365 .base = {
3366 .cra_name = "rfc7539esp(chacha20,poly1305)",
3367 .cra_driver_name = "rfc7539esp-chacha20-"
3368 "poly1305-caam",
3369 .cra_blocksize = 1,
3370 },
3371 .setkey = chachapoly_setkey,
3372 .setauthsize = chachapoly_setauthsize,
3373 .encrypt = chachapoly_encrypt,
3374 .decrypt = chachapoly_decrypt,
3375 .ivsize = 8,
3376 .maxauthsize = POLY1305_DIGEST_SIZE,
3377 },
3378 .caam = {
3379 .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
3380 OP_ALG_AAI_AEAD,
3381 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3382 OP_ALG_AAI_AEAD,
3383 .nodkp = true,
3384 },
3385 },
3386};
3387
3388static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
3389 bool uses_dkp)
3390{
3391 dma_addr_t dma_addr;
3392 struct caam_drv_private *priv;
3393
3394 ctx->jrdev = caam_jr_alloc();
3395 if (IS_ERR(ctx->jrdev)) {
3396 pr_err("Job Ring Device allocation for transform failed\n");
3397 return PTR_ERR(ctx->jrdev);
3398 }
3399
3400 priv = dev_get_drvdata(ctx->jrdev->parent);
3401 if (priv->era >= 6 && uses_dkp)
3402 ctx->dir = DMA_BIDIRECTIONAL;
3403 else
3404 ctx->dir = DMA_TO_DEVICE;
3405
3406 dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_enc,
3407 offsetof(struct caam_ctx,
3408 sh_desc_enc_dma),
3409 ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
3410 if (dma_mapping_error(ctx->jrdev, dma_addr)) {
3411 dev_err(ctx->jrdev, "unable to map key, shared descriptors\n");
3412 caam_jr_free(ctx->jrdev);
3413 return -ENOMEM;
3414 }
3415
3416 ctx->sh_desc_enc_dma = dma_addr;
3417 ctx->sh_desc_dec_dma = dma_addr + offsetof(struct caam_ctx,
3418 sh_desc_dec);
3419 ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key);
3420
3421 /* copy descriptor header template value */
3422 ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
3423 ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
3424
3425 return 0;
3426}
3427
3428static int caam_cra_init(struct crypto_skcipher *tfm)
3429{
3430 struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
3431 struct caam_skcipher_alg *caam_alg =
3432 container_of(alg, typeof(*caam_alg), skcipher);
3433
3434 return caam_init_common(crypto_skcipher_ctx(tfm), &caam_alg->caam,
3435 false);
3436}
3437
3438static int caam_aead_init(struct crypto_aead *tfm)
3439{
3440 struct aead_alg *alg = crypto_aead_alg(tfm);
3441 struct caam_aead_alg *caam_alg =
3442 container_of(alg, struct caam_aead_alg, aead);
3443 struct caam_ctx *ctx = crypto_aead_ctx(tfm);
3444
3445 return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp);
3446}
3447
3448static void caam_exit_common(struct caam_ctx *ctx)
3449{
3450 dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_enc_dma,
3451 offsetof(struct caam_ctx, sh_desc_enc_dma),
3452 ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
3453 caam_jr_free(ctx->jrdev);
3454}
3455
3456static void caam_cra_exit(struct crypto_skcipher *tfm)
3457{
3458 caam_exit_common(crypto_skcipher_ctx(tfm));
3459}
3460
3461static void caam_aead_exit(struct crypto_aead *tfm)
3462{
3463 caam_exit_common(crypto_aead_ctx(tfm));
3464}
3465
3466void caam_algapi_exit(void)
3467{
3468 int i;
3469
3470 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
3471 struct caam_aead_alg *t_alg = driver_aeads + i;
3472
3473 if (t_alg->registered)
3474 crypto_unregister_aead(&t_alg->aead);
3475 }
3476
3477 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
3478 struct caam_skcipher_alg *t_alg = driver_algs + i;
3479
3480 if (t_alg->registered)
3481 crypto_unregister_skcipher(&t_alg->skcipher);
3482 }
3483}
3484
3485static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg)
3486{
3487 struct skcipher_alg *alg = &t_alg->skcipher;
3488
3489 alg->base.cra_module = THIS_MODULE;
3490 alg->base.cra_priority = CAAM_CRA_PRIORITY;
3491 alg->base.cra_ctxsize = sizeof(struct caam_ctx);
3492 alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
3493
3494 alg->init = caam_cra_init;
3495 alg->exit = caam_cra_exit;
3496}
3497
3498static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
3499{
3500 struct aead_alg *alg = &t_alg->aead;
3501
3502 alg->base.cra_module = THIS_MODULE;
3503 alg->base.cra_priority = CAAM_CRA_PRIORITY;
3504 alg->base.cra_ctxsize = sizeof(struct caam_ctx);
3505 alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
3506
3507 alg->init = caam_aead_init;
3508 alg->exit = caam_aead_exit;
3509}
3510
3511int caam_algapi_init(struct device *ctrldev)
3512{
3513 struct caam_drv_private *priv = dev_get_drvdata(ctrldev);
3514 int i = 0, err = 0;
3515 u32 aes_vid, aes_inst, des_inst, md_vid, md_inst, ccha_inst, ptha_inst;
3516 unsigned int md_limit = SHA512_DIGEST_SIZE;
3517 bool registered = false, gcm_support;
3518
3519 /*
3520 * Register crypto algorithms the device supports.
3521 * First, detect presence and attributes of DES, AES, and MD blocks.
3522 */
3523 if (priv->era < 10) {
3524 u32 cha_vid, cha_inst, aes_rn;
3525
3526 cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
3527 aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
3528 md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3529
3530 cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
3531 des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
3532 CHA_ID_LS_DES_SHIFT;
3533 aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
3534 md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3535 ccha_inst = 0;
3536 ptha_inst = 0;
3537
3538 aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &
3539 CHA_ID_LS_AES_MASK;
3540 gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8);
3541 } else {
3542 u32 aesa, mdha;
3543
3544 aesa = rd_reg32(&priv->ctrl->vreg.aesa);
3545 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
3546
3547 aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3548 md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3549
3550 des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
3551 aes_inst = aesa & CHA_VER_NUM_MASK;
3552 md_inst = mdha & CHA_VER_NUM_MASK;
3553 ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK;
3554 ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK;
3555
3556 gcm_support = aesa & CHA_VER_MISC_AES_GCM;
3557 }
3558
3559 /* If MD is present, limit digest size based on LP256 */
3560 if (md_inst && md_vid == CHA_VER_VID_MD_LP256)
3561 md_limit = SHA256_DIGEST_SIZE;
3562
3563 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
3564 struct caam_skcipher_alg *t_alg = driver_algs + i;
3565 u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
3566
3567 /* Skip DES algorithms if not supported by device */
3568 if (!des_inst &&
3569 ((alg_sel == OP_ALG_ALGSEL_3DES) ||
3570 (alg_sel == OP_ALG_ALGSEL_DES)))
3571 continue;
3572
3573 /* Skip AES algorithms if not supported by device */
3574 if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
3575 continue;
3576
3577 /*
3578 * Check support for AES modes not available
3579 * on LP devices.
3580 */
3581 if (aes_vid == CHA_VER_VID_AES_LP &&
3582 (t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==
3583 OP_ALG_AAI_XTS)
3584 continue;
3585
3586 caam_skcipher_alg_init(t_alg);
3587
3588 err = crypto_register_skcipher(&t_alg->skcipher);
3589 if (err) {
3590 pr_warn("%s alg registration failed\n",
3591 t_alg->skcipher.base.cra_driver_name);
3592 continue;
3593 }
3594
3595 t_alg->registered = true;
3596 registered = true;
3597 }
3598
3599 for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
3600 struct caam_aead_alg *t_alg = driver_aeads + i;
3601 u32 c1_alg_sel = t_alg->caam.class1_alg_type &
3602 OP_ALG_ALGSEL_MASK;
3603 u32 c2_alg_sel = t_alg->caam.class2_alg_type &
3604 OP_ALG_ALGSEL_MASK;
3605 u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
3606
3607 /* Skip DES algorithms if not supported by device */
3608 if (!des_inst &&
3609 ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
3610 (c1_alg_sel == OP_ALG_ALGSEL_DES)))
3611 continue;
3612
3613 /* Skip AES algorithms if not supported by device */
3614 if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
3615 continue;
3616
3617 /* Skip CHACHA20 algorithms if not supported by device */
3618 if (c1_alg_sel == OP_ALG_ALGSEL_CHACHA20 && !ccha_inst)
3619 continue;
3620
3621 /* Skip POLY1305 algorithms if not supported by device */
3622 if (c2_alg_sel == OP_ALG_ALGSEL_POLY1305 && !ptha_inst)
3623 continue;
3624
3625 /* Skip GCM algorithms if not supported by device */
3626 if (c1_alg_sel == OP_ALG_ALGSEL_AES &&
3627 alg_aai == OP_ALG_AAI_GCM && !gcm_support)
3628 continue;
3629
3630 /*
3631 * Skip algorithms requiring message digests
3632 * if MD or MD size is not supported by device.
3633 */
3634 if (is_mdha(c2_alg_sel) &&
3635 (!md_inst || t_alg->aead.maxauthsize > md_limit))
3636 continue;
3637
3638 caam_aead_alg_init(t_alg);
3639
3640 err = crypto_register_aead(&t_alg->aead);
3641 if (err) {
3642 pr_warn("%s alg registration failed\n",
3643 t_alg->aead.base.cra_driver_name);
3644 continue;
3645 }
3646
3647 t_alg->registered = true;
3648 registered = true;
3649 }
3650
3651 if (registered)
3652 pr_info("caam algorithms registered in /proc/crypto\n");
3653
3654 return err;
3655}