| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ |
| 3 | |
| 4 | #ifndef __CC_CRYS_KERNEL_H__ |
| 5 | #define __CC_CRYS_KERNEL_H__ |
| 6 | |
| 7 | // -------------------------------------- |
| 8 | // BLOCK: DSCRPTR |
| 9 | // -------------------------------------- |
| 10 | #define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL |
| 11 | #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL |
| 12 | #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL |
| 13 | #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL |
| 14 | #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL |
| 15 | #define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL |
| 16 | #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL |
| 17 | #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL |
| 18 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL |
| 19 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL |
| 20 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL |
| 21 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL |
| 22 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL |
| 23 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL |
| 24 | #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL |
| 25 | #define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL |
| 26 | #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL |
| 27 | #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL |
| 28 | #define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL |
| 29 | #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL |
| 30 | #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL |
| 31 | #define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL |
| 32 | #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL |
| 33 | #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL |
| 34 | #define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL |
| 35 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL |
| 36 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL |
| 37 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL |
| 38 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL |
| 39 | #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL |
| 40 | #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL |
| 41 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL |
| 42 | #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL |
| 43 | #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL |
| 44 | #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL |
| 45 | #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL |
| 46 | #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL |
| 47 | #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL |
| 48 | #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL |
| 49 | #define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL |
| 50 | #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL |
| 51 | #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL |
| 52 | #define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL |
| 53 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL |
| 54 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL |
| 55 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL |
| 56 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL |
| 57 | #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL |
| 58 | #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL |
| 59 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL |
| 60 | #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL |
| 61 | #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL |
| 62 | #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL |
| 63 | #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL |
| 64 | #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL |
| 65 | #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL |
| 66 | #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL |
| 67 | #define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL |
| 68 | #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL |
| 69 | #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL |
| 70 | #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL |
| 71 | #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL |
| 72 | #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL |
| 73 | #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL |
| 74 | #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL |
| 75 | #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL |
| 76 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL |
| 77 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL |
| 78 | #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL |
| 79 | #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL |
| 80 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL |
| 81 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL |
| 82 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL |
| 83 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL |
| 84 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL |
| 85 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL |
| 86 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL |
| 87 | #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL |
| 88 | #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL |
| 89 | #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL |
| 90 | #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL |
| 91 | #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL |
| 92 | #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL |
| 93 | #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL |
| 94 | #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL |
| 95 | #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL |
| 96 | #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL |
| 97 | #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL |
| 98 | #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL |
| 99 | #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL |
| 100 | #define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL |
| 101 | #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL |
| 102 | #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL |
| 103 | #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL |
| 104 | #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL |
| 105 | #define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL |
| 106 | #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL |
| 107 | #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL |
| 108 | #define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL |
| 109 | #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL |
| 110 | #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL |
| 111 | // -------------------------------------- |
| 112 | // BLOCK: AXI_P |
| 113 | // -------------------------------------- |
| 114 | #define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL |
| 115 | #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL |
| 116 | #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL |
| 117 | #define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL |
| 118 | #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL |
| 119 | #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL |
| 120 | #define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL |
| 121 | #define CC_AXIM_MON_COMP8_REG_OFFSET 0xBA0UL |
| 122 | #define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL |
| 123 | #define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL |
| 124 | #define CC_AXIM_MON_ERR_REG_OFFSET 0xBC4UL |
| 125 | #define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL |
| 126 | #define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL |
| 127 | #define CC_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL |
| 128 | #define CC_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL |
| 129 | #define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL |
| 130 | #define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL |
| 131 | #define CC_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL |
| 132 | #define CC_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL |
| 133 | #define CC_AXIM_CFG_REG_OFFSET 0xBE8UL |
| 134 | #define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL |
| 135 | #define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL |
| 136 | #define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL |
| 137 | #define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL |
| 138 | #define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL |
| 139 | #define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL |
| 140 | #define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL |
| 141 | #define CC_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL |
| 142 | #define CC_AXIM_ACE_CONST_REG_OFFSET 0xBECUL |
| 143 | #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL |
| 144 | #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL |
| 145 | #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL |
| 146 | #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL |
| 147 | #define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL |
| 148 | #define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL |
| 149 | #define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL |
| 150 | #define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL |
| 151 | #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL |
| 152 | #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL |
| 153 | #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL |
| 154 | #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL |
| 155 | #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL |
| 156 | #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL |
| 157 | #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL |
| 158 | #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL |
| 159 | #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL |
| 160 | #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL |
| 161 | #define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL |
| 162 | #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL |
| 163 | #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL |
| 164 | #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL |
| 165 | #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL |
| 166 | #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL |
| 167 | #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL |
| 168 | #endif // __CC_CRYS_KERNEL_H__ |