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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / firmware / qcom_scm.h
blob: 4ab1a242261283807d07d2c2f77e4de42fb949d7 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7#define QCOM_SCM_SVC_BOOT 0x1
8#define QCOM_SCM_BOOT_ADDR 0x1
9#define QCOM_SCM_SET_DLOAD_MODE 0x10
10#define QCOM_SCM_BOOT_ADDR_MC 0x11
11#define QCOM_SCM_SET_REMOTE_STATE 0xa
12extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
13extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
14
15#define QCOM_SCM_FLAG_HLOS 0x01
16#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
17#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
18extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
19 const cpumask_t *cpus);
20extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
21
22#define QCOM_SCM_CMD_TERMINATE_PC 0x2
23#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
24#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
25extern void __qcom_scm_cpu_power_down(u32 flags);
26
27#define QCOM_SCM_SVC_IO 0x5
28#define QCOM_SCM_IO_READ 0x1
29#define QCOM_SCM_IO_WRITE 0x2
30extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
31extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
32
33#define QCOM_SCM_SVC_INFO 0x6
34#define QCOM_IS_CALL_AVAIL_CMD 0x1
35extern bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
36 u32 cmd_id);
37
38#define QCOM_SCM_SVC_HDCP 0x11
39#define QCOM_SCM_CMD_HDCP 0x01
40extern int __qcom_scm_hdcp_req(struct device *dev,
41 struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
42
43extern void __qcom_scm_init(void);
44
45#define QCOM_SCM_SVC_PIL 0x2
46#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
47#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
48#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
49#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
50#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
51#define QCOM_SCM_PAS_MSS_RESET 0xa
52extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
53extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
54 dma_addr_t metadata_phys);
55extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
56 phys_addr_t addr, phys_addr_t size);
57extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
58extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
59extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
60
61#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
62#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
63#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
64extern int __qcom_scm_ice_invalidate_key(struct device *dev, u32 index);
65extern int __qcom_scm_ice_set_key(struct device *dev, u32 index,
66 dma_addr_t key_phys,
67 u32 key_size, enum qcom_scm_ice_cipher cipher,
68 u32 data_unit_size);
69
70/* common error codes */
71#define QCOM_SCM_V2_EBUSY -12
72#define QCOM_SCM_ENOMEM -5
73#define QCOM_SCM_EOPNOTSUPP -4
74#define QCOM_SCM_EINVAL_ADDR -3
75#define QCOM_SCM_EINVAL_ARG -2
76#define QCOM_SCM_ERROR -1
77#define QCOM_SCM_INTERRUPTED 1
78
79static inline int qcom_scm_remap_error(int err)
80{
81 switch (err) {
82 case QCOM_SCM_ERROR:
83 return -EIO;
84 case QCOM_SCM_EINVAL_ADDR:
85 case QCOM_SCM_EINVAL_ARG:
86 return -EINVAL;
87 case QCOM_SCM_EOPNOTSUPP:
88 return -EOPNOTSUPP;
89 case QCOM_SCM_ENOMEM:
90 return -ENOMEM;
91 case QCOM_SCM_V2_EBUSY:
92 return -EBUSY;
93 }
94 return -EINVAL;
95}
96
97#define QCOM_SCM_SVC_MP 0xc
98#define QCOM_SCM_RESTORE_SEC_CFG 2
99extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
100 u32 spare);
101#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3
102#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4
103#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
104#define QCOM_SCM_CONFIG_ERRATA1 0x3
105#define QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL 0x2
106extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
107 size_t *size);
108extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
109 u32 size, u32 spare);
110extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
111 bool enable);
112#define QCOM_MEM_PROT_ASSIGN_ID 0x16
113extern int __qcom_scm_assign_mem(struct device *dev,
114 phys_addr_t mem_region, size_t mem_sz,
115 phys_addr_t src, size_t src_sz,
116 phys_addr_t dest, size_t dest_sz);
117
118#endif