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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / gpu / drm / bridge / analogix-anx78xx.c
blob: 56df07cdab68f6dab2fdee567af959d2e119b89f [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright(c) 2016, Analogix Semiconductor.
4 *
5 * Based on anx7808 driver obtained from chromeos with copyright:
6 * Copyright(c) 2013, Google Inc.
7 */
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/gpio/consumer.h>
11#include <linux/i2c.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/types.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_crtc.h>
23#include <drm/drm_dp_helper.h>
24#include <drm/drm_edid.h>
25#include <drm/drm_print.h>
26#include <drm/drm_probe_helper.h>
27
28#include "analogix-anx78xx.h"
29
30#define I2C_NUM_ADDRESSES 5
31#define I2C_IDX_TX_P0 0
32#define I2C_IDX_TX_P1 1
33#define I2C_IDX_TX_P2 2
34#define I2C_IDX_RX_P0 3
35#define I2C_IDX_RX_P1 4
36
37#define XTAL_CLK 270 /* 27M */
38#define AUX_CH_BUFFER_SIZE 16
39#define AUX_WAIT_TIMEOUT_MS 15
40
41static const u8 anx78xx_i2c_addresses[] = {
42 [I2C_IDX_TX_P0] = TX_P0,
43 [I2C_IDX_TX_P1] = TX_P1,
44 [I2C_IDX_TX_P2] = TX_P2,
45 [I2C_IDX_RX_P0] = RX_P0,
46 [I2C_IDX_RX_P1] = RX_P1,
47};
48
49struct anx78xx_platform_data {
50 struct regulator *dvdd10;
51 struct gpio_desc *gpiod_hpd;
52 struct gpio_desc *gpiod_pd;
53 struct gpio_desc *gpiod_reset;
54
55 int hpd_irq;
56 int intp_irq;
57};
58
59struct anx78xx {
60 struct drm_dp_aux aux;
61 struct drm_bridge bridge;
62 struct i2c_client *client;
63 struct edid *edid;
64 struct drm_connector connector;
65 struct drm_dp_link link;
66 struct anx78xx_platform_data pdata;
67 struct mutex lock;
68
69 /*
70 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
71 * RX_P0 and RX_P1.
72 */
73 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
74 struct regmap *map[I2C_NUM_ADDRESSES];
75
76 u16 chipid;
77 u8 dpcd[DP_RECEIVER_CAP_SIZE];
78
79 bool powered;
80};
81
82static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
83{
84 return container_of(c, struct anx78xx, connector);
85}
86
87static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
88{
89 return container_of(bridge, struct anx78xx, bridge);
90}
91
92static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
93{
94 return regmap_update_bits(map, reg, mask, mask);
95}
96
97static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
98{
99 return regmap_update_bits(map, reg, mask, 0);
100}
101
102static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
103{
104 unsigned int value;
105 int err;
106
107 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
108 &value);
109 if (err < 0)
110 return false;
111
112 return (value & SP_AUX_EN) == 0;
113}
114
115static int anx78xx_aux_wait(struct anx78xx *anx78xx)
116{
117 unsigned long timeout;
118 unsigned int status;
119 int err;
120
121 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
122
123 while (!anx78xx_aux_op_finished(anx78xx)) {
124 if (time_after(jiffies, timeout)) {
125 if (!anx78xx_aux_op_finished(anx78xx)) {
126 DRM_ERROR("Timed out waiting AUX to finish\n");
127 return -ETIMEDOUT;
128 }
129
130 break;
131 }
132
133 usleep_range(1000, 2000);
134 }
135
136 /* Read the AUX channel access status */
137 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
138 &status);
139 if (err < 0) {
140 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
141 return err;
142 }
143
144 if (status & SP_AUX_STATUS) {
145 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
146 status);
147 return -ETIMEDOUT;
148 }
149
150 return 0;
151}
152
153static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
154{
155 int err;
156
157 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
158 addr & 0xff);
159 if (err)
160 return err;
161
162 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
163 (addr & 0xff00) >> 8);
164 if (err)
165 return err;
166
167 /*
168 * DP AUX CH Address Register #2, only update bits[3:0]
169 * [7:4] RESERVED
170 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
171 */
172 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
173 SP_AUX_ADDR_19_16_REG,
174 SP_AUX_ADDR_19_16_MASK,
175 (addr & 0xf0000) >> 16);
176
177 if (err)
178 return err;
179
180 return 0;
181}
182
183static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
184 struct drm_dp_aux_msg *msg)
185{
186 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
187 u8 ctrl1 = msg->request;
188 u8 ctrl2 = SP_AUX_EN;
189 u8 *buffer = msg->buffer;
190 int err;
191
192 /* The DP AUX transmit and receive buffer has 16 bytes. */
193 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
194 return -E2BIG;
195
196 /* Zero-sized messages specify address-only transactions. */
197 if (msg->size < 1)
198 ctrl2 |= SP_ADDR_ONLY;
199 else /* For non-zero-sized set the length field. */
200 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
201
202 if ((msg->request & DP_AUX_I2C_READ) == 0) {
203 /* When WRITE | MOT write values to data buffer */
204 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
205 SP_DP_BUF_DATA0_REG, buffer,
206 msg->size);
207 if (err)
208 return err;
209 }
210
211 /* Write address and request */
212 err = anx78xx_aux_address(anx78xx, msg->address);
213 if (err)
214 return err;
215
216 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
217 ctrl1);
218 if (err)
219 return err;
220
221 /* Start transaction */
222 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
223 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
224 SP_AUX_EN, ctrl2);
225 if (err)
226 return err;
227
228 err = anx78xx_aux_wait(anx78xx);
229 if (err)
230 return err;
231
232 msg->reply = DP_AUX_I2C_REPLY_ACK;
233
234 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
235 /* Read values from data buffer */
236 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
237 SP_DP_BUF_DATA0_REG, buffer,
238 msg->size);
239 if (err)
240 return err;
241 }
242
243 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
244 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
245 if (err)
246 return err;
247
248 return msg->size;
249}
250
251static int anx78xx_set_hpd(struct anx78xx *anx78xx)
252{
253 int err;
254
255 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
256 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
257 if (err)
258 return err;
259
260 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
261 SP_HPD_OUT);
262 if (err)
263 return err;
264
265 return 0;
266}
267
268static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
269{
270 int err;
271
272 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
273 SP_HPD_OUT);
274 if (err)
275 return err;
276
277 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
278 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
279 if (err)
280 return err;
281
282 return 0;
283}
284
285static const struct reg_sequence tmds_phy_initialization[] = {
286 { SP_TMDS_CTRL_BASE + 1, 0x90 },
287 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
288 { SP_TMDS_CTRL_BASE + 6, 0x92 },
289 { SP_TMDS_CTRL_BASE + 7, 0x80 },
290 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
291 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
292 { SP_TMDS_CTRL_BASE + 23, 0x18 },
293};
294
295static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
296{
297 int err;
298
299 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
300 SP_AUD_MUTE | SP_VID_MUTE);
301 if (err)
302 return err;
303
304 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
305 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
306 SP_DIGITAL_CKDT_EN);
307 if (err)
308 return err;
309
310 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
311 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
312 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
313 if (err)
314 return err;
315
316 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
317 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
318 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
319 if (err)
320 return err;
321
322 /* Sync detect change, GP set mute */
323 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
324 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
325 BIT(6));
326 if (err)
327 return err;
328
329 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
330 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
331 SP_AEC_EN21);
332 if (err)
333 return err;
334
335 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
336 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
337 if (err)
338 return err;
339
340 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
341 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
342 if (err)
343 return err;
344
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
346 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
347 if (err)
348 return err;
349
350 /* Enable DDC stretch */
351 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
352 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
353 if (err)
354 return err;
355
356 /* TMDS phy initialization */
357 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
358 tmds_phy_initialization,
359 ARRAY_SIZE(tmds_phy_initialization));
360 if (err)
361 return err;
362
363 err = anx78xx_clear_hpd(anx78xx);
364 if (err)
365 return err;
366
367 return 0;
368}
369
370static const u8 dp_tx_output_precise_tune_bits[20] = {
371 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
372 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
373 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
374};
375
376static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
377{
378 int err;
379
380 /*
381 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
382 * register.
383 */
384 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
385 0x02);
386 if (err)
387 return err;
388
389 /*
390 * Write DP TX output emphasis precise tune bits.
391 */
392 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
393 SP_DP_TX_LT_CTRL0_REG,
394 dp_tx_output_precise_tune_bits,
395 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
396
397 if (err)
398 return err;
399
400 return 0;
401}
402
403static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
404{
405 unsigned int value;
406 int err;
407
408 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
409 SP_ANALOG_DEBUG2_REG,
410 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
411 SP_XTAL_FRQ_27M);
412 if (err)
413 return err;
414
415 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
416 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
417 if (err)
418 return err;
419
420 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
421 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
422 if (err)
423 return err;
424
425 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
426 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
427 if (err)
428 return err;
429
430 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
431 SP_I2C_GEN_10US_TIMER1_REG,
432 (XTAL_CLK & 0xff00) >> 8);
433 if (err)
434 return err;
435
436 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
437 XTAL_CLK / 10 - 1);
438 if (err)
439 return err;
440
441 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
442 SP_HDMI_US_TIMER_CTRL_REG,
443 &value);
444 if (err)
445 return err;
446
447 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
448 SP_HDMI_US_TIMER_CTRL_REG,
449 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
450 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
451 if (err)
452 return err;
453
454 return 0;
455}
456
457static const struct reg_sequence otp_key_protect[] = {
458 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
459 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
460 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
461};
462
463static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
464{
465 int err;
466
467 /* Set terminal resistor to 50 ohm */
468 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
469 0x30);
470 if (err)
471 return err;
472
473 /* Enable aux double diff output */
474 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
475 SP_DP_AUX_CH_CTRL2_REG, 0x08);
476 if (err)
477 return err;
478
479 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
480 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
481 SP_AUTO_START);
482 if (err)
483 return err;
484
485 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
486 otp_key_protect,
487 ARRAY_SIZE(otp_key_protect));
488 if (err)
489 return err;
490
491 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
492 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
493 if (err)
494 return err;
495
496 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
497 SP_VID_VRES_TH);
498 if (err)
499 return err;
500
501 /*
502 * DP HDCP auto authentication wait timer (when downstream starts to
503 * auth, DP side will wait for this period then do auth automatically)
504 */
505 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
506 0x00);
507 if (err)
508 return err;
509
510 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
511 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
512 if (err)
513 return err;
514
515 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
516 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
517 if (err)
518 return err;
519
520 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
521 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
522 if (err)
523 return err;
524
525 err = anx78xx_xtal_clk_sel(anx78xx);
526 if (err)
527 return err;
528
529 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
530 SP_DEFER_CTRL_EN | 0x0c);
531 if (err)
532 return err;
533
534 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
535 SP_DP_POLLING_CTRL_REG,
536 SP_AUTO_POLLING_DISABLE);
537 if (err)
538 return err;
539
540 /*
541 * Short the link integrity check timer to speed up bstatus
542 * polling for HDCP CTS item 1A-07
543 */
544 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
545 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
546 if (err)
547 return err;
548
549 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
550 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
551 if (err)
552 return err;
553
554 /* Power down the main link by default */
555 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
556 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
557 if (err)
558 return err;
559
560 err = anx78xx_link_phy_initialization(anx78xx);
561 if (err)
562 return err;
563
564 /* Gen m_clk with downspreading */
565 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
566 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
567 if (err)
568 return err;
569
570 return 0;
571}
572
573static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
574{
575 int err;
576
577 /*
578 * BIT0: INT pin assertion polarity: 1 = assert high
579 * BIT1: INT pin output type: 0 = push/pull
580 */
581 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
582 if (err)
583 return err;
584
585 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
586 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
587 if (err)
588 return err;
589
590 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
591 SP_TRAINING_FINISH);
592 if (err)
593 return err;
594
595 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
596 SP_CKDT_CHG | SP_SCDT_CHG);
597 if (err)
598 return err;
599
600 return 0;
601}
602
603static void anx78xx_poweron(struct anx78xx *anx78xx)
604{
605 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
606 int err;
607
608 if (WARN_ON(anx78xx->powered))
609 return;
610
611 if (pdata->dvdd10) {
612 err = regulator_enable(pdata->dvdd10);
613 if (err) {
614 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
615 err);
616 return;
617 }
618
619 usleep_range(1000, 2000);
620 }
621
622 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
623 usleep_range(1000, 2000);
624
625 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
626 usleep_range(1000, 2000);
627
628 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
629
630 /* Power on registers module */
631 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
632 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
633 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
634 SP_REGISTER_PD | SP_TOTAL_PD);
635
636 anx78xx->powered = true;
637}
638
639static void anx78xx_poweroff(struct anx78xx *anx78xx)
640{
641 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
642 int err;
643
644 if (WARN_ON(!anx78xx->powered))
645 return;
646
647 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
648 usleep_range(1000, 2000);
649
650 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
651 usleep_range(1000, 2000);
652
653 if (pdata->dvdd10) {
654 err = regulator_disable(pdata->dvdd10);
655 if (err) {
656 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
657 err);
658 return;
659 }
660
661 usleep_range(1000, 2000);
662 }
663
664 anx78xx->powered = false;
665}
666
667static int anx78xx_start(struct anx78xx *anx78xx)
668{
669 int err;
670
671 /* Power on all modules */
672 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
673 SP_POWERDOWN_CTRL_REG,
674 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
675 SP_LINK_PD);
676
677 err = anx78xx_enable_interrupts(anx78xx);
678 if (err) {
679 DRM_ERROR("Failed to enable interrupts: %d\n", err);
680 goto err_poweroff;
681 }
682
683 err = anx78xx_rx_initialization(anx78xx);
684 if (err) {
685 DRM_ERROR("Failed receiver initialization: %d\n", err);
686 goto err_poweroff;
687 }
688
689 err = anx78xx_tx_initialization(anx78xx);
690 if (err) {
691 DRM_ERROR("Failed transmitter initialization: %d\n", err);
692 goto err_poweroff;
693 }
694
695 /*
696 * This delay seems to help keep the hardware in a good state. Without
697 * it, there are times where it fails silently.
698 */
699 usleep_range(10000, 15000);
700
701 return 0;
702
703err_poweroff:
704 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
705 anx78xx_poweroff(anx78xx);
706
707 return err;
708}
709
710static int anx78xx_init_pdata(struct anx78xx *anx78xx)
711{
712 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
713 struct device *dev = &anx78xx->client->dev;
714
715 /* 1.0V digital core power regulator */
716 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
717 if (IS_ERR(pdata->dvdd10)) {
718 if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
719 DRM_ERROR("DVDD10 regulator not found\n");
720
721 return PTR_ERR(pdata->dvdd10);
722 }
723
724 /* GPIO for HPD */
725 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
726 if (IS_ERR(pdata->gpiod_hpd))
727 return PTR_ERR(pdata->gpiod_hpd);
728
729 /* GPIO for chip power down */
730 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
731 if (IS_ERR(pdata->gpiod_pd))
732 return PTR_ERR(pdata->gpiod_pd);
733
734 /* GPIO for chip reset */
735 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
736
737 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
738}
739
740static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
741{
742 u8 dp_bw, value;
743 int err;
744
745 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
746 0x0);
747 if (err)
748 return err;
749
750 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
751 SP_POWERDOWN_CTRL_REG,
752 SP_TOTAL_PD);
753 if (err)
754 return err;
755
756 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
757 if (err < 0)
758 return err;
759
760 switch (dp_bw) {
761 case DP_LINK_BW_1_62:
762 case DP_LINK_BW_2_7:
763 case DP_LINK_BW_5_4:
764 break;
765
766 default:
767 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
768 return -EINVAL;
769 }
770
771 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
772 SP_VIDEO_MUTE);
773 if (err)
774 return err;
775
776 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
777 SP_VID_CTRL1_REG, SP_VIDEO_EN);
778 if (err)
779 return err;
780
781 /* Get DPCD info */
782 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
783 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
784 if (err < 0) {
785 DRM_ERROR("Failed to read DPCD: %d\n", err);
786 return err;
787 }
788
789 /* Clear channel x SERDES power down */
790 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
791 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
792 if (err)
793 return err;
794
795 /* Check link capabilities */
796 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
797 if (err < 0) {
798 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
799 return err;
800 }
801
802 /* Power up the sink */
803 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
804 if (err < 0) {
805 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
806 return err;
807 }
808
809 /* Possibly enable downspread on the sink */
810 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
811 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
812 if (err)
813 return err;
814
815 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
816 DRM_DEBUG("Enable downspread on the sink\n");
817 /* 4000PPM */
818 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
819 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
820 if (err)
821 return err;
822
823 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
824 DP_SPREAD_AMP_0_5);
825 if (err < 0)
826 return err;
827 } else {
828 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
829 if (err < 0)
830 return err;
831 }
832
833 /* Set the lane count and the link rate on the sink */
834 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
835 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
836 SP_DP_SYSTEM_CTRL_BASE + 4,
837 SP_ENHANCED_MODE);
838 else
839 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
840 SP_DP_SYSTEM_CTRL_BASE + 4,
841 SP_ENHANCED_MODE);
842 if (err)
843 return err;
844
845 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
846 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
847 SP_DP_MAIN_LINK_BW_SET_REG, value);
848 if (err)
849 return err;
850
851 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
852 if (err < 0) {
853 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
854 return err;
855 }
856
857 /* Start training on the source */
858 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
859 SP_LT_EN);
860 if (err)
861 return err;
862
863 return 0;
864}
865
866static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
867{
868 int err;
869
870 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
871 SP_VIDEO_MUTE);
872 if (err)
873 return err;
874
875 /* Enable DP output */
876 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
877 SP_VIDEO_EN);
878 if (err)
879 return err;
880
881 return 0;
882}
883
884static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
885 struct hdmi_avi_infoframe *frame)
886{
887 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
888 int err;
889
890 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
891 if (err < 0) {
892 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
893 return err;
894 }
895
896 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
897 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
898 if (err)
899 return err;
900
901 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
902 SP_INFOFRAME_AVI_DB1_REG, buffer,
903 frame->length);
904 if (err)
905 return err;
906
907 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
908 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
909 if (err)
910 return err;
911
912 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
913 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
914 if (err)
915 return err;
916
917 return 0;
918}
919
920static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
921{
922 u8 value;
923 int err;
924
925 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
926 if (err < 0) {
927 DRM_ERROR("Get sink count failed %d\n", err);
928 return err;
929 }
930
931 if (!DP_GET_SINK_COUNT(value)) {
932 DRM_ERROR("Downstream disconnected\n");
933 return -EIO;
934 }
935
936 return 0;
937}
938
939static int anx78xx_get_modes(struct drm_connector *connector)
940{
941 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
942 int err, num_modes = 0;
943
944 if (WARN_ON(!anx78xx->powered))
945 return 0;
946
947 if (anx78xx->edid)
948 return drm_add_edid_modes(connector, anx78xx->edid);
949
950 mutex_lock(&anx78xx->lock);
951
952 err = anx78xx_get_downstream_info(anx78xx);
953 if (err) {
954 DRM_ERROR("Failed to get downstream info: %d\n", err);
955 goto unlock;
956 }
957
958 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
959 if (!anx78xx->edid) {
960 DRM_ERROR("Failed to read EDID\n");
961 goto unlock;
962 }
963
964 err = drm_connector_update_edid_property(connector,
965 anx78xx->edid);
966 if (err) {
967 DRM_ERROR("Failed to update EDID property: %d\n", err);
968 goto unlock;
969 }
970
971 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
972
973unlock:
974 mutex_unlock(&anx78xx->lock);
975
976 return num_modes;
977}
978
979static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
980 .get_modes = anx78xx_get_modes,
981};
982
983static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
984 bool force)
985{
986 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
987
988 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
989 return connector_status_disconnected;
990
991 return connector_status_connected;
992}
993
994static const struct drm_connector_funcs anx78xx_connector_funcs = {
995 .fill_modes = drm_helper_probe_single_connector_modes,
996 .detect = anx78xx_detect,
997 .destroy = drm_connector_cleanup,
998 .reset = drm_atomic_helper_connector_reset,
999 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1000 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1001};
1002
1003static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1004{
1005 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1006 int err;
1007
1008 if (!bridge->encoder) {
1009 DRM_ERROR("Parent encoder object not found");
1010 return -ENODEV;
1011 }
1012
1013 /* Register aux channel */
1014 anx78xx->aux.name = "DP-AUX";
1015 anx78xx->aux.dev = &anx78xx->client->dev;
1016 anx78xx->aux.transfer = anx78xx_aux_transfer;
1017
1018 err = drm_dp_aux_register(&anx78xx->aux);
1019 if (err < 0) {
1020 DRM_ERROR("Failed to register aux channel: %d\n", err);
1021 return err;
1022 }
1023
1024 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1025 &anx78xx_connector_funcs,
1026 DRM_MODE_CONNECTOR_DisplayPort);
1027 if (err) {
1028 DRM_ERROR("Failed to initialize connector: %d\n", err);
1029 return err;
1030 }
1031
1032 drm_connector_helper_add(&anx78xx->connector,
1033 &anx78xx_connector_helper_funcs);
1034
1035 err = drm_connector_register(&anx78xx->connector);
1036 if (err) {
1037 DRM_ERROR("Failed to register connector: %d\n", err);
1038 return err;
1039 }
1040
1041 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1042
1043 err = drm_connector_attach_encoder(&anx78xx->connector,
1044 bridge->encoder);
1045 if (err) {
1046 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1047 return err;
1048 }
1049
1050 return 0;
1051}
1052
1053static enum drm_mode_status
1054anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1055 const struct drm_display_mode *mode)
1056{
1057 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1058 return MODE_NO_INTERLACE;
1059
1060 /* Max 1200p at 5.4 Ghz, one lane */
1061 if (mode->clock > 154000)
1062 return MODE_CLOCK_HIGH;
1063
1064 return MODE_OK;
1065}
1066
1067static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1068{
1069 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1070
1071 /* Power off all modules except configuration registers access */
1072 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1073 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1074}
1075
1076static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1077 const struct drm_display_mode *mode,
1078 const struct drm_display_mode *adjusted_mode)
1079{
1080 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1081 struct hdmi_avi_infoframe frame;
1082 int err;
1083
1084 if (WARN_ON(!anx78xx->powered))
1085 return;
1086
1087 mutex_lock(&anx78xx->lock);
1088
1089 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1090 &anx78xx->connector,
1091 adjusted_mode);
1092 if (err) {
1093 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1094 goto unlock;
1095 }
1096
1097 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1098 if (err)
1099 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1100
1101unlock:
1102 mutex_unlock(&anx78xx->lock);
1103}
1104
1105static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1106{
1107 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1108 int err;
1109
1110 err = anx78xx_start(anx78xx);
1111 if (err) {
1112 DRM_ERROR("Failed to initialize: %d\n", err);
1113 return;
1114 }
1115
1116 err = anx78xx_set_hpd(anx78xx);
1117 if (err)
1118 DRM_ERROR("Failed to set HPD: %d\n", err);
1119}
1120
1121static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1122 .attach = anx78xx_bridge_attach,
1123 .mode_valid = anx78xx_bridge_mode_valid,
1124 .disable = anx78xx_bridge_disable,
1125 .mode_set = anx78xx_bridge_mode_set,
1126 .enable = anx78xx_bridge_enable,
1127};
1128
1129static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1130{
1131 struct anx78xx *anx78xx = data;
1132 int err;
1133
1134 if (anx78xx->powered)
1135 return IRQ_HANDLED;
1136
1137 mutex_lock(&anx78xx->lock);
1138
1139 /* Cable is pulled, power on the chip */
1140 anx78xx_poweron(anx78xx);
1141
1142 err = anx78xx_enable_interrupts(anx78xx);
1143 if (err)
1144 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1145
1146 mutex_unlock(&anx78xx->lock);
1147
1148 return IRQ_HANDLED;
1149}
1150
1151static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1152{
1153 int err;
1154
1155 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1156
1157 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1158 irq);
1159 if (err)
1160 return err;
1161
1162 if (irq & SP_TRAINING_FINISH) {
1163 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1164 err = anx78xx_config_dp_output(anx78xx);
1165 }
1166
1167 return err;
1168}
1169
1170static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1171{
1172 bool event = false;
1173 int err;
1174
1175 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1176
1177 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1178 SP_COMMON_INT_STATUS4_REG, irq);
1179 if (err) {
1180 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1181 return event;
1182 }
1183
1184 if (irq & SP_HPD_LOST) {
1185 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1186 event = true;
1187 anx78xx_poweroff(anx78xx);
1188 /* Free cached EDID */
1189 kfree(anx78xx->edid);
1190 anx78xx->edid = NULL;
1191 } else if (irq & SP_HPD_PLUG) {
1192 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1193 event = true;
1194 }
1195
1196 return event;
1197}
1198
1199static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1200{
1201 unsigned int value;
1202 int err;
1203
1204 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1205
1206 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1207 irq);
1208 if (err) {
1209 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1210 return;
1211 }
1212
1213 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1214 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1215
1216 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1217 SP_SYSTEM_STATUS_REG, &value);
1218 if (err) {
1219 DRM_ERROR("Read system status reg failed: %d\n", err);
1220 return;
1221 }
1222
1223 if (!(value & SP_TMDS_CLOCK_DET)) {
1224 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1225 return;
1226 }
1227
1228 if (!(value & SP_TMDS_DE_DET)) {
1229 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1230 return;
1231 }
1232
1233 err = anx78xx_dp_link_training(anx78xx);
1234 if (err)
1235 DRM_ERROR("Failed to start link training: %d\n", err);
1236 }
1237}
1238
1239static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1240{
1241 struct anx78xx *anx78xx = data;
1242 bool event = false;
1243 unsigned int irq;
1244 int err;
1245
1246 mutex_lock(&anx78xx->lock);
1247
1248 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1249 &irq);
1250 if (err) {
1251 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1252 goto unlock;
1253 }
1254
1255 if (irq)
1256 anx78xx_handle_dp_int_1(anx78xx, irq);
1257
1258 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1259 SP_COMMON_INT_STATUS4_REG, &irq);
1260 if (err) {
1261 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1262 err);
1263 goto unlock;
1264 }
1265
1266 if (irq)
1267 event = anx78xx_handle_common_int_4(anx78xx, irq);
1268
1269 /* Make sure we are still powered after handle HPD events */
1270 if (!anx78xx->powered)
1271 goto unlock;
1272
1273 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1274 &irq);
1275 if (err) {
1276 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1277 goto unlock;
1278 }
1279
1280 if (irq)
1281 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1282
1283unlock:
1284 mutex_unlock(&anx78xx->lock);
1285
1286 if (event)
1287 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1288
1289 return IRQ_HANDLED;
1290}
1291
1292static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1293{
1294 unsigned int i;
1295
1296 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1297 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1298}
1299
1300static const struct regmap_config anx78xx_regmap_config = {
1301 .reg_bits = 8,
1302 .val_bits = 8,
1303};
1304
1305static const u16 anx78xx_chipid_list[] = {
1306 0x7812,
1307 0x7814,
1308 0x7818,
1309};
1310
1311static int anx78xx_i2c_probe(struct i2c_client *client,
1312 const struct i2c_device_id *id)
1313{
1314 struct anx78xx *anx78xx;
1315 struct anx78xx_platform_data *pdata;
1316 unsigned int i, idl, idh, version;
1317 bool found = false;
1318 int err;
1319
1320 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1321 if (!anx78xx)
1322 return -ENOMEM;
1323
1324 pdata = &anx78xx->pdata;
1325
1326 mutex_init(&anx78xx->lock);
1327
1328#if IS_ENABLED(CONFIG_OF)
1329 anx78xx->bridge.of_node = client->dev.of_node;
1330#endif
1331
1332 anx78xx->client = client;
1333 i2c_set_clientdata(client, anx78xx);
1334
1335 err = anx78xx_init_pdata(anx78xx);
1336 if (err) {
1337 if (err != -EPROBE_DEFER)
1338 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1339
1340 return err;
1341 }
1342
1343 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1344 if (pdata->hpd_irq < 0) {
1345 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1346 return -ENODEV;
1347 }
1348
1349 pdata->intp_irq = client->irq;
1350 if (!pdata->intp_irq) {
1351 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1352 return -ENODEV;
1353 }
1354
1355 /* Map slave addresses of ANX7814 */
1356 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1357 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1358 anx78xx_i2c_addresses[i] >> 1);
1359 if (!anx78xx->i2c_dummy[i]) {
1360 err = -ENOMEM;
1361 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1362 anx78xx_i2c_addresses[i]);
1363 goto err_unregister_i2c;
1364 }
1365
1366 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1367 &anx78xx_regmap_config);
1368 if (IS_ERR(anx78xx->map[i])) {
1369 err = PTR_ERR(anx78xx->map[i]);
1370 DRM_ERROR("Failed regmap initialization %02x\n",
1371 anx78xx_i2c_addresses[i]);
1372 goto err_unregister_i2c;
1373 }
1374 }
1375
1376 /* Look for supported chip ID */
1377 anx78xx_poweron(anx78xx);
1378
1379 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1380 &idl);
1381 if (err)
1382 goto err_poweroff;
1383
1384 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1385 &idh);
1386 if (err)
1387 goto err_poweroff;
1388
1389 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1390
1391 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1392 &version);
1393 if (err)
1394 goto err_poweroff;
1395
1396 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1397 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1398 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1399 anx78xx->chipid, version);
1400 found = true;
1401 break;
1402 }
1403 }
1404
1405 if (!found) {
1406 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1407 anx78xx->chipid, version);
1408 err = -ENODEV;
1409 goto err_poweroff;
1410 }
1411
1412 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1413 anx78xx_hpd_threaded_handler,
1414 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1415 "anx78xx-hpd", anx78xx);
1416 if (err) {
1417 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1418 err);
1419 goto err_poweroff;
1420 }
1421
1422 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1423 anx78xx_intp_threaded_handler,
1424 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1425 "anx78xx-intp", anx78xx);
1426 if (err) {
1427 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1428 goto err_poweroff;
1429 }
1430
1431 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1432
1433 drm_bridge_add(&anx78xx->bridge);
1434
1435 /* If cable is pulled out, just poweroff and wait for HPD event */
1436 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1437 anx78xx_poweroff(anx78xx);
1438
1439 return 0;
1440
1441err_poweroff:
1442 anx78xx_poweroff(anx78xx);
1443
1444err_unregister_i2c:
1445 unregister_i2c_dummy_clients(anx78xx);
1446 return err;
1447}
1448
1449static int anx78xx_i2c_remove(struct i2c_client *client)
1450{
1451 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1452
1453 drm_bridge_remove(&anx78xx->bridge);
1454
1455 unregister_i2c_dummy_clients(anx78xx);
1456
1457 kfree(anx78xx->edid);
1458
1459 return 0;
1460}
1461
1462static const struct i2c_device_id anx78xx_id[] = {
1463 { "anx7814", 0 },
1464 { /* sentinel */ }
1465};
1466MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1467
1468#if IS_ENABLED(CONFIG_OF)
1469static const struct of_device_id anx78xx_match_table[] = {
1470 { .compatible = "analogix,anx7814", },
1471 { /* sentinel */ },
1472};
1473MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1474#endif
1475
1476static struct i2c_driver anx78xx_driver = {
1477 .driver = {
1478 .name = "anx7814",
1479 .of_match_table = of_match_ptr(anx78xx_match_table),
1480 },
1481 .probe = anx78xx_i2c_probe,
1482 .remove = anx78xx_i2c_remove,
1483 .id_table = anx78xx_id,
1484};
1485module_i2c_driver(anx78xx_driver);
1486
1487MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1488MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1489MODULE_LICENSE("GPL v2");