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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / gpu / drm / i915 / gvt / handlers.c
blob: 45ffccdcd50e780dba2ddd7020e8dbbd68c51dd5 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
40#include "gvt.h"
41#include "i915_pvinfo.h"
42
43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51{
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58 else if (IS_BROXTON(gvt->dev_priv))
59 return D_BXT;
60 else if (IS_COFFEELAKE(gvt->dev_priv))
61 return D_CFL;
62
63 return 0;
64}
65
66bool intel_gvt_match_device(struct intel_gvt *gvt,
67 unsigned long device)
68{
69 return intel_gvt_get_device_type(gvt) & device;
70}
71
72static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
73 void *p_data, unsigned int bytes)
74{
75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
76}
77
78static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
79 void *p_data, unsigned int bytes)
80{
81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
82}
83
84static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
85 unsigned int offset)
86{
87 struct intel_gvt_mmio_info *e;
88
89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
90 if (e->offset == offset)
91 return e;
92 }
93 return NULL;
94}
95
96static int new_mmio_info(struct intel_gvt *gvt,
97 u32 offset, u8 flags, u32 size,
98 u32 addr_mask, u32 ro_mask, u32 device,
99 gvt_mmio_func read, gvt_mmio_func write)
100{
101 struct intel_gvt_mmio_info *info, *p;
102 u32 start, end, i;
103
104 if (!intel_gvt_match_device(gvt, device))
105 return 0;
106
107 if (WARN_ON(!IS_ALIGNED(offset, 4)))
108 return -EINVAL;
109
110 start = offset;
111 end = offset + size;
112
113 for (i = start; i < end; i += 4) {
114 info = kzalloc(sizeof(*info), GFP_KERNEL);
115 if (!info)
116 return -ENOMEM;
117
118 info->offset = i;
119 p = find_mmio_info(gvt, info->offset);
120 if (p) {
121 WARN(1, "dup mmio definition offset %x\n",
122 info->offset);
123 kfree(info);
124
125 /* We return -EEXIST here to make GVT-g load fail.
126 * So duplicated MMIO can be found as soon as
127 * possible.
128 */
129 return -EEXIST;
130 }
131
132 info->ro_mask = ro_mask;
133 info->device = device;
134 info->read = read ? read : intel_vgpu_default_mmio_read;
135 info->write = write ? write : intel_vgpu_default_mmio_write;
136 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
137 INIT_HLIST_NODE(&info->node);
138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
139 gvt->mmio.num_tracked_mmio++;
140 }
141 return 0;
142}
143
144/**
145 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
146 * @gvt: a GVT device
147 * @offset: register offset
148 *
149 * Returns:
150 * Ring ID on success, negative error code if failed.
151 */
152int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
153 unsigned int offset)
154{
155 enum intel_engine_id id;
156 struct intel_engine_cs *engine;
157
158 offset &= ~GENMASK(11, 0);
159 for_each_engine(engine, gvt->dev_priv, id) {
160 if (engine->mmio_base == offset)
161 return id;
162 }
163 return -ENODEV;
164}
165
166#define offset_to_fence_num(offset) \
167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168
169#define fence_num_to_offset(num) \
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
171
172
173void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
174{
175 switch (reason) {
176 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
177 pr_err("Detected your guest driver doesn't support GVT-g.\n");
178 break;
179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
180 pr_err("Graphics resource is not enough for the guest\n");
181 break;
182 case GVT_FAILSAFE_GUEST_ERR:
183 pr_err("GVT Internal error for the guest\n");
184 break;
185 default:
186 break;
187 }
188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
189 vgpu->failsafe = true;
190}
191
192static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
193 unsigned int fence_num, void *p_data, unsigned int bytes)
194{
195 unsigned int max_fence = vgpu_fence_sz(vgpu);
196
197 if (fence_num >= max_fence) {
198 gvt_vgpu_err("access oob fence reg %d/%d\n",
199 fence_num, max_fence);
200
201 /* When guest access oob fence regs without access
202 * pv_info first, we treat guest not supporting GVT,
203 * and we will let vgpu enter failsafe mode.
204 */
205 if (!vgpu->pv_notified)
206 enter_failsafe_mode(vgpu,
207 GVT_FAILSAFE_UNSUPPORTED_GUEST);
208
209 memset(p_data, 0, bytes);
210 return -EINVAL;
211 }
212 return 0;
213}
214
215static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
216 unsigned int offset, void *p_data, unsigned int bytes)
217{
218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
219
220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
223 else if (!ips)
224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
225 else {
226 /* All engines must be enabled together for vGPU,
227 * since we don't know which engine the ppgtt will
228 * bind to when shadowing.
229 */
230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
231 ips);
232 return -EINVAL;
233 }
234 }
235
236 write_vreg(vgpu, offset, p_data, bytes);
237 return 0;
238}
239
240static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
241 void *p_data, unsigned int bytes)
242{
243 int ret;
244
245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
246 p_data, bytes);
247 if (ret)
248 return ret;
249 read_vreg(vgpu, off, p_data, bytes);
250 return 0;
251}
252
253static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
254 void *p_data, unsigned int bytes)
255{
256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
257 unsigned int fence_num = offset_to_fence_num(off);
258 int ret;
259
260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
261 if (ret)
262 return ret;
263 write_vreg(vgpu, off, p_data, bytes);
264
265 mmio_hw_access_pre(dev_priv);
266 intel_vgpu_write_fence(vgpu, fence_num,
267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
268 mmio_hw_access_post(dev_priv);
269 return 0;
270}
271
272#define CALC_MODE_MASK_REG(old, new) \
273 (((new) & GENMASK(31, 16)) \
274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
275 | ((new) & ((new) >> 16))))
276
277static int mul_force_wake_write(struct intel_vgpu *vgpu,
278 unsigned int offset, void *p_data, unsigned int bytes)
279{
280 u32 old, new;
281 u32 ack_reg_offset;
282
283 old = vgpu_vreg(vgpu, offset);
284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
285
286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) {
287 switch (offset) {
288 case FORCEWAKE_RENDER_GEN9_REG:
289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
290 break;
291 case FORCEWAKE_BLITTER_GEN9_REG:
292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
293 break;
294 case FORCEWAKE_MEDIA_GEN9_REG:
295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
296 break;
297 default:
298 /*should not hit here*/
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
300 return -EINVAL;
301 }
302 } else {
303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
304 }
305
306 vgpu_vreg(vgpu, offset) = new;
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
308 return 0;
309}
310
311static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
312 void *p_data, unsigned int bytes)
313{
314 intel_engine_mask_t engine_mask = 0;
315 u32 data;
316
317 write_vreg(vgpu, offset, p_data, bytes);
318 data = vgpu_vreg(vgpu, offset);
319
320 if (data & GEN6_GRDOM_FULL) {
321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
322 engine_mask = ALL_ENGINES;
323 } else {
324 if (data & GEN6_GRDOM_RENDER) {
325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
326 engine_mask |= BIT(RCS0);
327 }
328 if (data & GEN6_GRDOM_MEDIA) {
329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
330 engine_mask |= BIT(VCS0);
331 }
332 if (data & GEN6_GRDOM_BLT) {
333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
334 engine_mask |= BIT(BCS0);
335 }
336 if (data & GEN6_GRDOM_VECS) {
337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
338 engine_mask |= BIT(VECS0);
339 }
340 if (data & GEN8_GRDOM_MEDIA2) {
341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
342 engine_mask |= BIT(VCS1);
343 }
344 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
345 }
346
347 /* vgpu_lock already hold by emulate mmio r/w */
348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
349
350 /* sw will wait for the device to ack the reset request */
351 vgpu_vreg(vgpu, offset) = 0;
352
353 return 0;
354}
355
356static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
357 void *p_data, unsigned int bytes)
358{
359 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
360}
361
362static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
363 void *p_data, unsigned int bytes)
364{
365 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
366}
367
368static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
369 unsigned int offset, void *p_data, unsigned int bytes)
370{
371 write_vreg(vgpu, offset, p_data, bytes);
372
373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
378
379 } else
380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
381 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
382 | PP_CYCLE_DELAY_ACTIVE);
383 return 0;
384}
385
386static int transconf_mmio_write(struct intel_vgpu *vgpu,
387 unsigned int offset, void *p_data, unsigned int bytes)
388{
389 write_vreg(vgpu, offset, p_data, bytes);
390
391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
393 else
394 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
395 return 0;
396}
397
398static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
399 void *p_data, unsigned int bytes)
400{
401 write_vreg(vgpu, offset, p_data, bytes);
402
403 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
404 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
405 else
406 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
407
408 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
409 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
410 else
411 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
412
413 return 0;
414}
415
416static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
417 void *p_data, unsigned int bytes)
418{
419 switch (offset) {
420 case 0xe651c:
421 case 0xe661c:
422 case 0xe671c:
423 case 0xe681c:
424 vgpu_vreg(vgpu, offset) = 1 << 17;
425 break;
426 case 0xe6c04:
427 vgpu_vreg(vgpu, offset) = 0x3;
428 break;
429 case 0xe6e1c:
430 vgpu_vreg(vgpu, offset) = 0x2f << 16;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 read_vreg(vgpu, offset, p_data, bytes);
437 return 0;
438}
439
440static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
441 void *p_data, unsigned int bytes)
442{
443 u32 data;
444
445 write_vreg(vgpu, offset, p_data, bytes);
446 data = vgpu_vreg(vgpu, offset);
447
448 if (data & PIPECONF_ENABLE)
449 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
450 else
451 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
452 /* vgpu_lock already hold by emulate mmio r/w */
453 mutex_unlock(&vgpu->vgpu_lock);
454 intel_gvt_check_vblank_emulation(vgpu->gvt);
455 mutex_lock(&vgpu->vgpu_lock);
456 return 0;
457}
458
459/* ascendingly sorted */
460static i915_reg_t force_nonpriv_white_list[] = {
461 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
462 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
463 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
464 _MMIO(0x2690),
465 _MMIO(0x2694),
466 _MMIO(0x2698),
467 _MMIO(0x2754),
468 _MMIO(0x28a0),
469 _MMIO(0x4de0),
470 _MMIO(0x4de4),
471 _MMIO(0x4dfc),
472 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
473 _MMIO(0x7014),
474 HDC_CHICKEN0,//_MMIO(0x7300)
475 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
476 _MMIO(0x7700),
477 _MMIO(0x7704),
478 _MMIO(0x7708),
479 _MMIO(0x770c),
480 _MMIO(0x83a8),
481 _MMIO(0xb110),
482 GEN8_L3SQCREG4,//_MMIO(0xb118)
483 _MMIO(0xe100),
484 _MMIO(0xe18c),
485 _MMIO(0xe48c),
486 _MMIO(0xe5f4),
487};
488
489/* a simple bsearch */
490static inline bool in_whitelist(unsigned int reg)
491{
492 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
493 i915_reg_t *array = force_nonpriv_white_list;
494
495 while (left < right) {
496 int mid = (left + right)/2;
497
498 if (reg > array[mid].reg)
499 left = mid + 1;
500 else if (reg < array[mid].reg)
501 right = mid;
502 else
503 return true;
504 }
505 return false;
506}
507
508static int force_nonpriv_write(struct intel_vgpu *vgpu,
509 unsigned int offset, void *p_data, unsigned int bytes)
510{
511 u32 reg_nonpriv = *(u32 *)p_data;
512 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
513 u32 ring_base;
514 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
515 int ret = -EINVAL;
516
517 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
518 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
519 vgpu->id, ring_id, offset, bytes);
520 return ret;
521 }
522
523 ring_base = dev_priv->engine[ring_id]->mmio_base;
524
525 if (in_whitelist(reg_nonpriv) ||
526 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
527 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
528 bytes);
529 } else
530 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
531 vgpu->id, reg_nonpriv, offset);
532
533 return 0;
534}
535
536static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
537 void *p_data, unsigned int bytes)
538{
539 write_vreg(vgpu, offset, p_data, bytes);
540
541 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
542 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
543 } else {
544 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
545 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
546 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
547 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
548 }
549 return 0;
550}
551
552static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
553 unsigned int offset, void *p_data, unsigned int bytes)
554{
555 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
556 return 0;
557}
558
559#define FDI_LINK_TRAIN_PATTERN1 0
560#define FDI_LINK_TRAIN_PATTERN2 1
561
562static int fdi_auto_training_started(struct intel_vgpu *vgpu)
563{
564 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
565 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
566 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
567
568 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
569 (rx_ctl & FDI_RX_ENABLE) &&
570 (rx_ctl & FDI_AUTO_TRAINING) &&
571 (tx_ctl & DP_TP_CTL_ENABLE) &&
572 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
573 return 1;
574 else
575 return 0;
576}
577
578static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
579 enum pipe pipe, unsigned int train_pattern)
580{
581 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
582 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
583 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
584 unsigned int fdi_iir_check_bits;
585
586 fdi_rx_imr = FDI_RX_IMR(pipe);
587 fdi_tx_ctl = FDI_TX_CTL(pipe);
588 fdi_rx_ctl = FDI_RX_CTL(pipe);
589
590 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
591 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
592 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
593 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
594 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
595 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
596 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
597 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
598 } else {
599 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
600 return -EINVAL;
601 }
602
603 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
604 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
605
606 /* If imr bit has been masked */
607 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
608 return 0;
609
610 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
611 == fdi_tx_check_bits)
612 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
613 == fdi_rx_check_bits))
614 return 1;
615 else
616 return 0;
617}
618
619#define INVALID_INDEX (~0U)
620
621static unsigned int calc_index(unsigned int offset, unsigned int start,
622 unsigned int next, unsigned int end, i915_reg_t i915_end)
623{
624 unsigned int range = next - start;
625
626 if (!end)
627 end = i915_mmio_reg_offset(i915_end);
628 if (offset < start || offset > end)
629 return INVALID_INDEX;
630 offset -= start;
631 return offset / range;
632}
633
634#define FDI_RX_CTL_TO_PIPE(offset) \
635 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
636
637#define FDI_TX_CTL_TO_PIPE(offset) \
638 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
639
640#define FDI_RX_IMR_TO_PIPE(offset) \
641 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
642
643static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
644 unsigned int offset, void *p_data, unsigned int bytes)
645{
646 i915_reg_t fdi_rx_iir;
647 unsigned int index;
648 int ret;
649
650 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
651 index = FDI_RX_CTL_TO_PIPE(offset);
652 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
653 index = FDI_TX_CTL_TO_PIPE(offset);
654 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
655 index = FDI_RX_IMR_TO_PIPE(offset);
656 else {
657 gvt_vgpu_err("Unsupported registers %x\n", offset);
658 return -EINVAL;
659 }
660
661 write_vreg(vgpu, offset, p_data, bytes);
662
663 fdi_rx_iir = FDI_RX_IIR(index);
664
665 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
666 if (ret < 0)
667 return ret;
668 if (ret)
669 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
670
671 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
672 if (ret < 0)
673 return ret;
674 if (ret)
675 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
676
677 if (offset == _FDI_RXA_CTL)
678 if (fdi_auto_training_started(vgpu))
679 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
680 DP_TP_STATUS_AUTOTRAIN_DONE;
681 return 0;
682}
683
684#define DP_TP_CTL_TO_PORT(offset) \
685 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
686
687static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
688 void *p_data, unsigned int bytes)
689{
690 i915_reg_t status_reg;
691 unsigned int index;
692 u32 data;
693
694 write_vreg(vgpu, offset, p_data, bytes);
695
696 index = DP_TP_CTL_TO_PORT(offset);
697 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
698 if (data == 0x2) {
699 status_reg = DP_TP_STATUS(index);
700 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
701 }
702 return 0;
703}
704
705static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
706 unsigned int offset, void *p_data, unsigned int bytes)
707{
708 u32 reg_val;
709 u32 sticky_mask;
710
711 reg_val = *((u32 *)p_data);
712 sticky_mask = GENMASK(27, 26) | (1 << 24);
713
714 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
715 (vgpu_vreg(vgpu, offset) & sticky_mask);
716 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
717 return 0;
718}
719
720static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
721 unsigned int offset, void *p_data, unsigned int bytes)
722{
723 u32 data;
724
725 write_vreg(vgpu, offset, p_data, bytes);
726 data = vgpu_vreg(vgpu, offset);
727
728 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
729 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
730 return 0;
731}
732
733static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
734 unsigned int offset, void *p_data, unsigned int bytes)
735{
736 u32 data;
737
738 write_vreg(vgpu, offset, p_data, bytes);
739 data = vgpu_vreg(vgpu, offset);
740
741 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
742 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
743 else
744 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
745 return 0;
746}
747
748#define DSPSURF_TO_PIPE(offset) \
749 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
750
751static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
752 void *p_data, unsigned int bytes)
753{
754 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
755 u32 pipe = DSPSURF_TO_PIPE(offset);
756 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
757
758 write_vreg(vgpu, offset, p_data, bytes);
759 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
760
761 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
762
763 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
764 intel_vgpu_trigger_virtual_event(vgpu, event);
765 else
766 set_bit(event, vgpu->irq.flip_done_event[pipe]);
767
768 return 0;
769}
770
771#define SPRSURF_TO_PIPE(offset) \
772 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
773
774static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
775 void *p_data, unsigned int bytes)
776{
777 u32 pipe = SPRSURF_TO_PIPE(offset);
778 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
779
780 write_vreg(vgpu, offset, p_data, bytes);
781 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
782
783 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
784 intel_vgpu_trigger_virtual_event(vgpu, event);
785 else
786 set_bit(event, vgpu->irq.flip_done_event[pipe]);
787
788 return 0;
789}
790
791static int reg50080_mmio_write(struct intel_vgpu *vgpu,
792 unsigned int offset, void *p_data,
793 unsigned int bytes)
794{
795 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
796 enum pipe pipe = REG_50080_TO_PIPE(offset);
797 enum plane_id plane = REG_50080_TO_PLANE(offset);
798 int event = SKL_FLIP_EVENT(pipe, plane);
799
800 write_vreg(vgpu, offset, p_data, bytes);
801 if (plane == PLANE_PRIMARY) {
802 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
803 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
804 } else {
805 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
806 }
807
808 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
809 intel_vgpu_trigger_virtual_event(vgpu, event);
810 else
811 set_bit(event, vgpu->irq.flip_done_event[pipe]);
812
813 return 0;
814}
815
816static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
817 unsigned int reg)
818{
819 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
820 enum intel_gvt_event_type event;
821
822 if (reg == _DPA_AUX_CH_CTL)
823 event = AUX_CHANNEL_A;
824 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
825 event = AUX_CHANNEL_B;
826 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
827 event = AUX_CHANNEL_C;
828 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
829 event = AUX_CHANNEL_D;
830 else {
831 WARN_ON(true);
832 return -EINVAL;
833 }
834
835 intel_vgpu_trigger_virtual_event(vgpu, event);
836 return 0;
837}
838
839static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
840 unsigned int reg, int len, bool data_valid)
841{
842 /* mark transaction done */
843 value |= DP_AUX_CH_CTL_DONE;
844 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
845 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
846
847 if (data_valid)
848 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
849 else
850 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
851
852 /* message size */
853 value &= ~(0xf << 20);
854 value |= (len << 20);
855 vgpu_vreg(vgpu, reg) = value;
856
857 if (value & DP_AUX_CH_CTL_INTERRUPT)
858 return trigger_aux_channel_interrupt(vgpu, reg);
859 return 0;
860}
861
862static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
863 u8 t)
864{
865 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
866 /* training pattern 1 for CR */
867 /* set LANE0_CR_DONE, LANE1_CR_DONE */
868 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
869 /* set LANE2_CR_DONE, LANE3_CR_DONE */
870 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
871 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
872 DPCD_TRAINING_PATTERN_2) {
873 /* training pattern 2 for EQ */
874 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
875 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
876 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
877 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
878 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
879 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
880 /* set INTERLANE_ALIGN_DONE */
881 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
882 DPCD_INTERLANE_ALIGN_DONE;
883 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
884 DPCD_LINK_TRAINING_DISABLED) {
885 /* finish link training */
886 /* set sink status as synchronized */
887 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
888 }
889}
890
891#define _REG_HSW_DP_AUX_CH_CTL(dp) \
892 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
893
894#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
895
896#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
897
898#define dpy_is_valid_port(port) \
899 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
900
901static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
902 unsigned int offset, void *p_data, unsigned int bytes)
903{
904 struct intel_vgpu_display *display = &vgpu->display;
905 int msg, addr, ctrl, op, len;
906 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
907 struct intel_vgpu_dpcd_data *dpcd = NULL;
908 struct intel_vgpu_port *port = NULL;
909 u32 data;
910
911 if (!dpy_is_valid_port(port_index)) {
912 gvt_vgpu_err("Unsupported DP port access!\n");
913 return 0;
914 }
915
916 write_vreg(vgpu, offset, p_data, bytes);
917 data = vgpu_vreg(vgpu, offset);
918
919 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)
920 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
921 /* SKL DPB/C/D aux ctl register changed */
922 return 0;
923 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
924 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
925 /* write to the data registers */
926 return 0;
927 }
928
929 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
930 /* just want to clear the sticky bits */
931 vgpu_vreg(vgpu, offset) = 0;
932 return 0;
933 }
934
935 port = &display->ports[port_index];
936 dpcd = port->dpcd;
937
938 /* read out message from DATA1 register */
939 msg = vgpu_vreg(vgpu, offset + 4);
940 addr = (msg >> 8) & 0xffff;
941 ctrl = (msg >> 24) & 0xff;
942 len = msg & 0xff;
943 op = ctrl >> 4;
944
945 if (op == GVT_AUX_NATIVE_WRITE) {
946 int t;
947 u8 buf[16];
948
949 if ((addr + len + 1) >= DPCD_SIZE) {
950 /*
951 * Write request exceeds what we supported,
952 * DCPD spec: When a Source Device is writing a DPCD
953 * address not supported by the Sink Device, the Sink
954 * Device shall reply with AUX NACK and “M” equal to
955 * zero.
956 */
957
958 /* NAK the write */
959 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
960 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
961 return 0;
962 }
963
964 /*
965 * Write request format: Headr (command + address + size) occupies
966 * 4 bytes, followed by (len + 1) bytes of data. See details at
967 * intel_dp_aux_transfer().
968 */
969 if ((len + 1 + 4) > AUX_BURST_SIZE) {
970 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
971 return -EINVAL;
972 }
973
974 /* unpack data from vreg to buf */
975 for (t = 0; t < 4; t++) {
976 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
977
978 buf[t * 4] = (r >> 24) & 0xff;
979 buf[t * 4 + 1] = (r >> 16) & 0xff;
980 buf[t * 4 + 2] = (r >> 8) & 0xff;
981 buf[t * 4 + 3] = r & 0xff;
982 }
983
984 /* write to virtual DPCD */
985 if (dpcd && dpcd->data_valid) {
986 for (t = 0; t <= len; t++) {
987 int p = addr + t;
988
989 dpcd->data[p] = buf[t];
990 /* check for link training */
991 if (p == DPCD_TRAINING_PATTERN_SET)
992 dp_aux_ch_ctl_link_training(dpcd,
993 buf[t]);
994 }
995 }
996
997 /* ACK the write */
998 vgpu_vreg(vgpu, offset + 4) = 0;
999 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1000 dpcd && dpcd->data_valid);
1001 return 0;
1002 }
1003
1004 if (op == GVT_AUX_NATIVE_READ) {
1005 int idx, i, ret = 0;
1006
1007 if ((addr + len + 1) >= DPCD_SIZE) {
1008 /*
1009 * read request exceeds what we supported
1010 * DPCD spec: A Sink Device receiving a Native AUX CH
1011 * read request for an unsupported DPCD address must
1012 * reply with an AUX ACK and read data set equal to
1013 * zero instead of replying with AUX NACK.
1014 */
1015
1016 /* ACK the READ*/
1017 vgpu_vreg(vgpu, offset + 4) = 0;
1018 vgpu_vreg(vgpu, offset + 8) = 0;
1019 vgpu_vreg(vgpu, offset + 12) = 0;
1020 vgpu_vreg(vgpu, offset + 16) = 0;
1021 vgpu_vreg(vgpu, offset + 20) = 0;
1022
1023 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1024 true);
1025 return 0;
1026 }
1027
1028 for (idx = 1; idx <= 5; idx++) {
1029 /* clear the data registers */
1030 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1031 }
1032
1033 /*
1034 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1035 */
1036 if ((len + 2) > AUX_BURST_SIZE) {
1037 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1038 return -EINVAL;
1039 }
1040
1041 /* read from virtual DPCD to vreg */
1042 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1043 if (dpcd && dpcd->data_valid) {
1044 for (i = 1; i <= (len + 1); i++) {
1045 int t;
1046
1047 t = dpcd->data[addr + i - 1];
1048 t <<= (24 - 8 * (i % 4));
1049 ret |= t;
1050
1051 if ((i % 4 == 3) || (i == (len + 1))) {
1052 vgpu_vreg(vgpu, offset +
1053 (i / 4 + 1) * 4) = ret;
1054 ret = 0;
1055 }
1056 }
1057 }
1058 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1059 dpcd && dpcd->data_valid);
1060 return 0;
1061 }
1062
1063 /* i2c transaction starts */
1064 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1065
1066 if (data & DP_AUX_CH_CTL_INTERRUPT)
1067 trigger_aux_channel_interrupt(vgpu, offset);
1068 return 0;
1069}
1070
1071static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1072 void *p_data, unsigned int bytes)
1073{
1074 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1075 write_vreg(vgpu, offset, p_data, bytes);
1076 return 0;
1077}
1078
1079static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1080 void *p_data, unsigned int bytes)
1081{
1082 bool vga_disable;
1083
1084 write_vreg(vgpu, offset, p_data, bytes);
1085 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1086
1087 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1088 vga_disable ? "Disable" : "Enable");
1089 return 0;
1090}
1091
1092static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1093 unsigned int sbi_offset)
1094{
1095 struct intel_vgpu_display *display = &vgpu->display;
1096 int num = display->sbi.number;
1097 int i;
1098
1099 for (i = 0; i < num; ++i)
1100 if (display->sbi.registers[i].offset == sbi_offset)
1101 break;
1102
1103 if (i == num)
1104 return 0;
1105
1106 return display->sbi.registers[i].value;
1107}
1108
1109static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1110 unsigned int offset, u32 value)
1111{
1112 struct intel_vgpu_display *display = &vgpu->display;
1113 int num = display->sbi.number;
1114 int i;
1115
1116 for (i = 0; i < num; ++i) {
1117 if (display->sbi.registers[i].offset == offset)
1118 break;
1119 }
1120
1121 if (i == num) {
1122 if (num == SBI_REG_MAX) {
1123 gvt_vgpu_err("SBI caching meets maximum limits\n");
1124 return;
1125 }
1126 display->sbi.number++;
1127 }
1128
1129 display->sbi.registers[i].offset = offset;
1130 display->sbi.registers[i].value = value;
1131}
1132
1133static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1134 void *p_data, unsigned int bytes)
1135{
1136 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1137 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1138 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1139 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1140 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1141 sbi_offset);
1142 }
1143 read_vreg(vgpu, offset, p_data, bytes);
1144 return 0;
1145}
1146
1147static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1148 void *p_data, unsigned int bytes)
1149{
1150 u32 data;
1151
1152 write_vreg(vgpu, offset, p_data, bytes);
1153 data = vgpu_vreg(vgpu, offset);
1154
1155 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1156 data |= SBI_READY;
1157
1158 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1159 data |= SBI_RESPONSE_SUCCESS;
1160
1161 vgpu_vreg(vgpu, offset) = data;
1162
1163 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1164 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1165 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1166 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1167
1168 write_virtual_sbi_register(vgpu, sbi_offset,
1169 vgpu_vreg_t(vgpu, SBI_DATA));
1170 }
1171 return 0;
1172}
1173
1174#define _vgtif_reg(x) \
1175 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1176
1177static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1178 void *p_data, unsigned int bytes)
1179{
1180 bool invalid_read = false;
1181
1182 read_vreg(vgpu, offset, p_data, bytes);
1183
1184 switch (offset) {
1185 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1186 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1187 invalid_read = true;
1188 break;
1189 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1190 _vgtif_reg(avail_rs.fence_num):
1191 if (offset + bytes >
1192 _vgtif_reg(avail_rs.fence_num) + 4)
1193 invalid_read = true;
1194 break;
1195 case 0x78010: /* vgt_caps */
1196 case 0x7881c:
1197 break;
1198 default:
1199 invalid_read = true;
1200 break;
1201 }
1202 if (invalid_read)
1203 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1204 offset, bytes, *(u32 *)p_data);
1205 vgpu->pv_notified = true;
1206 return 0;
1207}
1208
1209static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1210{
1211 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1212 struct intel_vgpu_mm *mm;
1213 u64 *pdps;
1214
1215 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1216
1217 switch (notification) {
1218 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1219 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1220 /* fall through */
1221 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1222 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1223 return PTR_ERR_OR_ZERO(mm);
1224 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1225 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1226 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1227 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1228 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1229 case 1: /* Remove this in guest driver. */
1230 break;
1231 default:
1232 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1233 }
1234 return 0;
1235}
1236
1237static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1238{
1239 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1240 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1241 char *env[3] = {NULL, NULL, NULL};
1242 char vmid_str[20];
1243 char display_ready_str[20];
1244
1245 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1246 env[0] = display_ready_str;
1247
1248 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1249 env[1] = vmid_str;
1250
1251 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1252}
1253
1254static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1255 void *p_data, unsigned int bytes)
1256{
1257 u32 data = *(u32 *)p_data;
1258 bool invalid_write = false;
1259
1260 switch (offset) {
1261 case _vgtif_reg(display_ready):
1262 send_display_ready_uevent(vgpu, data ? 1 : 0);
1263 break;
1264 case _vgtif_reg(g2v_notify):
1265 handle_g2v_notification(vgpu, data);
1266 break;
1267 /* add xhot and yhot to handled list to avoid error log */
1268 case _vgtif_reg(cursor_x_hot):
1269 case _vgtif_reg(cursor_y_hot):
1270 case _vgtif_reg(pdp[0].lo):
1271 case _vgtif_reg(pdp[0].hi):
1272 case _vgtif_reg(pdp[1].lo):
1273 case _vgtif_reg(pdp[1].hi):
1274 case _vgtif_reg(pdp[2].lo):
1275 case _vgtif_reg(pdp[2].hi):
1276 case _vgtif_reg(pdp[3].lo):
1277 case _vgtif_reg(pdp[3].hi):
1278 case _vgtif_reg(execlist_context_descriptor_lo):
1279 case _vgtif_reg(execlist_context_descriptor_hi):
1280 break;
1281 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1282 invalid_write = true;
1283 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1284 break;
1285 default:
1286 invalid_write = true;
1287 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1288 offset, bytes, data);
1289 break;
1290 }
1291
1292 if (!invalid_write)
1293 write_vreg(vgpu, offset, p_data, bytes);
1294
1295 return 0;
1296}
1297
1298static int pf_write(struct intel_vgpu *vgpu,
1299 unsigned int offset, void *p_data, unsigned int bytes)
1300{
1301 u32 val = *(u32 *)p_data;
1302
1303 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1304 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1305 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1306 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1307 vgpu->id);
1308 return 0;
1309 }
1310
1311 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1312}
1313
1314static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1315 unsigned int offset, void *p_data, unsigned int bytes)
1316{
1317 write_vreg(vgpu, offset, p_data, bytes);
1318
1319 if (vgpu_vreg(vgpu, offset) &
1320 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1321 vgpu_vreg(vgpu, offset) |=
1322 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1323 else
1324 vgpu_vreg(vgpu, offset) &=
1325 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1326 return 0;
1327}
1328
1329static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1330 unsigned int offset, void *p_data, unsigned int bytes)
1331{
1332 write_vreg(vgpu, offset, p_data, bytes);
1333
1334 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1335 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1336 else
1337 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1338
1339 return 0;
1340}
1341
1342static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1343 unsigned int offset, void *p_data, unsigned int bytes)
1344{
1345 write_vreg(vgpu, offset, p_data, bytes);
1346
1347 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1348 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1349 return 0;
1350}
1351
1352static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1353 void *p_data, unsigned int bytes)
1354{
1355 u32 mode;
1356
1357 write_vreg(vgpu, offset, p_data, bytes);
1358 mode = vgpu_vreg(vgpu, offset);
1359
1360 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1361 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1362 vgpu->id);
1363 return 0;
1364 }
1365
1366 return 0;
1367}
1368
1369static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1370 void *p_data, unsigned int bytes)
1371{
1372 u32 trtte = *(u32 *)p_data;
1373
1374 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1375 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1376 vgpu->id);
1377 return -EINVAL;
1378 }
1379 write_vreg(vgpu, offset, p_data, bytes);
1380
1381 return 0;
1382}
1383
1384static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1385 void *p_data, unsigned int bytes)
1386{
1387 write_vreg(vgpu, offset, p_data, bytes);
1388 return 0;
1389}
1390
1391static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1392 void *p_data, unsigned int bytes)
1393{
1394 u32 v = 0;
1395
1396 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1397 v |= (1 << 0);
1398
1399 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1400 v |= (1 << 8);
1401
1402 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1403 v |= (1 << 16);
1404
1405 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1406 v |= (1 << 24);
1407
1408 vgpu_vreg(vgpu, offset) = v;
1409
1410 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1411}
1412
1413static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1414 void *p_data, unsigned int bytes)
1415{
1416 u32 value = *(u32 *)p_data;
1417 u32 cmd = value & 0xff;
1418 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1419
1420 switch (cmd) {
1421 case GEN9_PCODE_READ_MEM_LATENCY:
1422 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1423 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1424 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {
1425 /**
1426 * "Read memory latency" command on gen9.
1427 * Below memory latency values are read
1428 * from skylake platform.
1429 */
1430 if (!*data0)
1431 *data0 = 0x1e1a1100;
1432 else
1433 *data0 = 0x61514b3d;
1434 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
1435 /**
1436 * "Read memory latency" command on gen9.
1437 * Below memory latency values are read
1438 * from Broxton MRB.
1439 */
1440 if (!*data0)
1441 *data0 = 0x16080707;
1442 else
1443 *data0 = 0x16161616;
1444 }
1445 break;
1446 case SKL_PCODE_CDCLK_CONTROL:
1447 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1448 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1449 || IS_COFFEELAKE(vgpu->gvt->dev_priv))
1450 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1451 break;
1452 case GEN6_PCODE_READ_RC6VIDS:
1453 *data0 |= 0x1;
1454 break;
1455 }
1456
1457 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1458 vgpu->id, value, *data0);
1459 /**
1460 * PCODE_READY clear means ready for pcode read/write,
1461 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1462 * always emulate as pcode read/write success and ready for access
1463 * anytime, since we don't touch real physical registers here.
1464 */
1465 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1466 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1467}
1468
1469static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1470 void *p_data, unsigned int bytes)
1471{
1472 u32 value = *(u32 *)p_data;
1473 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1474
1475 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1476 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1477 offset, value);
1478 return -EINVAL;
1479 }
1480 /*
1481 * Need to emulate all the HWSP register write to ensure host can
1482 * update the VM CSB status correctly. Here listed registers can
1483 * support BDW, SKL or other platforms with same HWSP registers.
1484 */
1485 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1486 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1487 offset);
1488 return -EINVAL;
1489 }
1490 vgpu->hws_pga[ring_id] = value;
1491 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1492 vgpu->id, value, offset);
1493
1494 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1495}
1496
1497static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1498 unsigned int offset, void *p_data, unsigned int bytes)
1499{
1500 u32 v = *(u32 *)p_data;
1501
1502 if (IS_BROXTON(vgpu->gvt->dev_priv))
1503 v &= (1 << 31) | (1 << 29);
1504 else
1505 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1506 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1507 v |= (v >> 1);
1508
1509 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1510}
1511
1512static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1513 void *p_data, unsigned int bytes)
1514{
1515 u32 v = *(u32 *)p_data;
1516
1517 /* other bits are MBZ. */
1518 v &= (1 << 31) | (1 << 30);
1519 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1520
1521 vgpu_vreg(vgpu, offset) = v;
1522
1523 return 0;
1524}
1525
1526static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1527 unsigned int offset, void *p_data, unsigned int bytes)
1528{
1529 u32 v = *(u32 *)p_data;
1530
1531 if (v & BXT_DE_PLL_PLL_ENABLE)
1532 v |= BXT_DE_PLL_LOCK;
1533
1534 vgpu_vreg(vgpu, offset) = v;
1535
1536 return 0;
1537}
1538
1539static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1540 unsigned int offset, void *p_data, unsigned int bytes)
1541{
1542 u32 v = *(u32 *)p_data;
1543
1544 if (v & PORT_PLL_ENABLE)
1545 v |= PORT_PLL_LOCK;
1546
1547 vgpu_vreg(vgpu, offset) = v;
1548
1549 return 0;
1550}
1551
1552static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1553 unsigned int offset, void *p_data, unsigned int bytes)
1554{
1555 u32 v = *(u32 *)p_data;
1556 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1557
1558 switch (offset) {
1559 case _PHY_CTL_FAMILY_EDP:
1560 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1561 break;
1562 case _PHY_CTL_FAMILY_DDI:
1563 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1564 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1565 break;
1566 }
1567
1568 vgpu_vreg(vgpu, offset) = v;
1569
1570 return 0;
1571}
1572
1573static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1574 unsigned int offset, void *p_data, unsigned int bytes)
1575{
1576 u32 v = vgpu_vreg(vgpu, offset);
1577
1578 v &= ~UNIQUE_TRANGE_EN_METHOD;
1579
1580 vgpu_vreg(vgpu, offset) = v;
1581
1582 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1583}
1584
1585static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1586 unsigned int offset, void *p_data, unsigned int bytes)
1587{
1588 u32 v = *(u32 *)p_data;
1589
1590 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1591 vgpu_vreg(vgpu, offset - 0x600) = v;
1592 vgpu_vreg(vgpu, offset - 0x800) = v;
1593 } else {
1594 vgpu_vreg(vgpu, offset - 0x400) = v;
1595 vgpu_vreg(vgpu, offset - 0x600) = v;
1596 }
1597
1598 vgpu_vreg(vgpu, offset) = v;
1599
1600 return 0;
1601}
1602
1603static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1604 unsigned int offset, void *p_data, unsigned int bytes)
1605{
1606 u32 v = *(u32 *)p_data;
1607
1608 if (v & BIT(0)) {
1609 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1610 ~PHY_RESERVED;
1611 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1612 PHY_POWER_GOOD;
1613 }
1614
1615 if (v & BIT(1)) {
1616 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1617 ~PHY_RESERVED;
1618 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1619 PHY_POWER_GOOD;
1620 }
1621
1622
1623 vgpu_vreg(vgpu, offset) = v;
1624
1625 return 0;
1626}
1627
1628static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1629 unsigned int offset, void *p_data, unsigned int bytes)
1630{
1631 vgpu_vreg(vgpu, offset) = 0;
1632 return 0;
1633}
1634
1635/**
1636 * FixMe:
1637 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1638 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1639 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1640 * these MI_BATCH_BUFFER.
1641 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1642 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1643 * The performance is still expected to be low, will need further improvement.
1644 */
1645static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1646 void *p_data, unsigned int bytes)
1647{
1648 u64 pat =
1649 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1650 GEN8_PPAT(1, 0) |
1651 GEN8_PPAT(2, 0) |
1652 GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1653 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1654 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1655 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1656 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1657
1658 vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1659
1660 return 0;
1661}
1662
1663static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1664 unsigned int offset, void *p_data, unsigned int bytes)
1665{
1666 struct intel_gvt *gvt = vgpu->gvt;
1667 struct drm_i915_private *dev_priv = gvt->dev_priv;
1668 int ring_id;
1669 u32 ring_base;
1670
1671 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1672 /**
1673 * Read HW reg in following case
1674 * a. the offset isn't a ring mmio
1675 * b. the offset's ring is running on hw.
1676 * c. the offset is ring time stamp mmio
1677 */
1678 if (ring_id >= 0)
1679 ring_base = dev_priv->engine[ring_id]->mmio_base;
1680
1681 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1682 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1683 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1684 mmio_hw_access_pre(dev_priv);
1685 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1686 mmio_hw_access_post(dev_priv);
1687 }
1688
1689 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1690}
1691
1692static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1693 void *p_data, unsigned int bytes)
1694{
1695 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1696 struct intel_vgpu_execlist *execlist;
1697 u32 data = *(u32 *)p_data;
1698 int ret = 0;
1699
1700 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1701 return -EINVAL;
1702
1703 execlist = &vgpu->submission.execlist[ring_id];
1704
1705 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1706 if (execlist->elsp_dwords.index == 3) {
1707 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1708 if(ret)
1709 gvt_vgpu_err("fail submit workload on ring %d\n",
1710 ring_id);
1711 }
1712
1713 ++execlist->elsp_dwords.index;
1714 execlist->elsp_dwords.index &= 0x3;
1715 return ret;
1716}
1717
1718static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1719 void *p_data, unsigned int bytes)
1720{
1721 u32 data = *(u32 *)p_data;
1722 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1723 bool enable_execlist;
1724 int ret;
1725
1726 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
1727 if (IS_COFFEELAKE(vgpu->gvt->dev_priv))
1728 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
1729 write_vreg(vgpu, offset, p_data, bytes);
1730
1731 if (data & _MASKED_BIT_ENABLE(1)) {
1732 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1733 return 0;
1734 }
1735
1736 if (IS_COFFEELAKE(vgpu->gvt->dev_priv) &&
1737 data & _MASKED_BIT_ENABLE(2)) {
1738 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1739 return 0;
1740 }
1741
1742 /* when PPGTT mode enabled, we will check if guest has called
1743 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1744 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1745 */
1746 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1747 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1748 && !vgpu->pv_notified) {
1749 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1750 return 0;
1751 }
1752 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1753 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1754 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1755
1756 gvt_dbg_core("EXECLIST %s on ring %d\n",
1757 (enable_execlist ? "enabling" : "disabling"),
1758 ring_id);
1759
1760 if (!enable_execlist)
1761 return 0;
1762
1763 ret = intel_vgpu_select_submission_ops(vgpu,
1764 BIT(ring_id),
1765 INTEL_VGPU_EXECLIST_SUBMISSION);
1766 if (ret)
1767 return ret;
1768
1769 intel_vgpu_start_schedule(vgpu);
1770 }
1771 return 0;
1772}
1773
1774static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1775 unsigned int offset, void *p_data, unsigned int bytes)
1776{
1777 unsigned int id = 0;
1778
1779 write_vreg(vgpu, offset, p_data, bytes);
1780 vgpu_vreg(vgpu, offset) = 0;
1781
1782 switch (offset) {
1783 case 0x4260:
1784 id = RCS0;
1785 break;
1786 case 0x4264:
1787 id = VCS0;
1788 break;
1789 case 0x4268:
1790 id = VCS1;
1791 break;
1792 case 0x426c:
1793 id = BCS0;
1794 break;
1795 case 0x4270:
1796 id = VECS0;
1797 break;
1798 default:
1799 return -EINVAL;
1800 }
1801 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1802
1803 return 0;
1804}
1805
1806static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1807 unsigned int offset, void *p_data, unsigned int bytes)
1808{
1809 u32 data;
1810
1811 write_vreg(vgpu, offset, p_data, bytes);
1812 data = vgpu_vreg(vgpu, offset);
1813
1814 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1815 data |= RESET_CTL_READY_TO_RESET;
1816 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1817 data &= ~RESET_CTL_READY_TO_RESET;
1818
1819 vgpu_vreg(vgpu, offset) = data;
1820 return 0;
1821}
1822
1823static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
1824 unsigned int offset, void *p_data,
1825 unsigned int bytes)
1826{
1827 u32 data = *(u32 *)p_data;
1828
1829 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1830 write_vreg(vgpu, offset, p_data, bytes);
1831
1832 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1833 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1834
1835 return 0;
1836}
1837
1838#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1839 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1840 f, s, am, rm, d, r, w); \
1841 if (ret) \
1842 return ret; \
1843} while (0)
1844
1845#define MMIO_D(reg, d) \
1846 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1847
1848#define MMIO_DH(reg, d, r, w) \
1849 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1850
1851#define MMIO_DFH(reg, d, f, r, w) \
1852 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1853
1854#define MMIO_GM(reg, d, r, w) \
1855 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1856
1857#define MMIO_GM_RDR(reg, d, r, w) \
1858 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1859
1860#define MMIO_RO(reg, d, f, rm, r, w) \
1861 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1862
1863#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1864 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1865 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1866 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1867 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1868 if (HAS_ENGINE(dev_priv, VCS1)) \
1869 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1870} while (0)
1871
1872#define MMIO_RING_D(prefix, d) \
1873 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1874
1875#define MMIO_RING_DFH(prefix, d, f, r, w) \
1876 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1877
1878#define MMIO_RING_GM(prefix, d, r, w) \
1879 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1880
1881#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1882 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1883
1884#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1885 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1886
1887static int init_generic_mmio_info(struct intel_gvt *gvt)
1888{
1889 struct drm_i915_private *dev_priv = gvt->dev_priv;
1890 int ret;
1891
1892 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1893 intel_vgpu_reg_imr_handler);
1894
1895 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1896 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1897 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1898 MMIO_D(SDEISR, D_ALL);
1899
1900 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1901
1902 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1903 gamw_echo_dev_rw_ia_write);
1904
1905 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1906 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1907 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1908
1909#define RING_REG(base) _MMIO((base) + 0x28)
1910 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1911#undef RING_REG
1912
1913#define RING_REG(base) _MMIO((base) + 0x134)
1914 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1915#undef RING_REG
1916
1917#define RING_REG(base) _MMIO((base) + 0x6c)
1918 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1919#undef RING_REG
1920 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1921
1922 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1923 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
1924 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1925 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1926
1927 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1928 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1929 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1930 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1931 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1932
1933 /* RING MODE */
1934#define RING_REG(base) _MMIO((base) + 0x29c)
1935 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1936 ring_mode_mmio_write);
1937#undef RING_REG
1938
1939 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1940 NULL, NULL);
1941 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1942 NULL, NULL);
1943 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1944 mmio_read_from_hw, NULL);
1945 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1946 mmio_read_from_hw, NULL);
1947
1948 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1949 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1950 NULL, NULL);
1951 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1952 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1953 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1954
1955 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1956 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1957 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1958 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1959 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1960 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1961 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1962 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1963 NULL, NULL);
1964 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1965 NULL, NULL);
1966 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1967 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1968 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1969 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1970 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1971 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1972 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1973 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1974 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1975 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1976
1977 /* display */
1978 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1979 MMIO_D(_MMIO(0x602a0), D_ALL);
1980
1981 MMIO_D(_MMIO(0x65050), D_ALL);
1982 MMIO_D(_MMIO(0x650b4), D_ALL);
1983
1984 MMIO_D(_MMIO(0xc4040), D_ALL);
1985 MMIO_D(DERRMR, D_ALL);
1986
1987 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1988 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1989 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1990 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1991
1992 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1993 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1994 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1995 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1996
1997 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1998 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1999 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
2000 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
2001
2002 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
2003 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
2004 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
2005 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
2006
2007 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
2008 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
2009 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
2010 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
2011
2012 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2013 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2014 MMIO_D(CURCNTR(PIPE_C), D_ALL);
2015
2016 MMIO_D(CURPOS(PIPE_A), D_ALL);
2017 MMIO_D(CURPOS(PIPE_B), D_ALL);
2018 MMIO_D(CURPOS(PIPE_C), D_ALL);
2019
2020 MMIO_D(CURBASE(PIPE_A), D_ALL);
2021 MMIO_D(CURBASE(PIPE_B), D_ALL);
2022 MMIO_D(CURBASE(PIPE_C), D_ALL);
2023
2024 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2025 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2026 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
2027
2028 MMIO_D(_MMIO(0x700ac), D_ALL);
2029 MMIO_D(_MMIO(0x710ac), D_ALL);
2030 MMIO_D(_MMIO(0x720ac), D_ALL);
2031
2032 MMIO_D(_MMIO(0x70090), D_ALL);
2033 MMIO_D(_MMIO(0x70094), D_ALL);
2034 MMIO_D(_MMIO(0x70098), D_ALL);
2035 MMIO_D(_MMIO(0x7009c), D_ALL);
2036
2037 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2038 MMIO_D(DSPADDR(PIPE_A), D_ALL);
2039 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
2040 MMIO_D(DSPPOS(PIPE_A), D_ALL);
2041 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
2042 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2043 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
2044 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
2045 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2046 reg50080_mmio_write);
2047
2048 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2049 MMIO_D(DSPADDR(PIPE_B), D_ALL);
2050 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2051 MMIO_D(DSPPOS(PIPE_B), D_ALL);
2052 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
2053 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2054 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2055 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
2056 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2057 reg50080_mmio_write);
2058
2059 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2060 MMIO_D(DSPADDR(PIPE_C), D_ALL);
2061 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2062 MMIO_D(DSPPOS(PIPE_C), D_ALL);
2063 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
2064 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2065 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2066 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
2067 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2068 reg50080_mmio_write);
2069
2070 MMIO_D(SPRCTL(PIPE_A), D_ALL);
2071 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2072 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2073 MMIO_D(SPRPOS(PIPE_A), D_ALL);
2074 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2075 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2076 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
2077 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2078 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2079 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2080 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2081 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
2082 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2083 reg50080_mmio_write);
2084
2085 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2086 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2087 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2088 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2089 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2090 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2091 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
2092 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2093 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2094 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2095 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2096 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
2097 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2098 reg50080_mmio_write);
2099
2100 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2101 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2102 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2103 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2104 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2105 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2106 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
2107 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2108 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2109 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2110 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2111 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
2112 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2113 reg50080_mmio_write);
2114
2115 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2116 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2117 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2118 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2119 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2120 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2121 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2122 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2123 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2124
2125 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2126 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2127 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2128 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2129 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2130 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2131 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2132 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2133 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2134
2135 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2136 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2137 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2138 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2139 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2140 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2141 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2142 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2143 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2144
2145 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2146 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2147 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2148 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2149 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2150 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2151 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2152 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2153
2154 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2155 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2156 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2157 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2158 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2159 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2160 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2161 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2162
2163 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2164 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2165 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2166 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2167 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2168 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2169 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2170 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2171
2172 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2173 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2174 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2175 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2176 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2177 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2178 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2179 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2180
2181 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2182 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2183 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2184 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2185 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2186 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2187 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2188 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2189
2190 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2191 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2192 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2193 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2194 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2195
2196 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2197 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2198 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2199 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2200 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2201
2202 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2203 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2204 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2205 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2206 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2207
2208 MMIO_D(WM0_PIPEA_ILK, D_ALL);
2209 MMIO_D(WM0_PIPEB_ILK, D_ALL);
2210 MMIO_D(WM0_PIPEC_IVB, D_ALL);
2211 MMIO_D(WM1_LP_ILK, D_ALL);
2212 MMIO_D(WM2_LP_ILK, D_ALL);
2213 MMIO_D(WM3_LP_ILK, D_ALL);
2214 MMIO_D(WM1S_LP_ILK, D_ALL);
2215 MMIO_D(WM2S_LP_IVB, D_ALL);
2216 MMIO_D(WM3S_LP_IVB, D_ALL);
2217
2218 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2219 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2220 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2221 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2222
2223 MMIO_D(_MMIO(0x48268), D_ALL);
2224
2225 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2226 gmbus_mmio_write);
2227 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2228 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
2229
2230 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2231 dp_aux_ch_ctl_mmio_write);
2232 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2233 dp_aux_ch_ctl_mmio_write);
2234 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2235 dp_aux_ch_ctl_mmio_write);
2236
2237 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2238
2239 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2240 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2241
2242 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2243 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2244 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2245 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2246 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2247 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2248 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2249 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2250 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2251
2252 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2253 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2254 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2255 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2256 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2257 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2258 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2259
2260 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2261 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2262 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2263 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2264 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2265 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2266 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2267
2268 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2269 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2270 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2271 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2272 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2273 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2274 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2275 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2276
2277 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2278 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2279 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2280
2281 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2282 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2283 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2284
2285 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2286 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2287 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2288
2289 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2290 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2291 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2292
2293 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2294 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2295 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2296 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2297 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2298 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2299
2300 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2301 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2302 MMIO_D(PCH_PP_STATUS, D_ALL);
2303 MMIO_D(PCH_LVDS, D_ALL);
2304 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2305 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2306 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2307 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2308 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2309 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2310 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2311 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2312 MMIO_D(PCH_DPLL_SEL, D_ALL);
2313
2314 MMIO_D(_MMIO(0x61208), D_ALL);
2315 MMIO_D(_MMIO(0x6120c), D_ALL);
2316 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2317 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2318
2319 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2320 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2321 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2322 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2323 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2324 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2325
2326 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2327 PORTA_HOTPLUG_STATUS_MASK
2328 | PORTB_HOTPLUG_STATUS_MASK
2329 | PORTC_HOTPLUG_STATUS_MASK
2330 | PORTD_HOTPLUG_STATUS_MASK,
2331 NULL, NULL);
2332
2333 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2334 MMIO_D(FUSE_STRAP, D_ALL);
2335 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2336
2337 MMIO_D(DISP_ARB_CTL, D_ALL);
2338 MMIO_D(DISP_ARB_CTL2, D_ALL);
2339
2340 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2341 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2342 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2343
2344 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2345 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2346 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2347 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2348 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2349 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2350 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2351
2352 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2353 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2354 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2355 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2356 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2357 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2358 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2359
2360 MMIO_D(IPS_CTL, D_ALL);
2361
2362 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2363 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2364 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2365 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2366 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2367 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2368 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2369 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2370 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2371 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2372 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2373 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2374 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2375
2376 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2377 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2378 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2379 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2380 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2381 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2382 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2383 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2384 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2385 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2386 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2387 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2388 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2389
2390 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2391 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2392 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2393 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2394 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2395 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2396 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2397 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2398 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2399 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2400 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2401 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2402 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2403
2404 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2405 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2406 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2407
2408 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2409 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2410 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2411
2412 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2413 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2414 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2415
2416 MMIO_D(_MMIO(0x60110), D_ALL);
2417 MMIO_D(_MMIO(0x61110), D_ALL);
2418 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2419 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2420 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2421 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2422 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2423 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2424 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2425 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2426 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2427
2428 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2429 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2430 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2431 MMIO_D(SPLL_CTL, D_ALL);
2432 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2433 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2434 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2435 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2436 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2437 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2438 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2439 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2440 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2441 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2442
2443 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2444 MMIO_D(_MMIO(0x46508), D_ALL);
2445
2446 MMIO_D(_MMIO(0x49080), D_ALL);
2447 MMIO_D(_MMIO(0x49180), D_ALL);
2448 MMIO_D(_MMIO(0x49280), D_ALL);
2449
2450 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2451 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2452 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2453
2454 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2455 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2456 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2457
2458 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2459 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2460 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2461
2462 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2463 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2464 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2465
2466 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2467 MMIO_D(SBI_ADDR, D_ALL);
2468 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2469 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2470 MMIO_D(PIXCLK_GATE, D_ALL);
2471
2472 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2473 dp_aux_ch_ctl_mmio_write);
2474
2475 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2476 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2477 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2478 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2479 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2480
2481 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2482 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2483 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2484 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2485 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2486
2487 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2488 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2489 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2490 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2491 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2492
2493 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2494 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2495 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2496 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2497 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2498
2499 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2500 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2501 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2502
2503 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2504 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2505 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2506 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2507
2508 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2509 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2510 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2511 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2512
2513 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2514 MMIO_D(FORCEWAKE_ACK, D_ALL);
2515 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2516 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2517 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2518 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2519 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2520 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2521 MMIO_D(ECOBUS, D_ALL);
2522 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2523 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2524 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2525 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2526 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2527 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2528 MMIO_D(GEN6_RPSTAT1, D_ALL);
2529 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2530 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2531 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2532 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2533 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2534 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2535 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2536 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2537 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2538 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2539 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2540 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2541 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2542 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2543 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2544 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2545 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2546 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2547 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2548 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2549 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2550 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2551 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2552 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2553 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2554 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2555 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2556 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2557 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2558
2559 MMIO_D(RSTDBYCTL, D_ALL);
2560
2561 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2562 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2563 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2564
2565 MMIO_D(TILECTL, D_ALL);
2566
2567 MMIO_D(GEN6_UCGCTL1, D_ALL);
2568 MMIO_D(GEN6_UCGCTL2, D_ALL);
2569
2570 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2571
2572 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2573 MMIO_D(_MMIO(0x13812c), D_ALL);
2574 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2575 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2576 MMIO_D(HSW_IDICR, D_ALL);
2577 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2578
2579 MMIO_D(_MMIO(0x3c), D_ALL);
2580 MMIO_D(_MMIO(0x860), D_ALL);
2581 MMIO_D(ECOSKPD, D_ALL);
2582 MMIO_D(_MMIO(0x121d0), D_ALL);
2583 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2584 MMIO_D(_MMIO(0x41d0), D_ALL);
2585 MMIO_D(GAC_ECO_BITS, D_ALL);
2586 MMIO_D(_MMIO(0x6200), D_ALL);
2587 MMIO_D(_MMIO(0x6204), D_ALL);
2588 MMIO_D(_MMIO(0x6208), D_ALL);
2589 MMIO_D(_MMIO(0x7118), D_ALL);
2590 MMIO_D(_MMIO(0x7180), D_ALL);
2591 MMIO_D(_MMIO(0x7408), D_ALL);
2592 MMIO_D(_MMIO(0x7c00), D_ALL);
2593 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2594 MMIO_D(_MMIO(0x911c), D_ALL);
2595 MMIO_D(_MMIO(0x9120), D_ALL);
2596 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2597
2598 MMIO_D(GAB_CTL, D_ALL);
2599 MMIO_D(_MMIO(0x48800), D_ALL);
2600 MMIO_D(_MMIO(0xce044), D_ALL);
2601 MMIO_D(_MMIO(0xe6500), D_ALL);
2602 MMIO_D(_MMIO(0xe6504), D_ALL);
2603 MMIO_D(_MMIO(0xe6600), D_ALL);
2604 MMIO_D(_MMIO(0xe6604), D_ALL);
2605 MMIO_D(_MMIO(0xe6700), D_ALL);
2606 MMIO_D(_MMIO(0xe6704), D_ALL);
2607 MMIO_D(_MMIO(0xe6800), D_ALL);
2608 MMIO_D(_MMIO(0xe6804), D_ALL);
2609 MMIO_D(PCH_GMBUS4, D_ALL);
2610 MMIO_D(PCH_GMBUS5, D_ALL);
2611
2612 MMIO_D(_MMIO(0x902c), D_ALL);
2613 MMIO_D(_MMIO(0xec008), D_ALL);
2614 MMIO_D(_MMIO(0xec00c), D_ALL);
2615 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2616 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2617 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2618 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2619 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2620 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2621 MMIO_D(_MMIO(0xec408), D_ALL);
2622 MMIO_D(_MMIO(0xec40c), D_ALL);
2623 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2624 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2625 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2626 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2627 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2628 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2629 MMIO_D(_MMIO(0xfc810), D_ALL);
2630 MMIO_D(_MMIO(0xfc81c), D_ALL);
2631 MMIO_D(_MMIO(0xfc828), D_ALL);
2632 MMIO_D(_MMIO(0xfc834), D_ALL);
2633 MMIO_D(_MMIO(0xfcc00), D_ALL);
2634 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2635 MMIO_D(_MMIO(0xfcc18), D_ALL);
2636 MMIO_D(_MMIO(0xfcc24), D_ALL);
2637 MMIO_D(_MMIO(0xfd000), D_ALL);
2638 MMIO_D(_MMIO(0xfd00c), D_ALL);
2639 MMIO_D(_MMIO(0xfd018), D_ALL);
2640 MMIO_D(_MMIO(0xfd024), D_ALL);
2641 MMIO_D(_MMIO(0xfd034), D_ALL);
2642
2643 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2644 MMIO_D(_MMIO(0x2054), D_ALL);
2645 MMIO_D(_MMIO(0x12054), D_ALL);
2646 MMIO_D(_MMIO(0x22054), D_ALL);
2647 MMIO_D(_MMIO(0x1a054), D_ALL);
2648
2649 MMIO_D(_MMIO(0x44070), D_ALL);
2650 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2651 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2652 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2653 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2654 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2655
2656 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2657 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2658 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2659 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2660 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2661 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2662
2663 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2664 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2665 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2666
2667 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2668 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2669 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2670 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2671 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2672 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2673 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2674 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2675 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2676 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2677 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2678 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2679 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2680 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2681 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2682 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2683 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2684
2685 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2686 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2687 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2688 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2689 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2690 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2691 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2692 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2693 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2694 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2695 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2696
2697 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2698 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2699 return 0;
2700}
2701
2702static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2703{
2704 struct drm_i915_private *dev_priv = gvt->dev_priv;
2705 int ret;
2706
2707 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2708 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2709 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2710 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2711
2712 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2713 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2714 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2715 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2716
2717 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2718 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2719 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2720 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2721
2722 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2723 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2724 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2725 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2726
2727 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2728 intel_vgpu_reg_imr_handler);
2729 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2730 intel_vgpu_reg_ier_handler);
2731 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2732 intel_vgpu_reg_iir_handler);
2733 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2734
2735 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2736 intel_vgpu_reg_imr_handler);
2737 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2738 intel_vgpu_reg_ier_handler);
2739 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2740 intel_vgpu_reg_iir_handler);
2741 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2742
2743 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2744 intel_vgpu_reg_imr_handler);
2745 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2746 intel_vgpu_reg_ier_handler);
2747 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2748 intel_vgpu_reg_iir_handler);
2749 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2750
2751 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2752 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2753 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2754 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2755
2756 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2757 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2758 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2759 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2760
2761 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2762 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2763 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2764 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2765
2766 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2767 intel_vgpu_reg_master_irq_handler);
2768
2769 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2770 mmio_read_from_hw, NULL);
2771
2772#define RING_REG(base) _MMIO((base) + 0xd0)
2773 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2774 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2775 ring_reset_ctl_write);
2776#undef RING_REG
2777
2778#define RING_REG(base) _MMIO((base) + 0x230)
2779 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2780#undef RING_REG
2781
2782#define RING_REG(base) _MMIO((base) + 0x234)
2783 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2784 NULL, NULL);
2785#undef RING_REG
2786
2787#define RING_REG(base) _MMIO((base) + 0x244)
2788 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2789#undef RING_REG
2790
2791#define RING_REG(base) _MMIO((base) + 0x370)
2792 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2793#undef RING_REG
2794
2795#define RING_REG(base) _MMIO((base) + 0x3a0)
2796 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2797#undef RING_REG
2798
2799 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2800 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2801 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2802 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2803 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2804 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2805 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2806
2807 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2808
2809 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
2810 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2811
2812 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2813
2814#define RING_REG(base) _MMIO((base) + 0x270)
2815 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2816#undef RING_REG
2817
2818 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2819
2820 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2821
2822 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2823 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2824 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2825
2826 MMIO_D(WM_MISC, D_BDW);
2827 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
2828
2829 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2830 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2831 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2832
2833 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2834
2835 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2836 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2837 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2838
2839 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2840 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2841 NULL, NULL);
2842 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2843 NULL, NULL);
2844 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2845
2846 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2847 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2848 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2849 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2850 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2851 MMIO_D(_MMIO(0xb110), D_BDW);
2852
2853 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2854 NULL, force_nonpriv_write);
2855
2856 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2857 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2858
2859 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2860 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2861
2862 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2863
2864 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2865
2866 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2867
2868 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2869 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2870
2871 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2872 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2873 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2874 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2875
2876 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2877
2878 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2879 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2880 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2881 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2882 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2883 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2884 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2885 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2886 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2887 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2888 return 0;
2889}
2890
2891static int init_skl_mmio_info(struct intel_gvt *gvt)
2892{
2893 struct drm_i915_private *dev_priv = gvt->dev_priv;
2894 int ret;
2895
2896 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2897 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2898 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2899 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2900 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2901 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2902
2903 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2904 dp_aux_ch_ctl_mmio_write);
2905 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2906 dp_aux_ch_ctl_mmio_write);
2907 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2908 dp_aux_ch_ctl_mmio_write);
2909
2910 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2911 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2912
2913 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2914
2915 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
2916 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2917 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2918 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2919 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
2920 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2921 MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2922 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2923 MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2924 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2925 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2926 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2927 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2928 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2929 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2930 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2931 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2932 MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2933 MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2934 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2935
2936 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2937 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2938 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2939 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2940 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2941 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2942
2943 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2944 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2945 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2946 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2947 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2948 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2949
2950 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2951 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2952 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2953 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2954 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2955 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2956
2957 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2958 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2959 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2960 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2961
2962 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2963 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2964 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2965 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2966
2967 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2968 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2969 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2970 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2971
2972 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2973 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2974 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2975
2976 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2977 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2978 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2979
2980 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2981 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2982 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2983
2984 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2985 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2986 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2987
2988 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2989 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2990 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2991
2992 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2993 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2994 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2995
2996 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2997 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2998 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2999
3000 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3001 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3002 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3003
3004 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
3005 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
3006 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
3007
3008 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3009 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3010 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3011 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
3012
3013 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3014 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3015 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3016 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3017
3018 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3019 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3020 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3021 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3022
3023 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3024 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3025 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3026 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3027
3028 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3029 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3030 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3031 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3032
3033 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3034 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3035 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3036 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3037
3038 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3039 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3040 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3041 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3042
3043 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3044 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3045 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3046 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3047
3048 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3049 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3050 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3051 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3052
3053 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3054 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
3055 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
3056 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
3057 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3058
3059 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3060 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3061 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
3062
3063 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3064
3065 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3066 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
3067
3068 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3069 NULL, NULL);
3070 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3071 NULL, NULL);
3072
3073 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
3074 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
3075 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3076 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3077 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3078 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3079 NULL, NULL);
3080
3081 /* TRTT */
3082 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3083 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3084 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3085 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3086 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3087 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
3088 NULL, gen9_trtte_write);
3089 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
3090
3091 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3092
3093 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3094
3095 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3096 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3097 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3098
3099 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
3100 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
3101 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3102 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3103 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3104 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3105 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3106 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3107 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3108 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
3109
3110 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3111 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3112 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3113
3114 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3115 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3116 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
3117 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3118 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3119 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
3120 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3121 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3122 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3123
3124 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
3125#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
3126 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3127 NULL, csfe_chicken1_mmio_write);
3128#undef CSFE_CHICKEN1_REG
3129 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3130 NULL, NULL);
3131 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3132 NULL, NULL);
3133
3134 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
3135 MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
3136
3137 return 0;
3138}
3139
3140static int init_bxt_mmio_info(struct intel_gvt *gvt)
3141{
3142 struct drm_i915_private *dev_priv = gvt->dev_priv;
3143 int ret;
3144
3145 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3146
3147 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3148 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3149 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3150 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3151 MMIO_D(ERROR_GEN6, D_BXT);
3152 MMIO_D(DONE_REG, D_BXT);
3153 MMIO_D(EIR, D_BXT);
3154 MMIO_D(PGTBL_ER, D_BXT);
3155 MMIO_D(_MMIO(0x4194), D_BXT);
3156 MMIO_D(_MMIO(0x4294), D_BXT);
3157 MMIO_D(_MMIO(0x4494), D_BXT);
3158
3159 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3160 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3161 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3162 MMIO_RING_D(RING_IPEHR, D_BXT);
3163 MMIO_RING_D(RING_INSTPS, D_BXT);
3164 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3165 MMIO_RING_D(RING_BBSTATE, D_BXT);
3166 MMIO_RING_D(RING_IPEIR, D_BXT);
3167
3168 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3169
3170 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3171 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3172 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3173 NULL, bxt_phy_ctl_family_write);
3174 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3175 NULL, bxt_phy_ctl_family_write);
3176 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3177 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3178 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3179 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3180 NULL, bxt_port_pll_enable_write);
3181 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3182 NULL, bxt_port_pll_enable_write);
3183 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3184 bxt_port_pll_enable_write);
3185
3186 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3187 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3188 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3189 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3190 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3191 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3192 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3193 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3194 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3195
3196 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3197 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3198 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3199 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3200 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3201 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3202 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3203 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3204 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3205
3206 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3207 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3208 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3209 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3210 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3211 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3212 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3213 NULL, bxt_pcs_dw12_grp_write);
3214 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3215 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3216 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3217 bxt_port_tx_dw3_read, NULL);
3218 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3219 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3220 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3221 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3222 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3223 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3224 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3225 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3226 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3227 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3228 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3229 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3230 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3231 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3232 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3233
3234 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3235 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3236 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3237 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3238 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3239 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3240 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3241 NULL, bxt_pcs_dw12_grp_write);
3242 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3243 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3244 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3245 bxt_port_tx_dw3_read, NULL);
3246 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3247 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3248 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3249 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3250 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3251 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3252 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3253 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3254 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3255 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3256 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3257 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3258 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3259 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3260 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3261
3262 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3263 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3264 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3265 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3266 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3267 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3268 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3269 NULL, bxt_pcs_dw12_grp_write);
3270 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3271 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3272 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3273 bxt_port_tx_dw3_read, NULL);
3274 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3275 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3276 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3277 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3278 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3279 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3280 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3281 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3282 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3283 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3284 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3285 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3286 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3287 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3288 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3289
3290 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3291 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3292 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3293 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3294
3295 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3296 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3297
3298 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3299 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3300 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3301
3302 MMIO_D(RC6_CTX_BASE, D_BXT);
3303
3304 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3305 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3306 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3307 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3308 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
3309 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3310 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
3311 MMIO_F(HSW_CS_GPR(0), 0x40, F_CMD_ACCESS, 0, 0, D_BXT, NULL, NULL);
3312 MMIO_F(_MMIO(0x12600), 0x40, F_CMD_ACCESS, 0, 0, D_BXT, NULL, NULL);
3313 MMIO_F(BCS_GPR(0), 0x40, F_CMD_ACCESS, 0, 0, D_BXT, NULL, NULL);
3314 MMIO_F(_MMIO(0x1a600), 0x40, F_CMD_ACCESS, 0, 0, D_BXT, NULL, NULL);
3315
3316 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3317
3318 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
3319
3320 return 0;
3321}
3322
3323static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3324 unsigned int offset)
3325{
3326 unsigned long device = intel_gvt_get_device_type(gvt);
3327 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3328 int num = gvt->mmio.num_mmio_block;
3329 int i;
3330
3331 for (i = 0; i < num; i++, block++) {
3332 if (!(device & block->device))
3333 continue;
3334 if (offset >= i915_mmio_reg_offset(block->offset) &&
3335 offset < i915_mmio_reg_offset(block->offset) + block->size)
3336 return block;
3337 }
3338 return NULL;
3339}
3340
3341/**
3342 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3343 * @gvt: GVT device
3344 *
3345 * This function is called at the driver unloading stage, to clean up the MMIO
3346 * information table of GVT device
3347 *
3348 */
3349void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3350{
3351 struct hlist_node *tmp;
3352 struct intel_gvt_mmio_info *e;
3353 int i;
3354
3355 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3356 kfree(e);
3357
3358 vfree(gvt->mmio.mmio_attribute);
3359 gvt->mmio.mmio_attribute = NULL;
3360}
3361
3362/* Special MMIO blocks. */
3363static struct gvt_mmio_block mmio_blocks[] = {
3364 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
3365 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3366 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3367 pvinfo_mmio_read, pvinfo_mmio_write},
3368 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3369 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3370 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3371};
3372
3373/**
3374 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3375 * @gvt: GVT device
3376 *
3377 * This function is called at the initialization stage, to setup the MMIO
3378 * information table for GVT device
3379 *
3380 * Returns:
3381 * zero on success, negative if failed.
3382 */
3383int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3384{
3385 struct intel_gvt_device_info *info = &gvt->device_info;
3386 struct drm_i915_private *dev_priv = gvt->dev_priv;
3387 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
3388 int ret;
3389
3390 gvt->mmio.mmio_attribute = vzalloc(size);
3391 if (!gvt->mmio.mmio_attribute)
3392 return -ENOMEM;
3393
3394 ret = init_generic_mmio_info(gvt);
3395 if (ret)
3396 goto err;
3397
3398 if (IS_BROADWELL(dev_priv)) {
3399 ret = init_broadwell_mmio_info(gvt);
3400 if (ret)
3401 goto err;
3402 } else if (IS_SKYLAKE(dev_priv)
3403 || IS_KABYLAKE(dev_priv)
3404 || IS_COFFEELAKE(dev_priv)) {
3405 ret = init_broadwell_mmio_info(gvt);
3406 if (ret)
3407 goto err;
3408 ret = init_skl_mmio_info(gvt);
3409 if (ret)
3410 goto err;
3411 } else if (IS_BROXTON(dev_priv)) {
3412 ret = init_broadwell_mmio_info(gvt);
3413 if (ret)
3414 goto err;
3415 ret = init_skl_mmio_info(gvt);
3416 if (ret)
3417 goto err;
3418 ret = init_bxt_mmio_info(gvt);
3419 if (ret)
3420 goto err;
3421 }
3422
3423 gvt->mmio.mmio_block = mmio_blocks;
3424 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3425
3426 return 0;
3427err:
3428 intel_gvt_clean_mmio_info(gvt);
3429 return ret;
3430}
3431
3432/**
3433 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3434 * @gvt: a GVT device
3435 * @handler: the handler
3436 * @data: private data given to handler
3437 *
3438 * Returns:
3439 * Zero on success, negative error code if failed.
3440 */
3441int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3442 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3443 void *data)
3444{
3445 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3446 struct intel_gvt_mmio_info *e;
3447 int i, j, ret;
3448
3449 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3450 ret = handler(gvt, e->offset, data);
3451 if (ret)
3452 return ret;
3453 }
3454
3455 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3456 for (j = 0; j < block->size; j += 4) {
3457 ret = handler(gvt,
3458 i915_mmio_reg_offset(block->offset) + j,
3459 data);
3460 if (ret)
3461 return ret;
3462 }
3463 }
3464 return 0;
3465}
3466
3467/**
3468 * intel_vgpu_default_mmio_read - default MMIO read handler
3469 * @vgpu: a vGPU
3470 * @offset: access offset
3471 * @p_data: data return buffer
3472 * @bytes: access data length
3473 *
3474 * Returns:
3475 * Zero on success, negative error code if failed.
3476 */
3477int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3478 void *p_data, unsigned int bytes)
3479{
3480 read_vreg(vgpu, offset, p_data, bytes);
3481 return 0;
3482}
3483
3484/**
3485 * intel_t_default_mmio_write - default MMIO write handler
3486 * @vgpu: a vGPU
3487 * @offset: access offset
3488 * @p_data: write data buffer
3489 * @bytes: access data length
3490 *
3491 * Returns:
3492 * Zero on success, negative error code if failed.
3493 */
3494int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3495 void *p_data, unsigned int bytes)
3496{
3497 write_vreg(vgpu, offset, p_data, bytes);
3498 return 0;
3499}
3500
3501/**
3502 * intel_vgpu_mask_mmio_write - write mask register
3503 * @vgpu: a vGPU
3504 * @offset: access offset
3505 * @p_data: write data buffer
3506 * @bytes: access data length
3507 *
3508 * Returns:
3509 * Zero on success, negative error code if failed.
3510 */
3511int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3512 void *p_data, unsigned int bytes)
3513{
3514 u32 mask, old_vreg;
3515
3516 old_vreg = vgpu_vreg(vgpu, offset);
3517 write_vreg(vgpu, offset, p_data, bytes);
3518 mask = vgpu_vreg(vgpu, offset) >> 16;
3519 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3520 (vgpu_vreg(vgpu, offset) & mask);
3521
3522 return 0;
3523}
3524
3525/**
3526 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3527 * force-nopriv register
3528 *
3529 * @gvt: a GVT device
3530 * @offset: register offset
3531 *
3532 * Returns:
3533 * True if the register is in force-nonpriv whitelist;
3534 * False if outside;
3535 */
3536bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3537 unsigned int offset)
3538{
3539 return in_whitelist(offset);
3540}
3541
3542/**
3543 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3544 * @vgpu: a vGPU
3545 * @offset: register offset
3546 * @pdata: data buffer
3547 * @bytes: data length
3548 * @is_read: read or write
3549 *
3550 * Returns:
3551 * Zero on success, negative error code if failed.
3552 */
3553int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3554 void *pdata, unsigned int bytes, bool is_read)
3555{
3556 struct intel_gvt *gvt = vgpu->gvt;
3557 struct intel_gvt_mmio_info *mmio_info;
3558 struct gvt_mmio_block *mmio_block;
3559 gvt_mmio_func func;
3560 int ret;
3561
3562 if (WARN_ON(bytes > 8))
3563 return -EINVAL;
3564
3565 /*
3566 * Handle special MMIO blocks.
3567 */
3568 mmio_block = find_mmio_block(gvt, offset);
3569 if (mmio_block) {
3570 func = is_read ? mmio_block->read : mmio_block->write;
3571 if (func)
3572 return func(vgpu, offset, pdata, bytes);
3573 goto default_rw;
3574 }
3575
3576 /*
3577 * Normal tracked MMIOs.
3578 */
3579 mmio_info = find_mmio_info(gvt, offset);
3580 if (!mmio_info) {
3581 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3582 goto default_rw;
3583 }
3584
3585 if (is_read)
3586 return mmio_info->read(vgpu, offset, pdata, bytes);
3587 else {
3588 u64 ro_mask = mmio_info->ro_mask;
3589 u32 old_vreg = 0;
3590 u64 data = 0;
3591
3592 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3593 old_vreg = vgpu_vreg(vgpu, offset);
3594 }
3595
3596 if (likely(!ro_mask))
3597 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3598 else if (!~ro_mask) {
3599 gvt_vgpu_err("try to write RO reg %x\n", offset);
3600 return 0;
3601 } else {
3602 /* keep the RO bits in the virtual register */
3603 memcpy(&data, pdata, bytes);
3604 data &= ~ro_mask;
3605 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3606 ret = mmio_info->write(vgpu, offset, &data, bytes);
3607 }
3608
3609 /* higher 16bits of mode ctl regs are mask bits for change */
3610 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3611 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3612
3613 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3614 | (vgpu_vreg(vgpu, offset) & mask);
3615 }
3616 }
3617
3618 return ret;
3619
3620default_rw:
3621 return is_read ?
3622 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3623 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3624}