| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright 2019 Intel Corporation. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __INTEL_PCH__ |
| 7 | #define __INTEL_PCH__ |
| 8 | |
| 9 | struct drm_i915_private; |
| 10 | |
| 11 | /* |
| 12 | * Sorted by south display engine compatibility. |
| 13 | * If the new PCH comes with a south display engine that is not |
| 14 | * inherited from the latest item, please do not add it to the |
| 15 | * end. Instead, add it right after its "parent" PCH. |
| 16 | */ |
| 17 | enum intel_pch { |
| 18 | PCH_NOP = -1, /* PCH without south display */ |
| 19 | PCH_NONE = 0, /* No PCH present */ |
| 20 | PCH_IBX, /* Ibexpeak PCH */ |
| 21 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
| 22 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ |
| 23 | PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ |
| 24 | PCH_CNP, /* Cannon/Comet Lake PCH */ |
| 25 | PCH_ICP, /* Ice Lake PCH */ |
| 26 | PCH_MCC, /* Mule Creek Canyon PCH */ |
| 27 | PCH_TGP, /* Tiger Lake PCH */ |
| 28 | }; |
| 29 | |
| 30 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 |
| 31 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 32 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 33 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 34 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 35 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
| 36 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 |
| 37 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 |
| 38 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
| 39 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 |
| 40 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 |
| 41 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 |
| 42 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 |
| 43 | #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 |
| 44 | #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 |
| 45 | #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 |
| 46 | #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 |
| 47 | #define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880 |
| 48 | #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 |
| 49 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
| 50 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
| 51 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
| 52 | |
| 53 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
| 54 | #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) |
| 55 | #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) |
| 56 | #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) |
| 57 | #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) |
| 58 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) |
| 59 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) |
| 60 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) |
| 61 | #define HAS_PCH_LPT_LP(dev_priv) \ |
| 62 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ |
| 63 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) |
| 64 | #define HAS_PCH_LPT_H(dev_priv) \ |
| 65 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ |
| 66 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) |
| 67 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
| 68 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) |
| 69 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) |
| 70 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) |
| 71 | |
| 72 | void intel_detect_pch(struct drm_i915_private *dev_priv); |
| 73 | |
| 74 | #endif /* __INTEL_PCH__ */ |