Blame - marvell/linux/drivers/gpu/drm/i915/intel_sideband.h - T108

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b.liu	e958203	2025-04-17 19:18:16 +0800	[diff] [blame^]	1	/* SPDX-License-Identifier: MIT */
				2
				3	#ifndef _INTEL_SIDEBAND_H_
				4	#define _INTEL_SIDEBAND_H_
				5
				6	#include <linux/bitops.h>
				7	#include <linux/types.h>
				8
				9	struct drm_i915_private;
				10	enum pipe;
				11
				12	enum intel_sbi_destination {
				13	SBI_ICLK,
				14	SBI_MPHY,
				15	};
				16
				17	enum {
				18	VLV_IOSF_SB_BUNIT,
				19	VLV_IOSF_SB_CCK,
				20	VLV_IOSF_SB_CCU,
				21	VLV_IOSF_SB_DPIO,
				22	VLV_IOSF_SB_FLISDSI,
				23	VLV_IOSF_SB_GPIO,
				24	VLV_IOSF_SB_NC,
				25	VLV_IOSF_SB_PUNIT,
				26	};
				27
				28	void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
				29	u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
				30	void vlv_iosf_sb_write(struct drm_i915_private *i915,
				31	u8 port, u32 reg, u32 val);
				32	void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
				33
				34	static inline void vlv_bunit_get(struct drm_i915_private *i915)
				35	{
				36	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
				37	}
				38
				39	u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
				40	void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
				41
				42	static inline void vlv_bunit_put(struct drm_i915_private *i915)
				43	{
				44	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
				45	}
				46
				47	static inline void vlv_cck_get(struct drm_i915_private *i915)
				48	{
				49	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
				50	}
				51
				52	u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
				53	void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
				54
				55	static inline void vlv_cck_put(struct drm_i915_private *i915)
				56	{
				57	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
				58	}
				59
				60	static inline void vlv_ccu_get(struct drm_i915_private *i915)
				61	{
				62	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
				63	}
				64
				65	u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
				66	void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
				67
				68	static inline void vlv_ccu_put(struct drm_i915_private *i915)
				69	{
				70	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
				71	}
				72
				73	static inline void vlv_dpio_get(struct drm_i915_private *i915)
				74	{
				75	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
				76	}
				77
				78	u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
				79	void vlv_dpio_write(struct drm_i915_private *i915,
				80	enum pipe pipe, int reg, u32 val);
				81
				82	static inline void vlv_dpio_put(struct drm_i915_private *i915)
				83	{
				84	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
				85	}
				86
				87	static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
				88	{
				89	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
				90	}
				91
				92	u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
				93	void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
				94
				95	static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
				96	{
				97	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
				98	}
				99
				100	static inline void vlv_nc_get(struct drm_i915_private *i915)
				101	{
				102	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
				103	}
				104
				105	u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
				106
				107	static inline void vlv_nc_put(struct drm_i915_private *i915)
				108	{
				109	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
				110	}
				111
				112	static inline void vlv_punit_get(struct drm_i915_private *i915)
				113	{
				114	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
				115	}
				116
				117	u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
				118	int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
				119
				120	static inline void vlv_punit_put(struct drm_i915_private *i915)
				121	{
				122	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
				123	}
				124
				125	u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
				126	enum intel_sbi_destination destination);
				127	void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
				128	enum intel_sbi_destination destination);
				129
				130	int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
				131	u32 val, u32 val1);
				132	int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
				133	u32 val, int fast_timeout_us,
				134	int slow_timeout_ms);
				135	#define sandybridge_pcode_write(i915, mbox, val) \
				136	sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
				137
				138	int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
				139	u32 reply_mask, u32 reply, int timeout_base_ms);
				140
				141	#endif /* _INTEL_SIDEBAND_H */