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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / gpu / drm / panel / panel-simple.c
blob: cca716278dcc34e38166e2f47faf6c48d9b01233 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
25#include <linux/delay.h>
26#include <linux/gpio/consumer.h>
27#include <linux/module.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
32#include <video/display_timing.h>
33#include <video/of_display_timing.h>
34#include <video/videomode.h>
35
36#include <drm/drm_crtc.h>
37#include <drm/drm_device.h>
38#include <drm/drm_mipi_dsi.h>
39#include <drm/drm_panel.h>
40
41/**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97};
98
99struct panel_simple {
100 struct drm_panel base;
101 bool prepared;
102 bool enabled;
103 bool no_hpd;
104
105 const struct panel_desc *desc;
106
107 struct backlight_device *backlight;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112
113 struct drm_display_mode override_mode;
114};
115
116static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117{
118 return container_of(panel, struct panel_simple, base);
119}
120
121static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
122{
123 struct drm_connector *connector = panel->base.connector;
124 struct drm_device *drm = panel->base.drm;
125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
127
128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
130 struct videomode vm;
131
132 videomode_from_timing(dt, &vm);
133 mode = drm_mode_create(drm);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u\n",
136 dt->hactive.typ, dt->vactive.typ);
137 continue;
138 }
139
140 drm_display_mode_from_videomode(&vm, mode);
141
142 mode->type |= DRM_MODE_TYPE_DRIVER;
143
144 if (panel->desc->num_timings == 1)
145 mode->type |= DRM_MODE_TYPE_PREFERRED;
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
151 return num;
152}
153
154static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
155{
156 struct drm_connector *connector = panel->base.connector;
157 struct drm_device *drm = panel->base.drm;
158 struct drm_display_mode *mode;
159 unsigned int i, num = 0;
160
161 for (i = 0; i < panel->desc->num_modes; i++) {
162 const struct drm_display_mode *m = &panel->desc->modes[i];
163
164 mode = drm_mode_duplicate(drm, m);
165 if (!mode) {
166 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
167 m->hdisplay, m->vdisplay, m->vrefresh);
168 continue;
169 }
170
171 mode->type |= DRM_MODE_TYPE_DRIVER;
172
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
175
176 drm_mode_set_name(mode);
177
178 drm_mode_probed_add(connector, mode);
179 num++;
180 }
181
182 return num;
183}
184
185static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
186{
187 struct drm_connector *connector = panel->base.connector;
188 struct drm_device *drm = panel->base.drm;
189 struct drm_display_mode *mode;
190 bool has_override = panel->override_mode.type;
191 unsigned int num = 0;
192
193 if (!panel->desc)
194 return 0;
195
196 if (has_override) {
197 mode = drm_mode_duplicate(drm, &panel->override_mode);
198 if (mode) {
199 drm_mode_probed_add(connector, mode);
200 num = 1;
201 } else {
202 dev_err(drm->dev, "failed to add override mode\n");
203 }
204 }
205
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
208 num = panel_simple_get_timings_modes(panel);
209
210 /*
211 * Only add fixed modes if timings/override added no mode.
212 *
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
215 */
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 if (num == 0)
218 num = panel_simple_get_display_modes(panel);
219
220 connector->display_info.bpc = panel->desc->bpc;
221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
226 connector->display_info.bus_flags = panel->desc->bus_flags;
227
228 return num;
229}
230
231static int panel_simple_disable(struct drm_panel *panel)
232{
233 struct panel_simple *p = to_panel_simple(panel);
234
235 if (!p->enabled)
236 return 0;
237
238 if (p->backlight) {
239 p->backlight->props.power = FB_BLANK_POWERDOWN;
240 p->backlight->props.state |= BL_CORE_FBBLANK;
241 backlight_update_status(p->backlight);
242 }
243
244 if (p->desc->delay.disable)
245 msleep(p->desc->delay.disable);
246
247 p->enabled = false;
248
249 return 0;
250}
251
252static int panel_simple_unprepare(struct drm_panel *panel)
253{
254 struct panel_simple *p = to_panel_simple(panel);
255
256 if (!p->prepared)
257 return 0;
258
259 gpiod_set_value_cansleep(p->enable_gpio, 0);
260
261 regulator_disable(p->supply);
262
263 if (p->desc->delay.unprepare)
264 msleep(p->desc->delay.unprepare);
265
266 p->prepared = false;
267
268 return 0;
269}
270
271static int panel_simple_prepare(struct drm_panel *panel)
272{
273 struct panel_simple *p = to_panel_simple(panel);
274 unsigned int delay;
275 int err;
276
277 if (p->prepared)
278 return 0;
279
280 err = regulator_enable(p->supply);
281 if (err < 0) {
282 dev_err(panel->dev, "failed to enable supply: %d\n", err);
283 return err;
284 }
285
286 gpiod_set_value_cansleep(p->enable_gpio, 1);
287
288 delay = p->desc->delay.prepare;
289 if (p->no_hpd)
290 delay += p->desc->delay.hpd_absent_delay;
291 if (delay)
292 msleep(delay);
293
294 p->prepared = true;
295
296 return 0;
297}
298
299static int panel_simple_enable(struct drm_panel *panel)
300{
301 struct panel_simple *p = to_panel_simple(panel);
302
303 if (p->enabled)
304 return 0;
305
306 if (p->desc->delay.enable)
307 msleep(p->desc->delay.enable);
308
309 if (p->backlight) {
310 p->backlight->props.state &= ~BL_CORE_FBBLANK;
311 p->backlight->props.power = FB_BLANK_UNBLANK;
312 backlight_update_status(p->backlight);
313 }
314
315 p->enabled = true;
316
317 return 0;
318}
319
320static int panel_simple_get_modes(struct drm_panel *panel)
321{
322 struct panel_simple *p = to_panel_simple(panel);
323 int num = 0;
324
325 /* probe EDID if a DDC bus is available */
326 if (p->ddc) {
327 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
328 drm_connector_update_edid_property(panel->connector, edid);
329 if (edid) {
330 num += drm_add_edid_modes(panel->connector, edid);
331 kfree(edid);
332 }
333 }
334
335 /* add hard-coded panel modes */
336 num += panel_simple_get_non_edid_modes(p);
337
338 return num;
339}
340
341static int panel_simple_get_timings(struct drm_panel *panel,
342 unsigned int num_timings,
343 struct display_timing *timings)
344{
345 struct panel_simple *p = to_panel_simple(panel);
346 unsigned int i;
347
348 if (p->desc->num_timings < num_timings)
349 num_timings = p->desc->num_timings;
350
351 if (timings)
352 for (i = 0; i < num_timings; i++)
353 timings[i] = p->desc->timings[i];
354
355 return p->desc->num_timings;
356}
357
358static const struct drm_panel_funcs panel_simple_funcs = {
359 .disable = panel_simple_disable,
360 .unprepare = panel_simple_unprepare,
361 .prepare = panel_simple_prepare,
362 .enable = panel_simple_enable,
363 .get_modes = panel_simple_get_modes,
364 .get_timings = panel_simple_get_timings,
365};
366
367#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
368 (to_check->field.typ >= bounds->field.min && \
369 to_check->field.typ <= bounds->field.max)
370static void panel_simple_parse_panel_timing_node(struct device *dev,
371 struct panel_simple *panel,
372 const struct display_timing *ot)
373{
374 const struct panel_desc *desc = panel->desc;
375 struct videomode vm;
376 unsigned int i;
377
378 if (WARN_ON(desc->num_modes)) {
379 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
380 return;
381 }
382 if (WARN_ON(!desc->num_timings)) {
383 dev_err(dev, "Reject override mode: no timings specified\n");
384 return;
385 }
386
387 for (i = 0; i < panel->desc->num_timings; i++) {
388 const struct display_timing *dt = &panel->desc->timings[i];
389
390 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
391 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
392 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
393 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
394 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
395 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
396 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
397 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
398 continue;
399
400 if (ot->flags != dt->flags)
401 continue;
402
403 videomode_from_timing(ot, &vm);
404 drm_display_mode_from_videomode(&vm, &panel->override_mode);
405 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
406 DRM_MODE_TYPE_PREFERRED;
407 break;
408 }
409
410 if (WARN_ON(!panel->override_mode.type))
411 dev_err(dev, "Reject override mode: No display_timing found\n");
412}
413
414static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
415{
416 struct device_node *backlight, *ddc;
417 struct panel_simple *panel;
418 struct display_timing dt;
419 int err;
420
421 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
422 if (!panel)
423 return -ENOMEM;
424
425 panel->enabled = false;
426 panel->prepared = false;
427 panel->desc = desc;
428
429 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
430
431 panel->supply = devm_regulator_get(dev, "power");
432 if (IS_ERR(panel->supply))
433 return PTR_ERR(panel->supply);
434
435 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
436 GPIOD_OUT_LOW);
437 if (IS_ERR(panel->enable_gpio)) {
438 err = PTR_ERR(panel->enable_gpio);
439 if (err != -EPROBE_DEFER)
440 dev_err(dev, "failed to request GPIO: %d\n", err);
441 return err;
442 }
443
444 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
445 if (backlight) {
446 panel->backlight = of_find_backlight_by_node(backlight);
447 of_node_put(backlight);
448
449 if (!panel->backlight)
450 return -EPROBE_DEFER;
451 }
452
453 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
454 if (ddc) {
455 panel->ddc = of_find_i2c_adapter_by_node(ddc);
456 of_node_put(ddc);
457
458 if (!panel->ddc) {
459 err = -EPROBE_DEFER;
460 goto free_backlight;
461 }
462 }
463
464 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
465 panel_simple_parse_panel_timing_node(dev, panel, &dt);
466
467 drm_panel_init(&panel->base);
468 panel->base.dev = dev;
469 panel->base.funcs = &panel_simple_funcs;
470
471 err = drm_panel_add(&panel->base);
472 if (err < 0)
473 goto free_ddc;
474
475 dev_set_drvdata(dev, panel);
476
477 return 0;
478
479free_ddc:
480 if (panel->ddc)
481 put_device(&panel->ddc->dev);
482free_backlight:
483 if (panel->backlight)
484 put_device(&panel->backlight->dev);
485
486 return err;
487}
488
489static int panel_simple_remove(struct device *dev)
490{
491 struct panel_simple *panel = dev_get_drvdata(dev);
492
493 drm_panel_remove(&panel->base);
494
495 panel_simple_disable(&panel->base);
496 panel_simple_unprepare(&panel->base);
497
498 if (panel->ddc)
499 put_device(&panel->ddc->dev);
500
501 if (panel->backlight)
502 put_device(&panel->backlight->dev);
503
504 return 0;
505}
506
507static void panel_simple_shutdown(struct device *dev)
508{
509 struct panel_simple *panel = dev_get_drvdata(dev);
510
511 panel_simple_disable(&panel->base);
512 panel_simple_unprepare(&panel->base);
513}
514
515static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
516 .clock = 9000,
517 .hdisplay = 480,
518 .hsync_start = 480 + 2,
519 .hsync_end = 480 + 2 + 41,
520 .htotal = 480 + 2 + 41 + 2,
521 .vdisplay = 272,
522 .vsync_start = 272 + 2,
523 .vsync_end = 272 + 2 + 10,
524 .vtotal = 272 + 2 + 10 + 2,
525 .vrefresh = 60,
526 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
527};
528
529static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
530 .modes = &ampire_am_480272h3tmqw_t01h_mode,
531 .num_modes = 1,
532 .bpc = 8,
533 .size = {
534 .width = 99,
535 .height = 58,
536 },
537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
538};
539
540static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
541 .clock = 33333,
542 .hdisplay = 800,
543 .hsync_start = 800 + 0,
544 .hsync_end = 800 + 0 + 255,
545 .htotal = 800 + 0 + 255 + 0,
546 .vdisplay = 480,
547 .vsync_start = 480 + 2,
548 .vsync_end = 480 + 2 + 45,
549 .vtotal = 480 + 2 + 45 + 0,
550 .vrefresh = 60,
551 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
552};
553
554static const struct panel_desc ampire_am800480r3tmqwa1h = {
555 .modes = &ampire_am800480r3tmqwa1h_mode,
556 .num_modes = 1,
557 .bpc = 6,
558 .size = {
559 .width = 152,
560 .height = 91,
561 },
562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
563};
564
565static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
566 .pixelclock = { 26400000, 33300000, 46800000 },
567 .hactive = { 800, 800, 800 },
568 .hfront_porch = { 16, 210, 354 },
569 .hback_porch = { 45, 36, 6 },
570 .hsync_len = { 1, 10, 40 },
571 .vactive = { 480, 480, 480 },
572 .vfront_porch = { 7, 22, 147 },
573 .vback_porch = { 22, 13, 3 },
574 .vsync_len = { 1, 10, 20 },
575 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
576 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
577};
578
579static const struct panel_desc armadeus_st0700_adapt = {
580 .timings = &santek_st0700i5y_rbslw_f_timing,
581 .num_timings = 1,
582 .bpc = 6,
583 .size = {
584 .width = 154,
585 .height = 86,
586 },
587 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
589};
590
591static const struct drm_display_mode auo_b101aw03_mode = {
592 .clock = 51450,
593 .hdisplay = 1024,
594 .hsync_start = 1024 + 156,
595 .hsync_end = 1024 + 156 + 8,
596 .htotal = 1024 + 156 + 8 + 156,
597 .vdisplay = 600,
598 .vsync_start = 600 + 16,
599 .vsync_end = 600 + 16 + 6,
600 .vtotal = 600 + 16 + 6 + 16,
601 .vrefresh = 60,
602};
603
604static const struct panel_desc auo_b101aw03 = {
605 .modes = &auo_b101aw03_mode,
606 .num_modes = 1,
607 .bpc = 6,
608 .size = {
609 .width = 223,
610 .height = 125,
611 },
612};
613
614static const struct display_timing auo_b101ean01_timing = {
615 .pixelclock = { 65300000, 72500000, 75000000 },
616 .hactive = { 1280, 1280, 1280 },
617 .hfront_porch = { 18, 119, 119 },
618 .hback_porch = { 21, 21, 21 },
619 .hsync_len = { 32, 32, 32 },
620 .vactive = { 800, 800, 800 },
621 .vfront_porch = { 4, 4, 4 },
622 .vback_porch = { 8, 8, 8 },
623 .vsync_len = { 18, 20, 20 },
624};
625
626static const struct panel_desc auo_b101ean01 = {
627 .timings = &auo_b101ean01_timing,
628 .num_timings = 1,
629 .bpc = 6,
630 .size = {
631 .width = 217,
632 .height = 136,
633 },
634};
635
636static const struct drm_display_mode auo_b101xtn01_mode = {
637 .clock = 72000,
638 .hdisplay = 1366,
639 .hsync_start = 1366 + 20,
640 .hsync_end = 1366 + 20 + 70,
641 .htotal = 1366 + 20 + 70,
642 .vdisplay = 768,
643 .vsync_start = 768 + 14,
644 .vsync_end = 768 + 14 + 42,
645 .vtotal = 768 + 14 + 42,
646 .vrefresh = 60,
647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
648};
649
650static const struct panel_desc auo_b101xtn01 = {
651 .modes = &auo_b101xtn01_mode,
652 .num_modes = 1,
653 .bpc = 6,
654 .size = {
655 .width = 223,
656 .height = 125,
657 },
658};
659
660static const struct drm_display_mode auo_b116xw03_mode = {
661 .clock = 70589,
662 .hdisplay = 1366,
663 .hsync_start = 1366 + 40,
664 .hsync_end = 1366 + 40 + 40,
665 .htotal = 1366 + 40 + 40 + 32,
666 .vdisplay = 768,
667 .vsync_start = 768 + 10,
668 .vsync_end = 768 + 10 + 12,
669 .vtotal = 768 + 10 + 12 + 6,
670 .vrefresh = 60,
671};
672
673static const struct panel_desc auo_b116xw03 = {
674 .modes = &auo_b116xw03_mode,
675 .num_modes = 1,
676 .bpc = 6,
677 .size = {
678 .width = 256,
679 .height = 144,
680 },
681};
682
683static const struct drm_display_mode auo_b133xtn01_mode = {
684 .clock = 69500,
685 .hdisplay = 1366,
686 .hsync_start = 1366 + 48,
687 .hsync_end = 1366 + 48 + 32,
688 .htotal = 1366 + 48 + 32 + 20,
689 .vdisplay = 768,
690 .vsync_start = 768 + 3,
691 .vsync_end = 768 + 3 + 6,
692 .vtotal = 768 + 3 + 6 + 13,
693 .vrefresh = 60,
694};
695
696static const struct panel_desc auo_b133xtn01 = {
697 .modes = &auo_b133xtn01_mode,
698 .num_modes = 1,
699 .bpc = 6,
700 .size = {
701 .width = 293,
702 .height = 165,
703 },
704};
705
706static const struct drm_display_mode auo_b133htn01_mode = {
707 .clock = 150660,
708 .hdisplay = 1920,
709 .hsync_start = 1920 + 172,
710 .hsync_end = 1920 + 172 + 80,
711 .htotal = 1920 + 172 + 80 + 60,
712 .vdisplay = 1080,
713 .vsync_start = 1080 + 25,
714 .vsync_end = 1080 + 25 + 10,
715 .vtotal = 1080 + 25 + 10 + 10,
716 .vrefresh = 60,
717};
718
719static const struct panel_desc auo_b133htn01 = {
720 .modes = &auo_b133htn01_mode,
721 .num_modes = 1,
722 .bpc = 6,
723 .size = {
724 .width = 293,
725 .height = 165,
726 },
727 .delay = {
728 .prepare = 105,
729 .enable = 20,
730 .unprepare = 50,
731 },
732};
733
734static const struct display_timing auo_g070vvn01_timings = {
735 .pixelclock = { 33300000, 34209000, 45000000 },
736 .hactive = { 800, 800, 800 },
737 .hfront_porch = { 20, 40, 200 },
738 .hback_porch = { 87, 40, 1 },
739 .hsync_len = { 1, 48, 87 },
740 .vactive = { 480, 480, 480 },
741 .vfront_porch = { 5, 13, 200 },
742 .vback_porch = { 31, 31, 29 },
743 .vsync_len = { 1, 1, 3 },
744};
745
746static const struct panel_desc auo_g070vvn01 = {
747 .timings = &auo_g070vvn01_timings,
748 .num_timings = 1,
749 .bpc = 8,
750 .size = {
751 .width = 152,
752 .height = 91,
753 },
754 .delay = {
755 .prepare = 200,
756 .enable = 50,
757 .disable = 50,
758 .unprepare = 1000,
759 },
760};
761
762static const struct drm_display_mode auo_g101evn010_mode = {
763 .clock = 68930,
764 .hdisplay = 1280,
765 .hsync_start = 1280 + 82,
766 .hsync_end = 1280 + 82 + 2,
767 .htotal = 1280 + 82 + 2 + 84,
768 .vdisplay = 800,
769 .vsync_start = 800 + 8,
770 .vsync_end = 800 + 8 + 2,
771 .vtotal = 800 + 8 + 2 + 6,
772 .vrefresh = 60,
773};
774
775static const struct panel_desc auo_g101evn010 = {
776 .modes = &auo_g101evn010_mode,
777 .num_modes = 1,
778 .bpc = 6,
779 .size = {
780 .width = 216,
781 .height = 135,
782 },
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
784};
785
786static const struct drm_display_mode auo_g104sn02_mode = {
787 .clock = 40000,
788 .hdisplay = 800,
789 .hsync_start = 800 + 40,
790 .hsync_end = 800 + 40 + 216,
791 .htotal = 800 + 40 + 216 + 128,
792 .vdisplay = 600,
793 .vsync_start = 600 + 10,
794 .vsync_end = 600 + 10 + 35,
795 .vtotal = 600 + 10 + 35 + 2,
796 .vrefresh = 60,
797};
798
799static const struct panel_desc auo_g104sn02 = {
800 .modes = &auo_g104sn02_mode,
801 .num_modes = 1,
802 .bpc = 8,
803 .size = {
804 .width = 211,
805 .height = 158,
806 },
807};
808
809static const struct display_timing auo_g133han01_timings = {
810 .pixelclock = { 134000000, 141200000, 149000000 },
811 .hactive = { 1920, 1920, 1920 },
812 .hfront_porch = { 39, 58, 77 },
813 .hback_porch = { 59, 88, 117 },
814 .hsync_len = { 28, 42, 56 },
815 .vactive = { 1080, 1080, 1080 },
816 .vfront_porch = { 3, 8, 11 },
817 .vback_porch = { 5, 14, 19 },
818 .vsync_len = { 4, 14, 19 },
819};
820
821static const struct panel_desc auo_g133han01 = {
822 .timings = &auo_g133han01_timings,
823 .num_timings = 1,
824 .bpc = 8,
825 .size = {
826 .width = 293,
827 .height = 165,
828 },
829 .delay = {
830 .prepare = 200,
831 .enable = 50,
832 .disable = 50,
833 .unprepare = 1000,
834 },
835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
836};
837
838static const struct display_timing auo_g185han01_timings = {
839 .pixelclock = { 120000000, 144000000, 175000000 },
840 .hactive = { 1920, 1920, 1920 },
841 .hfront_porch = { 36, 120, 148 },
842 .hback_porch = { 24, 88, 108 },
843 .hsync_len = { 20, 48, 64 },
844 .vactive = { 1080, 1080, 1080 },
845 .vfront_porch = { 6, 10, 40 },
846 .vback_porch = { 2, 5, 20 },
847 .vsync_len = { 2, 5, 20 },
848};
849
850static const struct panel_desc auo_g185han01 = {
851 .timings = &auo_g185han01_timings,
852 .num_timings = 1,
853 .bpc = 8,
854 .size = {
855 .width = 409,
856 .height = 230,
857 },
858 .delay = {
859 .prepare = 50,
860 .enable = 200,
861 .disable = 110,
862 .unprepare = 1000,
863 },
864 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
865};
866
867static const struct display_timing auo_p320hvn03_timings = {
868 .pixelclock = { 106000000, 148500000, 164000000 },
869 .hactive = { 1920, 1920, 1920 },
870 .hfront_porch = { 25, 50, 130 },
871 .hback_porch = { 25, 50, 130 },
872 .hsync_len = { 20, 40, 105 },
873 .vactive = { 1080, 1080, 1080 },
874 .vfront_porch = { 8, 17, 150 },
875 .vback_porch = { 8, 17, 150 },
876 .vsync_len = { 4, 11, 100 },
877};
878
879static const struct panel_desc auo_p320hvn03 = {
880 .timings = &auo_p320hvn03_timings,
881 .num_timings = 1,
882 .bpc = 8,
883 .size = {
884 .width = 698,
885 .height = 393,
886 },
887 .delay = {
888 .prepare = 1,
889 .enable = 450,
890 .unprepare = 500,
891 },
892 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
893};
894
895static const struct drm_display_mode auo_t215hvn01_mode = {
896 .clock = 148800,
897 .hdisplay = 1920,
898 .hsync_start = 1920 + 88,
899 .hsync_end = 1920 + 88 + 44,
900 .htotal = 1920 + 88 + 44 + 148,
901 .vdisplay = 1080,
902 .vsync_start = 1080 + 4,
903 .vsync_end = 1080 + 4 + 5,
904 .vtotal = 1080 + 4 + 5 + 36,
905 .vrefresh = 60,
906};
907
908static const struct panel_desc auo_t215hvn01 = {
909 .modes = &auo_t215hvn01_mode,
910 .num_modes = 1,
911 .bpc = 8,
912 .size = {
913 .width = 430,
914 .height = 270,
915 },
916 .delay = {
917 .disable = 5,
918 .unprepare = 1000,
919 },
920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
921 .connector_type = DRM_MODE_CONNECTOR_LVDS,
922};
923
924static const struct drm_display_mode avic_tm070ddh03_mode = {
925 .clock = 51200,
926 .hdisplay = 1024,
927 .hsync_start = 1024 + 160,
928 .hsync_end = 1024 + 160 + 4,
929 .htotal = 1024 + 160 + 4 + 156,
930 .vdisplay = 600,
931 .vsync_start = 600 + 17,
932 .vsync_end = 600 + 17 + 1,
933 .vtotal = 600 + 17 + 1 + 17,
934 .vrefresh = 60,
935};
936
937static const struct panel_desc avic_tm070ddh03 = {
938 .modes = &avic_tm070ddh03_mode,
939 .num_modes = 1,
940 .bpc = 8,
941 .size = {
942 .width = 154,
943 .height = 90,
944 },
945 .delay = {
946 .prepare = 20,
947 .enable = 200,
948 .disable = 200,
949 },
950};
951
952static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
953 .clock = 30000,
954 .hdisplay = 800,
955 .hsync_start = 800 + 40,
956 .hsync_end = 800 + 40 + 48,
957 .htotal = 800 + 40 + 48 + 40,
958 .vdisplay = 480,
959 .vsync_start = 480 + 13,
960 .vsync_end = 480 + 13 + 3,
961 .vtotal = 480 + 13 + 3 + 29,
962};
963
964static const struct panel_desc bananapi_s070wv20_ct16 = {
965 .modes = &bananapi_s070wv20_ct16_mode,
966 .num_modes = 1,
967 .bpc = 6,
968 .size = {
969 .width = 154,
970 .height = 86,
971 },
972};
973
974static const struct drm_display_mode boe_hv070wsa_mode = {
975 .clock = 42105,
976 .hdisplay = 1024,
977 .hsync_start = 1024 + 30,
978 .hsync_end = 1024 + 30 + 30,
979 .htotal = 1024 + 30 + 30 + 30,
980 .vdisplay = 600,
981 .vsync_start = 600 + 10,
982 .vsync_end = 600 + 10 + 10,
983 .vtotal = 600 + 10 + 10 + 10,
984 .vrefresh = 60,
985};
986
987static const struct panel_desc boe_hv070wsa = {
988 .modes = &boe_hv070wsa_mode,
989 .num_modes = 1,
990 .size = {
991 .width = 154,
992 .height = 90,
993 },
994};
995
996static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
997 {
998 .clock = 71900,
999 .hdisplay = 1280,
1000 .hsync_start = 1280 + 48,
1001 .hsync_end = 1280 + 48 + 32,
1002 .htotal = 1280 + 48 + 32 + 80,
1003 .vdisplay = 800,
1004 .vsync_start = 800 + 3,
1005 .vsync_end = 800 + 3 + 5,
1006 .vtotal = 800 + 3 + 5 + 24,
1007 .vrefresh = 60,
1008 },
1009 {
1010 .clock = 57500,
1011 .hdisplay = 1280,
1012 .hsync_start = 1280 + 48,
1013 .hsync_end = 1280 + 48 + 32,
1014 .htotal = 1280 + 48 + 32 + 80,
1015 .vdisplay = 800,
1016 .vsync_start = 800 + 3,
1017 .vsync_end = 800 + 3 + 5,
1018 .vtotal = 800 + 3 + 5 + 24,
1019 .vrefresh = 48,
1020 },
1021};
1022
1023static const struct panel_desc boe_nv101wxmn51 = {
1024 .modes = boe_nv101wxmn51_modes,
1025 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1026 .bpc = 8,
1027 .size = {
1028 .width = 217,
1029 .height = 136,
1030 },
1031 .delay = {
1032 .prepare = 210,
1033 .enable = 50,
1034 .unprepare = 160,
1035 },
1036};
1037
1038static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1039 .clock = 9000,
1040 .hdisplay = 480,
1041 .hsync_start = 480 + 5,
1042 .hsync_end = 480 + 5 + 5,
1043 .htotal = 480 + 5 + 5 + 40,
1044 .vdisplay = 272,
1045 .vsync_start = 272 + 8,
1046 .vsync_end = 272 + 8 + 8,
1047 .vtotal = 272 + 8 + 8 + 8,
1048 .vrefresh = 60,
1049 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1050};
1051
1052static const struct panel_desc cdtech_s043wq26h_ct7 = {
1053 .modes = &cdtech_s043wq26h_ct7_mode,
1054 .num_modes = 1,
1055 .bpc = 8,
1056 .size = {
1057 .width = 95,
1058 .height = 54,
1059 },
1060 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1061};
1062
1063static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1064 .clock = 35000,
1065 .hdisplay = 800,
1066 .hsync_start = 800 + 40,
1067 .hsync_end = 800 + 40 + 40,
1068 .htotal = 800 + 40 + 40 + 48,
1069 .vdisplay = 480,
1070 .vsync_start = 480 + 29,
1071 .vsync_end = 480 + 29 + 13,
1072 .vtotal = 480 + 29 + 13 + 3,
1073 .vrefresh = 60,
1074 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1075};
1076
1077static const struct panel_desc cdtech_s070wv95_ct16 = {
1078 .modes = &cdtech_s070wv95_ct16_mode,
1079 .num_modes = 1,
1080 .bpc = 8,
1081 .size = {
1082 .width = 154,
1083 .height = 85,
1084 },
1085};
1086
1087static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1088 .clock = 66770,
1089 .hdisplay = 800,
1090 .hsync_start = 800 + 49,
1091 .hsync_end = 800 + 49 + 33,
1092 .htotal = 800 + 49 + 33 + 17,
1093 .vdisplay = 1280,
1094 .vsync_start = 1280 + 1,
1095 .vsync_end = 1280 + 1 + 7,
1096 .vtotal = 1280 + 1 + 7 + 15,
1097 .vrefresh = 60,
1098 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1099};
1100
1101static const struct panel_desc chunghwa_claa070wp03xg = {
1102 .modes = &chunghwa_claa070wp03xg_mode,
1103 .num_modes = 1,
1104 .bpc = 6,
1105 .size = {
1106 .width = 94,
1107 .height = 150,
1108 },
1109};
1110
1111static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1112 .clock = 72070,
1113 .hdisplay = 1366,
1114 .hsync_start = 1366 + 58,
1115 .hsync_end = 1366 + 58 + 58,
1116 .htotal = 1366 + 58 + 58 + 58,
1117 .vdisplay = 768,
1118 .vsync_start = 768 + 4,
1119 .vsync_end = 768 + 4 + 4,
1120 .vtotal = 768 + 4 + 4 + 4,
1121 .vrefresh = 60,
1122};
1123
1124static const struct panel_desc chunghwa_claa101wa01a = {
1125 .modes = &chunghwa_claa101wa01a_mode,
1126 .num_modes = 1,
1127 .bpc = 6,
1128 .size = {
1129 .width = 220,
1130 .height = 120,
1131 },
1132};
1133
1134static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1135 .clock = 69300,
1136 .hdisplay = 1366,
1137 .hsync_start = 1366 + 48,
1138 .hsync_end = 1366 + 48 + 32,
1139 .htotal = 1366 + 48 + 32 + 20,
1140 .vdisplay = 768,
1141 .vsync_start = 768 + 16,
1142 .vsync_end = 768 + 16 + 8,
1143 .vtotal = 768 + 16 + 8 + 16,
1144 .vrefresh = 60,
1145};
1146
1147static const struct panel_desc chunghwa_claa101wb01 = {
1148 .modes = &chunghwa_claa101wb01_mode,
1149 .num_modes = 1,
1150 .bpc = 6,
1151 .size = {
1152 .width = 223,
1153 .height = 125,
1154 },
1155};
1156
1157static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1158 .clock = 33260,
1159 .hdisplay = 800,
1160 .hsync_start = 800 + 40,
1161 .hsync_end = 800 + 40 + 128,
1162 .htotal = 800 + 40 + 128 + 88,
1163 .vdisplay = 480,
1164 .vsync_start = 480 + 10,
1165 .vsync_end = 480 + 10 + 2,
1166 .vtotal = 480 + 10 + 2 + 33,
1167 .vrefresh = 60,
1168 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1169};
1170
1171static const struct panel_desc dataimage_scf0700c48ggu18 = {
1172 .modes = &dataimage_scf0700c48ggu18_mode,
1173 .num_modes = 1,
1174 .bpc = 8,
1175 .size = {
1176 .width = 152,
1177 .height = 91,
1178 },
1179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1181};
1182
1183static const struct display_timing dlc_dlc0700yzg_1_timing = {
1184 .pixelclock = { 45000000, 51200000, 57000000 },
1185 .hactive = { 1024, 1024, 1024 },
1186 .hfront_porch = { 100, 106, 113 },
1187 .hback_porch = { 100, 106, 113 },
1188 .hsync_len = { 100, 108, 114 },
1189 .vactive = { 600, 600, 600 },
1190 .vfront_porch = { 8, 11, 15 },
1191 .vback_porch = { 8, 11, 15 },
1192 .vsync_len = { 9, 13, 15 },
1193 .flags = DISPLAY_FLAGS_DE_HIGH,
1194};
1195
1196static const struct panel_desc dlc_dlc0700yzg_1 = {
1197 .timings = &dlc_dlc0700yzg_1_timing,
1198 .num_timings = 1,
1199 .bpc = 6,
1200 .size = {
1201 .width = 154,
1202 .height = 86,
1203 },
1204 .delay = {
1205 .prepare = 30,
1206 .enable = 200,
1207 .disable = 200,
1208 },
1209 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1210};
1211
1212static const struct display_timing dlc_dlc1010gig_timing = {
1213 .pixelclock = { 68900000, 71100000, 73400000 },
1214 .hactive = { 1280, 1280, 1280 },
1215 .hfront_porch = { 43, 53, 63 },
1216 .hback_porch = { 43, 53, 63 },
1217 .hsync_len = { 44, 54, 64 },
1218 .vactive = { 800, 800, 800 },
1219 .vfront_porch = { 5, 8, 11 },
1220 .vback_porch = { 5, 8, 11 },
1221 .vsync_len = { 5, 7, 11 },
1222 .flags = DISPLAY_FLAGS_DE_HIGH,
1223};
1224
1225static const struct panel_desc dlc_dlc1010gig = {
1226 .timings = &dlc_dlc1010gig_timing,
1227 .num_timings = 1,
1228 .bpc = 8,
1229 .size = {
1230 .width = 216,
1231 .height = 135,
1232 },
1233 .delay = {
1234 .prepare = 60,
1235 .enable = 150,
1236 .disable = 100,
1237 .unprepare = 60,
1238 },
1239 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1240};
1241
1242static const struct drm_display_mode edt_et035012dm6_mode = {
1243 .clock = 6500,
1244 .hdisplay = 320,
1245 .hsync_start = 320 + 20,
1246 .hsync_end = 320 + 20 + 30,
1247 .htotal = 320 + 20 + 68,
1248 .vdisplay = 240,
1249 .vsync_start = 240 + 4,
1250 .vsync_end = 240 + 4 + 4,
1251 .vtotal = 240 + 4 + 4 + 14,
1252 .vrefresh = 60,
1253 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1254};
1255
1256static const struct panel_desc edt_et035012dm6 = {
1257 .modes = &edt_et035012dm6_mode,
1258 .num_modes = 1,
1259 .bpc = 8,
1260 .size = {
1261 .width = 70,
1262 .height = 52,
1263 },
1264 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1265 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1266};
1267
1268static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1269 .clock = 9000,
1270 .hdisplay = 480,
1271 .hsync_start = 480 + 2,
1272 .hsync_end = 480 + 2 + 41,
1273 .htotal = 480 + 2 + 41 + 2,
1274 .vdisplay = 272,
1275 .vsync_start = 272 + 2,
1276 .vsync_end = 272 + 2 + 10,
1277 .vtotal = 272 + 2 + 10 + 2,
1278 .vrefresh = 60,
1279 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1280};
1281
1282static const struct panel_desc edt_etm0430g0dh6 = {
1283 .modes = &edt_etm0430g0dh6_mode,
1284 .num_modes = 1,
1285 .bpc = 6,
1286 .size = {
1287 .width = 95,
1288 .height = 54,
1289 },
1290};
1291
1292static const struct drm_display_mode edt_et057090dhu_mode = {
1293 .clock = 25175,
1294 .hdisplay = 640,
1295 .hsync_start = 640 + 16,
1296 .hsync_end = 640 + 16 + 30,
1297 .htotal = 640 + 16 + 30 + 114,
1298 .vdisplay = 480,
1299 .vsync_start = 480 + 10,
1300 .vsync_end = 480 + 10 + 3,
1301 .vtotal = 480 + 10 + 3 + 32,
1302 .vrefresh = 60,
1303 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1304};
1305
1306static const struct panel_desc edt_et057090dhu = {
1307 .modes = &edt_et057090dhu_mode,
1308 .num_modes = 1,
1309 .bpc = 6,
1310 .size = {
1311 .width = 115,
1312 .height = 86,
1313 },
1314 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1315 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1316};
1317
1318static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1319 .clock = 33260,
1320 .hdisplay = 800,
1321 .hsync_start = 800 + 40,
1322 .hsync_end = 800 + 40 + 128,
1323 .htotal = 800 + 40 + 128 + 88,
1324 .vdisplay = 480,
1325 .vsync_start = 480 + 10,
1326 .vsync_end = 480 + 10 + 2,
1327 .vtotal = 480 + 10 + 2 + 33,
1328 .vrefresh = 60,
1329 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1330};
1331
1332static const struct panel_desc edt_etm0700g0dh6 = {
1333 .modes = &edt_etm0700g0dh6_mode,
1334 .num_modes = 1,
1335 .bpc = 6,
1336 .size = {
1337 .width = 152,
1338 .height = 91,
1339 },
1340 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1341 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1342};
1343
1344static const struct panel_desc edt_etm0700g0bdh6 = {
1345 .modes = &edt_etm0700g0dh6_mode,
1346 .num_modes = 1,
1347 .bpc = 6,
1348 .size = {
1349 .width = 152,
1350 .height = 91,
1351 },
1352 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1353 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1354};
1355
1356static const struct display_timing evervision_vgg804821_timing = {
1357 .pixelclock = { 27600000, 33300000, 50000000 },
1358 .hactive = { 800, 800, 800 },
1359 .hfront_porch = { 40, 66, 70 },
1360 .hback_porch = { 40, 67, 70 },
1361 .hsync_len = { 40, 67, 70 },
1362 .vactive = { 480, 480, 480 },
1363 .vfront_porch = { 6, 10, 10 },
1364 .vback_porch = { 7, 11, 11 },
1365 .vsync_len = { 7, 11, 11 },
1366 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1367 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1368 DISPLAY_FLAGS_SYNC_NEGEDGE,
1369};
1370
1371static const struct panel_desc evervision_vgg804821 = {
1372 .timings = &evervision_vgg804821_timing,
1373 .num_timings = 1,
1374 .bpc = 8,
1375 .size = {
1376 .width = 108,
1377 .height = 64,
1378 },
1379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1380 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1381};
1382
1383static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1384 .clock = 32260,
1385 .hdisplay = 800,
1386 .hsync_start = 800 + 168,
1387 .hsync_end = 800 + 168 + 64,
1388 .htotal = 800 + 168 + 64 + 88,
1389 .vdisplay = 480,
1390 .vsync_start = 480 + 37,
1391 .vsync_end = 480 + 37 + 2,
1392 .vtotal = 480 + 37 + 2 + 8,
1393 .vrefresh = 60,
1394};
1395
1396static const struct panel_desc foxlink_fl500wvr00_a0t = {
1397 .modes = &foxlink_fl500wvr00_a0t_mode,
1398 .num_modes = 1,
1399 .bpc = 8,
1400 .size = {
1401 .width = 108,
1402 .height = 65,
1403 },
1404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1405};
1406
1407static const struct drm_display_mode friendlyarm_hd702e_mode = {
1408 .clock = 67185,
1409 .hdisplay = 800,
1410 .hsync_start = 800 + 20,
1411 .hsync_end = 800 + 20 + 24,
1412 .htotal = 800 + 20 + 24 + 20,
1413 .vdisplay = 1280,
1414 .vsync_start = 1280 + 4,
1415 .vsync_end = 1280 + 4 + 8,
1416 .vtotal = 1280 + 4 + 8 + 4,
1417 .vrefresh = 60,
1418 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1419};
1420
1421static const struct panel_desc friendlyarm_hd702e = {
1422 .modes = &friendlyarm_hd702e_mode,
1423 .num_modes = 1,
1424 .size = {
1425 .width = 94,
1426 .height = 151,
1427 },
1428};
1429
1430static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1431 .clock = 9000,
1432 .hdisplay = 480,
1433 .hsync_start = 480 + 5,
1434 .hsync_end = 480 + 5 + 1,
1435 .htotal = 480 + 5 + 1 + 40,
1436 .vdisplay = 272,
1437 .vsync_start = 272 + 8,
1438 .vsync_end = 272 + 8 + 1,
1439 .vtotal = 272 + 8 + 1 + 8,
1440 .vrefresh = 60,
1441};
1442
1443static const struct panel_desc giantplus_gpg482739qs5 = {
1444 .modes = &giantplus_gpg482739qs5_mode,
1445 .num_modes = 1,
1446 .bpc = 8,
1447 .size = {
1448 .width = 95,
1449 .height = 54,
1450 },
1451 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1452};
1453
1454static const struct display_timing giantplus_gpm940b0_timing = {
1455 .pixelclock = { 13500000, 27000000, 27500000 },
1456 .hactive = { 320, 320, 320 },
1457 .hfront_porch = { 14, 686, 718 },
1458 .hback_porch = { 50, 70, 255 },
1459 .hsync_len = { 1, 1, 1 },
1460 .vactive = { 240, 240, 240 },
1461 .vfront_porch = { 1, 1, 179 },
1462 .vback_porch = { 1, 21, 31 },
1463 .vsync_len = { 1, 1, 6 },
1464 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1465};
1466
1467static const struct panel_desc giantplus_gpm940b0 = {
1468 .timings = &giantplus_gpm940b0_timing,
1469 .num_timings = 1,
1470 .bpc = 8,
1471 .size = {
1472 .width = 60,
1473 .height = 45,
1474 },
1475 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1476 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1477};
1478
1479static const struct display_timing hannstar_hsd070pww1_timing = {
1480 .pixelclock = { 64300000, 71100000, 82000000 },
1481 .hactive = { 1280, 1280, 1280 },
1482 .hfront_porch = { 1, 1, 10 },
1483 .hback_porch = { 1, 1, 10 },
1484 /*
1485 * According to the data sheet, the minimum horizontal blanking interval
1486 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1487 * minimum working horizontal blanking interval to be 60 clocks.
1488 */
1489 .hsync_len = { 58, 158, 661 },
1490 .vactive = { 800, 800, 800 },
1491 .vfront_porch = { 1, 1, 10 },
1492 .vback_porch = { 1, 1, 10 },
1493 .vsync_len = { 1, 21, 203 },
1494 .flags = DISPLAY_FLAGS_DE_HIGH,
1495};
1496
1497static const struct panel_desc hannstar_hsd070pww1 = {
1498 .timings = &hannstar_hsd070pww1_timing,
1499 .num_timings = 1,
1500 .bpc = 6,
1501 .size = {
1502 .width = 151,
1503 .height = 94,
1504 },
1505 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1506};
1507
1508static const struct display_timing hannstar_hsd100pxn1_timing = {
1509 .pixelclock = { 55000000, 65000000, 75000000 },
1510 .hactive = { 1024, 1024, 1024 },
1511 .hfront_porch = { 40, 40, 40 },
1512 .hback_porch = { 220, 220, 220 },
1513 .hsync_len = { 20, 60, 100 },
1514 .vactive = { 768, 768, 768 },
1515 .vfront_porch = { 7, 7, 7 },
1516 .vback_porch = { 21, 21, 21 },
1517 .vsync_len = { 10, 10, 10 },
1518 .flags = DISPLAY_FLAGS_DE_HIGH,
1519};
1520
1521static const struct panel_desc hannstar_hsd100pxn1 = {
1522 .timings = &hannstar_hsd100pxn1_timing,
1523 .num_timings = 1,
1524 .bpc = 6,
1525 .size = {
1526 .width = 203,
1527 .height = 152,
1528 },
1529 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1530};
1531
1532static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1533 .clock = 33333,
1534 .hdisplay = 800,
1535 .hsync_start = 800 + 85,
1536 .hsync_end = 800 + 85 + 86,
1537 .htotal = 800 + 85 + 86 + 85,
1538 .vdisplay = 480,
1539 .vsync_start = 480 + 16,
1540 .vsync_end = 480 + 16 + 13,
1541 .vtotal = 480 + 16 + 13 + 16,
1542 .vrefresh = 60,
1543};
1544
1545static const struct panel_desc hitachi_tx23d38vm0caa = {
1546 .modes = &hitachi_tx23d38vm0caa_mode,
1547 .num_modes = 1,
1548 .bpc = 6,
1549 .size = {
1550 .width = 195,
1551 .height = 117,
1552 },
1553 .delay = {
1554 .enable = 160,
1555 .disable = 160,
1556 },
1557};
1558
1559static const struct drm_display_mode innolux_at043tn24_mode = {
1560 .clock = 9000,
1561 .hdisplay = 480,
1562 .hsync_start = 480 + 2,
1563 .hsync_end = 480 + 2 + 41,
1564 .htotal = 480 + 2 + 41 + 2,
1565 .vdisplay = 272,
1566 .vsync_start = 272 + 2,
1567 .vsync_end = 272 + 2 + 10,
1568 .vtotal = 272 + 2 + 10 + 2,
1569 .vrefresh = 60,
1570 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1571};
1572
1573static const struct panel_desc innolux_at043tn24 = {
1574 .modes = &innolux_at043tn24_mode,
1575 .num_modes = 1,
1576 .bpc = 8,
1577 .size = {
1578 .width = 95,
1579 .height = 54,
1580 },
1581 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1582 .connector_type = DRM_MODE_CONNECTOR_DPI,
1583 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1584};
1585
1586static const struct drm_display_mode innolux_at070tn92_mode = {
1587 .clock = 33333,
1588 .hdisplay = 800,
1589 .hsync_start = 800 + 210,
1590 .hsync_end = 800 + 210 + 20,
1591 .htotal = 800 + 210 + 20 + 46,
1592 .vdisplay = 480,
1593 .vsync_start = 480 + 22,
1594 .vsync_end = 480 + 22 + 10,
1595 .vtotal = 480 + 22 + 23 + 10,
1596 .vrefresh = 60,
1597};
1598
1599static const struct panel_desc innolux_at070tn92 = {
1600 .modes = &innolux_at070tn92_mode,
1601 .num_modes = 1,
1602 .size = {
1603 .width = 154,
1604 .height = 86,
1605 },
1606 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1607};
1608
1609static const struct display_timing innolux_g070y2_l01_timing = {
1610 .pixelclock = { 28000000, 29500000, 32000000 },
1611 .hactive = { 800, 800, 800 },
1612 .hfront_porch = { 61, 91, 141 },
1613 .hback_porch = { 60, 90, 140 },
1614 .hsync_len = { 12, 12, 12 },
1615 .vactive = { 480, 480, 480 },
1616 .vfront_porch = { 4, 9, 30 },
1617 .vback_porch = { 4, 8, 28 },
1618 .vsync_len = { 2, 2, 2 },
1619 .flags = DISPLAY_FLAGS_DE_HIGH,
1620};
1621
1622static const struct panel_desc innolux_g070y2_l01 = {
1623 .timings = &innolux_g070y2_l01_timing,
1624 .num_timings = 1,
1625 .bpc = 6,
1626 .size = {
1627 .width = 152,
1628 .height = 91,
1629 },
1630 .delay = {
1631 .prepare = 10,
1632 .enable = 100,
1633 .disable = 100,
1634 .unprepare = 800,
1635 },
1636 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1637};
1638
1639static const struct display_timing innolux_g101ice_l01_timing = {
1640 .pixelclock = { 60400000, 71100000, 74700000 },
1641 .hactive = { 1280, 1280, 1280 },
1642 .hfront_porch = { 30, 60, 70 },
1643 .hback_porch = { 30, 60, 70 },
1644 .hsync_len = { 22, 40, 60 },
1645 .vactive = { 800, 800, 800 },
1646 .vfront_porch = { 3, 8, 14 },
1647 .vback_porch = { 3, 8, 14 },
1648 .vsync_len = { 4, 7, 12 },
1649 .flags = DISPLAY_FLAGS_DE_HIGH,
1650};
1651
1652static const struct panel_desc innolux_g101ice_l01 = {
1653 .timings = &innolux_g101ice_l01_timing,
1654 .num_timings = 1,
1655 .bpc = 8,
1656 .size = {
1657 .width = 217,
1658 .height = 135,
1659 },
1660 .delay = {
1661 .enable = 200,
1662 .disable = 200,
1663 },
1664 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1665};
1666
1667static const struct display_timing innolux_g121i1_l01_timing = {
1668 .pixelclock = { 67450000, 71000000, 74550000 },
1669 .hactive = { 1280, 1280, 1280 },
1670 .hfront_porch = { 40, 80, 160 },
1671 .hback_porch = { 39, 79, 159 },
1672 .hsync_len = { 1, 1, 1 },
1673 .vactive = { 800, 800, 800 },
1674 .vfront_porch = { 5, 11, 100 },
1675 .vback_porch = { 4, 11, 99 },
1676 .vsync_len = { 1, 1, 1 },
1677};
1678
1679static const struct panel_desc innolux_g121i1_l01 = {
1680 .timings = &innolux_g121i1_l01_timing,
1681 .num_timings = 1,
1682 .bpc = 6,
1683 .size = {
1684 .width = 261,
1685 .height = 163,
1686 },
1687 .delay = {
1688 .enable = 200,
1689 .disable = 20,
1690 },
1691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1692};
1693
1694static const struct drm_display_mode innolux_g121x1_l03_mode = {
1695 .clock = 65000,
1696 .hdisplay = 1024,
1697 .hsync_start = 1024 + 0,
1698 .hsync_end = 1024 + 1,
1699 .htotal = 1024 + 0 + 1 + 320,
1700 .vdisplay = 768,
1701 .vsync_start = 768 + 38,
1702 .vsync_end = 768 + 38 + 1,
1703 .vtotal = 768 + 38 + 1 + 0,
1704 .vrefresh = 60,
1705 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1706};
1707
1708static const struct panel_desc innolux_g121x1_l03 = {
1709 .modes = &innolux_g121x1_l03_mode,
1710 .num_modes = 1,
1711 .bpc = 6,
1712 .size = {
1713 .width = 246,
1714 .height = 185,
1715 },
1716 .delay = {
1717 .enable = 200,
1718 .unprepare = 200,
1719 .disable = 400,
1720 },
1721 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1722 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1723 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1724};
1725
1726/*
1727 * Datasheet specifies that at 60 Hz refresh rate:
1728 * - total horizontal time: { 1506, 1592, 1716 }
1729 * - total vertical time: { 788, 800, 868 }
1730 *
1731 * ...but doesn't go into exactly how that should be split into a front
1732 * porch, back porch, or sync length. For now we'll leave a single setting
1733 * here which allows a bit of tweaking of the pixel clock at the expense of
1734 * refresh rate.
1735 */
1736static const struct display_timing innolux_n116bge_timing = {
1737 .pixelclock = { 72600000, 76420000, 80240000 },
1738 .hactive = { 1366, 1366, 1366 },
1739 .hfront_porch = { 136, 136, 136 },
1740 .hback_porch = { 60, 60, 60 },
1741 .hsync_len = { 30, 30, 30 },
1742 .vactive = { 768, 768, 768 },
1743 .vfront_porch = { 8, 8, 8 },
1744 .vback_porch = { 12, 12, 12 },
1745 .vsync_len = { 12, 12, 12 },
1746 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1747};
1748
1749static const struct panel_desc innolux_n116bge = {
1750 .timings = &innolux_n116bge_timing,
1751 .num_timings = 1,
1752 .bpc = 6,
1753 .size = {
1754 .width = 256,
1755 .height = 144,
1756 },
1757};
1758
1759static const struct drm_display_mode innolux_n156bge_l21_mode = {
1760 .clock = 69300,
1761 .hdisplay = 1366,
1762 .hsync_start = 1366 + 16,
1763 .hsync_end = 1366 + 16 + 34,
1764 .htotal = 1366 + 16 + 34 + 50,
1765 .vdisplay = 768,
1766 .vsync_start = 768 + 2,
1767 .vsync_end = 768 + 2 + 6,
1768 .vtotal = 768 + 2 + 6 + 12,
1769 .vrefresh = 60,
1770};
1771
1772static const struct panel_desc innolux_n156bge_l21 = {
1773 .modes = &innolux_n156bge_l21_mode,
1774 .num_modes = 1,
1775 .bpc = 6,
1776 .size = {
1777 .width = 344,
1778 .height = 193,
1779 },
1780};
1781
1782static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1783 .clock = 206016,
1784 .hdisplay = 2160,
1785 .hsync_start = 2160 + 48,
1786 .hsync_end = 2160 + 48 + 32,
1787 .htotal = 2160 + 48 + 32 + 80,
1788 .vdisplay = 1440,
1789 .vsync_start = 1440 + 3,
1790 .vsync_end = 1440 + 3 + 10,
1791 .vtotal = 1440 + 3 + 10 + 27,
1792 .vrefresh = 60,
1793 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1794};
1795
1796static const struct panel_desc innolux_p120zdg_bf1 = {
1797 .modes = &innolux_p120zdg_bf1_mode,
1798 .num_modes = 1,
1799 .bpc = 8,
1800 .size = {
1801 .width = 254,
1802 .height = 169,
1803 },
1804 .delay = {
1805 .hpd_absent_delay = 200,
1806 .unprepare = 500,
1807 },
1808};
1809
1810static const struct drm_display_mode innolux_zj070na_01p_mode = {
1811 .clock = 51501,
1812 .hdisplay = 1024,
1813 .hsync_start = 1024 + 128,
1814 .hsync_end = 1024 + 128 + 64,
1815 .htotal = 1024 + 128 + 64 + 128,
1816 .vdisplay = 600,
1817 .vsync_start = 600 + 16,
1818 .vsync_end = 600 + 16 + 4,
1819 .vtotal = 600 + 16 + 4 + 16,
1820 .vrefresh = 60,
1821};
1822
1823static const struct panel_desc innolux_zj070na_01p = {
1824 .modes = &innolux_zj070na_01p_mode,
1825 .num_modes = 1,
1826 .bpc = 6,
1827 .size = {
1828 .width = 154,
1829 .height = 90,
1830 },
1831};
1832
1833static const struct display_timing koe_tx14d24vm1bpa_timing = {
1834 .pixelclock = { 5580000, 5850000, 6200000 },
1835 .hactive = { 320, 320, 320 },
1836 .hfront_porch = { 30, 30, 30 },
1837 .hback_porch = { 30, 30, 30 },
1838 .hsync_len = { 1, 5, 17 },
1839 .vactive = { 240, 240, 240 },
1840 .vfront_porch = { 6, 6, 6 },
1841 .vback_porch = { 5, 5, 5 },
1842 .vsync_len = { 1, 2, 11 },
1843 .flags = DISPLAY_FLAGS_DE_HIGH,
1844};
1845
1846static const struct panel_desc koe_tx14d24vm1bpa = {
1847 .timings = &koe_tx14d24vm1bpa_timing,
1848 .num_timings = 1,
1849 .bpc = 6,
1850 .size = {
1851 .width = 115,
1852 .height = 86,
1853 },
1854};
1855
1856static const struct display_timing koe_tx31d200vm0baa_timing = {
1857 .pixelclock = { 39600000, 43200000, 48000000 },
1858 .hactive = { 1280, 1280, 1280 },
1859 .hfront_porch = { 16, 36, 56 },
1860 .hback_porch = { 16, 36, 56 },
1861 .hsync_len = { 8, 8, 8 },
1862 .vactive = { 480, 480, 480 },
1863 .vfront_porch = { 6, 21, 33 },
1864 .vback_porch = { 6, 21, 33 },
1865 .vsync_len = { 8, 8, 8 },
1866 .flags = DISPLAY_FLAGS_DE_HIGH,
1867};
1868
1869static const struct panel_desc koe_tx31d200vm0baa = {
1870 .timings = &koe_tx31d200vm0baa_timing,
1871 .num_timings = 1,
1872 .bpc = 6,
1873 .size = {
1874 .width = 292,
1875 .height = 109,
1876 },
1877 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1878};
1879
1880static const struct display_timing kyo_tcg121xglp_timing = {
1881 .pixelclock = { 52000000, 65000000, 71000000 },
1882 .hactive = { 1024, 1024, 1024 },
1883 .hfront_porch = { 2, 2, 2 },
1884 .hback_porch = { 2, 2, 2 },
1885 .hsync_len = { 86, 124, 244 },
1886 .vactive = { 768, 768, 768 },
1887 .vfront_porch = { 2, 2, 2 },
1888 .vback_porch = { 2, 2, 2 },
1889 .vsync_len = { 6, 34, 73 },
1890 .flags = DISPLAY_FLAGS_DE_HIGH,
1891};
1892
1893static const struct panel_desc kyo_tcg121xglp = {
1894 .timings = &kyo_tcg121xglp_timing,
1895 .num_timings = 1,
1896 .bpc = 8,
1897 .size = {
1898 .width = 246,
1899 .height = 184,
1900 },
1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1902};
1903
1904static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1905 .clock = 7000,
1906 .hdisplay = 320,
1907 .hsync_start = 320 + 20,
1908 .hsync_end = 320 + 20 + 30,
1909 .htotal = 320 + 20 + 30 + 38,
1910 .vdisplay = 240,
1911 .vsync_start = 240 + 4,
1912 .vsync_end = 240 + 4 + 3,
1913 .vtotal = 240 + 4 + 3 + 15,
1914 .vrefresh = 60,
1915};
1916
1917static const struct panel_desc lemaker_bl035_rgb_002 = {
1918 .modes = &lemaker_bl035_rgb_002_mode,
1919 .num_modes = 1,
1920 .size = {
1921 .width = 70,
1922 .height = 52,
1923 },
1924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1925 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1926};
1927
1928static const struct drm_display_mode lg_lb070wv8_mode = {
1929 .clock = 33246,
1930 .hdisplay = 800,
1931 .hsync_start = 800 + 88,
1932 .hsync_end = 800 + 88 + 80,
1933 .htotal = 800 + 88 + 80 + 88,
1934 .vdisplay = 480,
1935 .vsync_start = 480 + 10,
1936 .vsync_end = 480 + 10 + 25,
1937 .vtotal = 480 + 10 + 25 + 10,
1938 .vrefresh = 60,
1939};
1940
1941static const struct panel_desc lg_lb070wv8 = {
1942 .modes = &lg_lb070wv8_mode,
1943 .num_modes = 1,
1944 .bpc = 8,
1945 .size = {
1946 .width = 151,
1947 .height = 91,
1948 },
1949 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1950};
1951
1952static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1953 .clock = 200000,
1954 .hdisplay = 1536,
1955 .hsync_start = 1536 + 12,
1956 .hsync_end = 1536 + 12 + 16,
1957 .htotal = 1536 + 12 + 16 + 48,
1958 .vdisplay = 2048,
1959 .vsync_start = 2048 + 8,
1960 .vsync_end = 2048 + 8 + 4,
1961 .vtotal = 2048 + 8 + 4 + 8,
1962 .vrefresh = 60,
1963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1964};
1965
1966static const struct panel_desc lg_lp079qx1_sp0v = {
1967 .modes = &lg_lp079qx1_sp0v_mode,
1968 .num_modes = 1,
1969 .size = {
1970 .width = 129,
1971 .height = 171,
1972 },
1973};
1974
1975static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1976 .clock = 205210,
1977 .hdisplay = 2048,
1978 .hsync_start = 2048 + 150,
1979 .hsync_end = 2048 + 150 + 5,
1980 .htotal = 2048 + 150 + 5 + 5,
1981 .vdisplay = 1536,
1982 .vsync_start = 1536 + 3,
1983 .vsync_end = 1536 + 3 + 1,
1984 .vtotal = 1536 + 3 + 1 + 9,
1985 .vrefresh = 60,
1986};
1987
1988static const struct panel_desc lg_lp097qx1_spa1 = {
1989 .modes = &lg_lp097qx1_spa1_mode,
1990 .num_modes = 1,
1991 .size = {
1992 .width = 208,
1993 .height = 147,
1994 },
1995};
1996
1997static const struct drm_display_mode lg_lp120up1_mode = {
1998 .clock = 162300,
1999 .hdisplay = 1920,
2000 .hsync_start = 1920 + 40,
2001 .hsync_end = 1920 + 40 + 40,
2002 .htotal = 1920 + 40 + 40+ 80,
2003 .vdisplay = 1280,
2004 .vsync_start = 1280 + 4,
2005 .vsync_end = 1280 + 4 + 4,
2006 .vtotal = 1280 + 4 + 4 + 12,
2007 .vrefresh = 60,
2008};
2009
2010static const struct panel_desc lg_lp120up1 = {
2011 .modes = &lg_lp120up1_mode,
2012 .num_modes = 1,
2013 .bpc = 8,
2014 .size = {
2015 .width = 267,
2016 .height = 183,
2017 },
2018};
2019
2020static const struct drm_display_mode lg_lp129qe_mode = {
2021 .clock = 285250,
2022 .hdisplay = 2560,
2023 .hsync_start = 2560 + 48,
2024 .hsync_end = 2560 + 48 + 32,
2025 .htotal = 2560 + 48 + 32 + 80,
2026 .vdisplay = 1700,
2027 .vsync_start = 1700 + 3,
2028 .vsync_end = 1700 + 3 + 10,
2029 .vtotal = 1700 + 3 + 10 + 36,
2030 .vrefresh = 60,
2031};
2032
2033static const struct panel_desc lg_lp129qe = {
2034 .modes = &lg_lp129qe_mode,
2035 .num_modes = 1,
2036 .bpc = 8,
2037 .size = {
2038 .width = 272,
2039 .height = 181,
2040 },
2041};
2042
2043static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2044 .clock = 30400,
2045 .hdisplay = 800,
2046 .hsync_start = 800 + 0,
2047 .hsync_end = 800 + 1,
2048 .htotal = 800 + 0 + 1 + 160,
2049 .vdisplay = 480,
2050 .vsync_start = 480 + 0,
2051 .vsync_end = 480 + 48 + 1,
2052 .vtotal = 480 + 48 + 1 + 0,
2053 .vrefresh = 60,
2054 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2055};
2056
2057static const struct drm_display_mode logicpd_type_28_mode = {
2058 .clock = 9000,
2059 .hdisplay = 480,
2060 .hsync_start = 480 + 3,
2061 .hsync_end = 480 + 3 + 42,
2062 .htotal = 480 + 3 + 42 + 2,
2063
2064 .vdisplay = 272,
2065 .vsync_start = 272 + 2,
2066 .vsync_end = 272 + 2 + 11,
2067 .vtotal = 272 + 2 + 11 + 3,
2068 .vrefresh = 60,
2069 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2070};
2071
2072static const struct panel_desc logicpd_type_28 = {
2073 .modes = &logicpd_type_28_mode,
2074 .num_modes = 1,
2075 .bpc = 8,
2076 .size = {
2077 .width = 105,
2078 .height = 67,
2079 },
2080 .delay = {
2081 .prepare = 200,
2082 .enable = 200,
2083 .unprepare = 200,
2084 .disable = 200,
2085 },
2086 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2088 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2089};
2090
2091static const struct panel_desc mitsubishi_aa070mc01 = {
2092 .modes = &mitsubishi_aa070mc01_mode,
2093 .num_modes = 1,
2094 .bpc = 8,
2095 .size = {
2096 .width = 152,
2097 .height = 91,
2098 },
2099
2100 .delay = {
2101 .enable = 200,
2102 .unprepare = 200,
2103 .disable = 400,
2104 },
2105 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2106 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2107};
2108
2109static const struct display_timing nec_nl12880bc20_05_timing = {
2110 .pixelclock = { 67000000, 71000000, 75000000 },
2111 .hactive = { 1280, 1280, 1280 },
2112 .hfront_porch = { 2, 30, 30 },
2113 .hback_porch = { 6, 100, 100 },
2114 .hsync_len = { 2, 30, 30 },
2115 .vactive = { 800, 800, 800 },
2116 .vfront_porch = { 5, 5, 5 },
2117 .vback_porch = { 11, 11, 11 },
2118 .vsync_len = { 7, 7, 7 },
2119};
2120
2121static const struct panel_desc nec_nl12880bc20_05 = {
2122 .timings = &nec_nl12880bc20_05_timing,
2123 .num_timings = 1,
2124 .bpc = 8,
2125 .size = {
2126 .width = 261,
2127 .height = 163,
2128 },
2129 .delay = {
2130 .enable = 50,
2131 .disable = 50,
2132 },
2133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2134};
2135
2136static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2137 .clock = 10870,
2138 .hdisplay = 480,
2139 .hsync_start = 480 + 2,
2140 .hsync_end = 480 + 2 + 41,
2141 .htotal = 480 + 2 + 41 + 2,
2142 .vdisplay = 272,
2143 .vsync_start = 272 + 2,
2144 .vsync_end = 272 + 2 + 4,
2145 .vtotal = 272 + 2 + 4 + 2,
2146 .vrefresh = 74,
2147 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2148};
2149
2150static const struct panel_desc nec_nl4827hc19_05b = {
2151 .modes = &nec_nl4827hc19_05b_mode,
2152 .num_modes = 1,
2153 .bpc = 8,
2154 .size = {
2155 .width = 95,
2156 .height = 54,
2157 },
2158 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2159 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2160};
2161
2162static const struct drm_display_mode netron_dy_e231732_mode = {
2163 .clock = 66000,
2164 .hdisplay = 1024,
2165 .hsync_start = 1024 + 160,
2166 .hsync_end = 1024 + 160 + 70,
2167 .htotal = 1024 + 160 + 70 + 90,
2168 .vdisplay = 600,
2169 .vsync_start = 600 + 127,
2170 .vsync_end = 600 + 127 + 20,
2171 .vtotal = 600 + 127 + 20 + 3,
2172 .vrefresh = 60,
2173};
2174
2175static const struct panel_desc netron_dy_e231732 = {
2176 .modes = &netron_dy_e231732_mode,
2177 .num_modes = 1,
2178 .size = {
2179 .width = 154,
2180 .height = 87,
2181 },
2182 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2183};
2184
2185static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2186 .clock = 9000,
2187 .hdisplay = 480,
2188 .hsync_start = 480 + 2,
2189 .hsync_end = 480 + 2 + 41,
2190 .htotal = 480 + 2 + 41 + 2,
2191 .vdisplay = 272,
2192 .vsync_start = 272 + 2,
2193 .vsync_end = 272 + 2 + 10,
2194 .vtotal = 272 + 2 + 10 + 2,
2195 .vrefresh = 60,
2196 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2197};
2198
2199static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2200 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2201 .num_modes = 1,
2202 .bpc = 8,
2203 .size = {
2204 .width = 95,
2205 .height = 54,
2206 },
2207 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2209 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2210};
2211
2212static const struct display_timing nlt_nl192108ac18_02d_timing = {
2213 .pixelclock = { 130000000, 148350000, 163000000 },
2214 .hactive = { 1920, 1920, 1920 },
2215 .hfront_porch = { 80, 100, 100 },
2216 .hback_porch = { 100, 120, 120 },
2217 .hsync_len = { 50, 60, 60 },
2218 .vactive = { 1080, 1080, 1080 },
2219 .vfront_porch = { 12, 30, 30 },
2220 .vback_porch = { 4, 10, 10 },
2221 .vsync_len = { 4, 5, 5 },
2222};
2223
2224static const struct panel_desc nlt_nl192108ac18_02d = {
2225 .timings = &nlt_nl192108ac18_02d_timing,
2226 .num_timings = 1,
2227 .bpc = 8,
2228 .size = {
2229 .width = 344,
2230 .height = 194,
2231 },
2232 .delay = {
2233 .unprepare = 500,
2234 },
2235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2236};
2237
2238static const struct drm_display_mode nvd_9128_mode = {
2239 .clock = 29500,
2240 .hdisplay = 800,
2241 .hsync_start = 800 + 130,
2242 .hsync_end = 800 + 130 + 98,
2243 .htotal = 800 + 0 + 130 + 98,
2244 .vdisplay = 480,
2245 .vsync_start = 480 + 10,
2246 .vsync_end = 480 + 10 + 50,
2247 .vtotal = 480 + 0 + 10 + 50,
2248};
2249
2250static const struct panel_desc nvd_9128 = {
2251 .modes = &nvd_9128_mode,
2252 .num_modes = 1,
2253 .bpc = 8,
2254 .size = {
2255 .width = 156,
2256 .height = 88,
2257 },
2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2259};
2260
2261static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2262 .pixelclock = { 30000000, 30000000, 40000000 },
2263 .hactive = { 800, 800, 800 },
2264 .hfront_porch = { 40, 40, 40 },
2265 .hback_porch = { 40, 40, 40 },
2266 .hsync_len = { 1, 48, 48 },
2267 .vactive = { 480, 480, 480 },
2268 .vfront_porch = { 13, 13, 13 },
2269 .vback_porch = { 29, 29, 29 },
2270 .vsync_len = { 3, 3, 3 },
2271 .flags = DISPLAY_FLAGS_DE_HIGH,
2272};
2273
2274static const struct panel_desc okaya_rs800480t_7x0gp = {
2275 .timings = &okaya_rs800480t_7x0gp_timing,
2276 .num_timings = 1,
2277 .bpc = 6,
2278 .size = {
2279 .width = 154,
2280 .height = 87,
2281 },
2282 .delay = {
2283 .prepare = 41,
2284 .enable = 50,
2285 .unprepare = 41,
2286 .disable = 50,
2287 },
2288 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2289};
2290
2291static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2292 .clock = 9000,
2293 .hdisplay = 480,
2294 .hsync_start = 480 + 5,
2295 .hsync_end = 480 + 5 + 30,
2296 .htotal = 480 + 5 + 30 + 10,
2297 .vdisplay = 272,
2298 .vsync_start = 272 + 8,
2299 .vsync_end = 272 + 8 + 5,
2300 .vtotal = 272 + 8 + 5 + 3,
2301 .vrefresh = 60,
2302};
2303
2304static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2305 .modes = &olimex_lcd_olinuxino_43ts_mode,
2306 .num_modes = 1,
2307 .size = {
2308 .width = 95,
2309 .height = 54,
2310 },
2311 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2312};
2313
2314/*
2315 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2316 * pixel clocks, but this is the timing that was being used in the Adafruit
2317 * installation instructions.
2318 */
2319static const struct drm_display_mode ontat_yx700wv03_mode = {
2320 .clock = 29500,
2321 .hdisplay = 800,
2322 .hsync_start = 824,
2323 .hsync_end = 896,
2324 .htotal = 992,
2325 .vdisplay = 480,
2326 .vsync_start = 483,
2327 .vsync_end = 493,
2328 .vtotal = 500,
2329 .vrefresh = 60,
2330 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2331};
2332
2333/*
2334 * Specification at:
2335 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2336 */
2337static const struct panel_desc ontat_yx700wv03 = {
2338 .modes = &ontat_yx700wv03_mode,
2339 .num_modes = 1,
2340 .bpc = 8,
2341 .size = {
2342 .width = 154,
2343 .height = 83,
2344 },
2345 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2346};
2347
2348static const struct drm_display_mode ortustech_com37h3m_mode = {
2349 .clock = 22153,
2350 .hdisplay = 480,
2351 .hsync_start = 480 + 8,
2352 .hsync_end = 480 + 8 + 10,
2353 .htotal = 480 + 8 + 10 + 10,
2354 .vdisplay = 640,
2355 .vsync_start = 640 + 4,
2356 .vsync_end = 640 + 4 + 3,
2357 .vtotal = 640 + 4 + 3 + 4,
2358 .vrefresh = 60,
2359 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2360};
2361
2362static const struct panel_desc ortustech_com37h3m = {
2363 .modes = &ortustech_com37h3m_mode,
2364 .num_modes = 1,
2365 .bpc = 8,
2366 .size = {
2367 .width = 56, /* 56.16mm */
2368 .height = 75, /* 74.88mm */
2369 },
2370 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2371 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2372 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2373};
2374
2375static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2376 .clock = 25000,
2377 .hdisplay = 480,
2378 .hsync_start = 480 + 10,
2379 .hsync_end = 480 + 10 + 10,
2380 .htotal = 480 + 10 + 10 + 15,
2381 .vdisplay = 800,
2382 .vsync_start = 800 + 3,
2383 .vsync_end = 800 + 3 + 3,
2384 .vtotal = 800 + 3 + 3 + 3,
2385 .vrefresh = 60,
2386};
2387
2388static const struct panel_desc ortustech_com43h4m85ulc = {
2389 .modes = &ortustech_com43h4m85ulc_mode,
2390 .num_modes = 1,
2391 .bpc = 6,
2392 .size = {
2393 .width = 56,
2394 .height = 93,
2395 },
2396 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2397 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2398};
2399
2400static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2401 .clock = 33000,
2402 .hdisplay = 800,
2403 .hsync_start = 800 + 210,
2404 .hsync_end = 800 + 210 + 30,
2405 .htotal = 800 + 210 + 30 + 16,
2406 .vdisplay = 480,
2407 .vsync_start = 480 + 22,
2408 .vsync_end = 480 + 22 + 13,
2409 .vtotal = 480 + 22 + 13 + 10,
2410 .vrefresh = 60,
2411 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2412};
2413
2414static const struct panel_desc osddisplays_osd070t1718_19ts = {
2415 .modes = &osddisplays_osd070t1718_19ts_mode,
2416 .num_modes = 1,
2417 .bpc = 8,
2418 .size = {
2419 .width = 152,
2420 .height = 91,
2421 },
2422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2423 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2424};
2425
2426static const struct drm_display_mode pda_91_00156_a0_mode = {
2427 .clock = 33300,
2428 .hdisplay = 800,
2429 .hsync_start = 800 + 1,
2430 .hsync_end = 800 + 1 + 64,
2431 .htotal = 800 + 1 + 64 + 64,
2432 .vdisplay = 480,
2433 .vsync_start = 480 + 1,
2434 .vsync_end = 480 + 1 + 23,
2435 .vtotal = 480 + 1 + 23 + 22,
2436 .vrefresh = 60,
2437};
2438
2439static const struct panel_desc pda_91_00156_a0 = {
2440 .modes = &pda_91_00156_a0_mode,
2441 .num_modes = 1,
2442 .size = {
2443 .width = 152,
2444 .height = 91,
2445 },
2446 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2447};
2448
2449
2450static const struct drm_display_mode qd43003c0_40_mode = {
2451 .clock = 9000,
2452 .hdisplay = 480,
2453 .hsync_start = 480 + 8,
2454 .hsync_end = 480 + 8 + 4,
2455 .htotal = 480 + 8 + 4 + 39,
2456 .vdisplay = 272,
2457 .vsync_start = 272 + 4,
2458 .vsync_end = 272 + 4 + 10,
2459 .vtotal = 272 + 4 + 10 + 2,
2460 .vrefresh = 60,
2461};
2462
2463static const struct panel_desc qd43003c0_40 = {
2464 .modes = &qd43003c0_40_mode,
2465 .num_modes = 1,
2466 .bpc = 8,
2467 .size = {
2468 .width = 95,
2469 .height = 53,
2470 },
2471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2472};
2473
2474static const struct display_timing rocktech_rk070er9427_timing = {
2475 .pixelclock = { 26400000, 33300000, 46800000 },
2476 .hactive = { 800, 800, 800 },
2477 .hfront_porch = { 16, 210, 354 },
2478 .hback_porch = { 46, 46, 46 },
2479 .hsync_len = { 1, 1, 1 },
2480 .vactive = { 480, 480, 480 },
2481 .vfront_porch = { 7, 22, 147 },
2482 .vback_porch = { 23, 23, 23 },
2483 .vsync_len = { 1, 1, 1 },
2484 .flags = DISPLAY_FLAGS_DE_HIGH,
2485};
2486
2487static const struct panel_desc rocktech_rk070er9427 = {
2488 .timings = &rocktech_rk070er9427_timing,
2489 .num_timings = 1,
2490 .bpc = 6,
2491 .size = {
2492 .width = 154,
2493 .height = 86,
2494 },
2495 .delay = {
2496 .prepare = 41,
2497 .enable = 50,
2498 .unprepare = 41,
2499 .disable = 50,
2500 },
2501 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2502};
2503
2504static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2505 .clock = 271560,
2506 .hdisplay = 2560,
2507 .hsync_start = 2560 + 48,
2508 .hsync_end = 2560 + 48 + 32,
2509 .htotal = 2560 + 48 + 32 + 80,
2510 .vdisplay = 1600,
2511 .vsync_start = 1600 + 2,
2512 .vsync_end = 1600 + 2 + 5,
2513 .vtotal = 1600 + 2 + 5 + 57,
2514 .vrefresh = 60,
2515};
2516
2517static const struct panel_desc samsung_lsn122dl01_c01 = {
2518 .modes = &samsung_lsn122dl01_c01_mode,
2519 .num_modes = 1,
2520 .size = {
2521 .width = 263,
2522 .height = 164,
2523 },
2524};
2525
2526static const struct drm_display_mode samsung_ltn101nt05_mode = {
2527 .clock = 54030,
2528 .hdisplay = 1024,
2529 .hsync_start = 1024 + 24,
2530 .hsync_end = 1024 + 24 + 136,
2531 .htotal = 1024 + 24 + 136 + 160,
2532 .vdisplay = 600,
2533 .vsync_start = 600 + 3,
2534 .vsync_end = 600 + 3 + 6,
2535 .vtotal = 600 + 3 + 6 + 61,
2536 .vrefresh = 60,
2537};
2538
2539static const struct panel_desc samsung_ltn101nt05 = {
2540 .modes = &samsung_ltn101nt05_mode,
2541 .num_modes = 1,
2542 .bpc = 6,
2543 .size = {
2544 .width = 223,
2545 .height = 125,
2546 },
2547};
2548
2549static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2550 .clock = 76300,
2551 .hdisplay = 1366,
2552 .hsync_start = 1366 + 64,
2553 .hsync_end = 1366 + 64 + 48,
2554 .htotal = 1366 + 64 + 48 + 128,
2555 .vdisplay = 768,
2556 .vsync_start = 768 + 2,
2557 .vsync_end = 768 + 2 + 5,
2558 .vtotal = 768 + 2 + 5 + 17,
2559 .vrefresh = 60,
2560};
2561
2562static const struct panel_desc samsung_ltn140at29_301 = {
2563 .modes = &samsung_ltn140at29_301_mode,
2564 .num_modes = 1,
2565 .bpc = 6,
2566 .size = {
2567 .width = 320,
2568 .height = 187,
2569 },
2570};
2571
2572static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2573 .clock = 168480,
2574 .hdisplay = 1920,
2575 .hsync_start = 1920 + 48,
2576 .hsync_end = 1920 + 48 + 32,
2577 .htotal = 1920 + 48 + 32 + 80,
2578 .vdisplay = 1280,
2579 .vsync_start = 1280 + 3,
2580 .vsync_end = 1280 + 3 + 10,
2581 .vtotal = 1280 + 3 + 10 + 57,
2582 .vrefresh = 60,
2583 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2584};
2585
2586static const struct panel_desc sharp_ld_d5116z01b = {
2587 .modes = &sharp_ld_d5116z01b_mode,
2588 .num_modes = 1,
2589 .bpc = 8,
2590 .size = {
2591 .width = 260,
2592 .height = 120,
2593 },
2594 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2595 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2596};
2597
2598static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2599 .clock = 33260,
2600 .hdisplay = 800,
2601 .hsync_start = 800 + 64,
2602 .hsync_end = 800 + 64 + 128,
2603 .htotal = 800 + 64 + 128 + 64,
2604 .vdisplay = 480,
2605 .vsync_start = 480 + 8,
2606 .vsync_end = 480 + 8 + 2,
2607 .vtotal = 480 + 8 + 2 + 35,
2608 .vrefresh = 60,
2609 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2610};
2611
2612static const struct panel_desc sharp_lq070y3dg3b = {
2613 .modes = &sharp_lq070y3dg3b_mode,
2614 .num_modes = 1,
2615 .bpc = 8,
2616 .size = {
2617 .width = 152, /* 152.4mm */
2618 .height = 91, /* 91.4mm */
2619 },
2620 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2621 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2622 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2623};
2624
2625static const struct drm_display_mode sharp_lq035q7db03_mode = {
2626 .clock = 5500,
2627 .hdisplay = 240,
2628 .hsync_start = 240 + 16,
2629 .hsync_end = 240 + 16 + 7,
2630 .htotal = 240 + 16 + 7 + 5,
2631 .vdisplay = 320,
2632 .vsync_start = 320 + 9,
2633 .vsync_end = 320 + 9 + 1,
2634 .vtotal = 320 + 9 + 1 + 7,
2635 .vrefresh = 60,
2636};
2637
2638static const struct panel_desc sharp_lq035q7db03 = {
2639 .modes = &sharp_lq035q7db03_mode,
2640 .num_modes = 1,
2641 .bpc = 6,
2642 .size = {
2643 .width = 54,
2644 .height = 72,
2645 },
2646 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2647};
2648
2649static const struct display_timing sharp_lq101k1ly04_timing = {
2650 .pixelclock = { 60000000, 65000000, 80000000 },
2651 .hactive = { 1280, 1280, 1280 },
2652 .hfront_porch = { 20, 20, 20 },
2653 .hback_porch = { 20, 20, 20 },
2654 .hsync_len = { 10, 10, 10 },
2655 .vactive = { 800, 800, 800 },
2656 .vfront_porch = { 4, 4, 4 },
2657 .vback_porch = { 4, 4, 4 },
2658 .vsync_len = { 4, 4, 4 },
2659 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2660};
2661
2662static const struct panel_desc sharp_lq101k1ly04 = {
2663 .timings = &sharp_lq101k1ly04_timing,
2664 .num_timings = 1,
2665 .bpc = 8,
2666 .size = {
2667 .width = 217,
2668 .height = 136,
2669 },
2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2671};
2672
2673static const struct display_timing sharp_lq123p1jx31_timing = {
2674 .pixelclock = { 252750000, 252750000, 266604720 },
2675 .hactive = { 2400, 2400, 2400 },
2676 .hfront_porch = { 48, 48, 48 },
2677 .hback_porch = { 80, 80, 84 },
2678 .hsync_len = { 32, 32, 32 },
2679 .vactive = { 1600, 1600, 1600 },
2680 .vfront_porch = { 3, 3, 3 },
2681 .vback_porch = { 33, 33, 120 },
2682 .vsync_len = { 10, 10, 10 },
2683 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2684};
2685
2686static const struct panel_desc sharp_lq123p1jx31 = {
2687 .timings = &sharp_lq123p1jx31_timing,
2688 .num_timings = 1,
2689 .bpc = 8,
2690 .size = {
2691 .width = 259,
2692 .height = 173,
2693 },
2694 .delay = {
2695 .prepare = 110,
2696 .enable = 50,
2697 .unprepare = 550,
2698 },
2699};
2700
2701static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2702 .clock = 71100,
2703 .hdisplay = 1024,
2704 .hsync_start = 1024 + 168,
2705 .hsync_end = 1024 + 168 + 64,
2706 .htotal = 1024 + 168 + 64 + 88,
2707 .vdisplay = 768,
2708 .vsync_start = 768 + 37,
2709 .vsync_end = 768 + 37 + 2,
2710 .vtotal = 768 + 37 + 2 + 8,
2711 .vrefresh = 60,
2712};
2713
2714static const struct panel_desc sharp_lq150x1lg11 = {
2715 .modes = &sharp_lq150x1lg11_mode,
2716 .num_modes = 1,
2717 .bpc = 6,
2718 .size = {
2719 .width = 304,
2720 .height = 228,
2721 },
2722 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2723};
2724
2725static const struct display_timing sharp_ls020b1dd01d_timing = {
2726 .pixelclock = { 2000000, 4200000, 5000000 },
2727 .hactive = { 240, 240, 240 },
2728 .hfront_porch = { 66, 66, 66 },
2729 .hback_porch = { 1, 1, 1 },
2730 .hsync_len = { 1, 1, 1 },
2731 .vactive = { 160, 160, 160 },
2732 .vfront_porch = { 52, 52, 52 },
2733 .vback_porch = { 6, 6, 6 },
2734 .vsync_len = { 10, 10, 10 },
2735 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2736};
2737
2738static const struct panel_desc sharp_ls020b1dd01d = {
2739 .timings = &sharp_ls020b1dd01d_timing,
2740 .num_timings = 1,
2741 .bpc = 6,
2742 .size = {
2743 .width = 42,
2744 .height = 28,
2745 },
2746 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2747 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2748 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2749 | DRM_BUS_FLAG_SHARP_SIGNALS,
2750};
2751
2752static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2753 .clock = 33300,
2754 .hdisplay = 800,
2755 .hsync_start = 800 + 1,
2756 .hsync_end = 800 + 1 + 64,
2757 .htotal = 800 + 1 + 64 + 64,
2758 .vdisplay = 480,
2759 .vsync_start = 480 + 1,
2760 .vsync_end = 480 + 1 + 23,
2761 .vtotal = 480 + 1 + 23 + 22,
2762 .vrefresh = 60,
2763};
2764
2765static const struct panel_desc shelly_sca07010_bfn_lnn = {
2766 .modes = &shelly_sca07010_bfn_lnn_mode,
2767 .num_modes = 1,
2768 .size = {
2769 .width = 152,
2770 .height = 91,
2771 },
2772 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2773};
2774
2775static const struct drm_display_mode starry_kr122ea0sra_mode = {
2776 .clock = 147000,
2777 .hdisplay = 1920,
2778 .hsync_start = 1920 + 16,
2779 .hsync_end = 1920 + 16 + 16,
2780 .htotal = 1920 + 16 + 16 + 32,
2781 .vdisplay = 1200,
2782 .vsync_start = 1200 + 15,
2783 .vsync_end = 1200 + 15 + 2,
2784 .vtotal = 1200 + 15 + 2 + 18,
2785 .vrefresh = 60,
2786 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2787};
2788
2789static const struct panel_desc starry_kr122ea0sra = {
2790 .modes = &starry_kr122ea0sra_mode,
2791 .num_modes = 1,
2792 .size = {
2793 .width = 263,
2794 .height = 164,
2795 },
2796 .delay = {
2797 .prepare = 10 + 200,
2798 .enable = 50,
2799 .unprepare = 10 + 500,
2800 },
2801};
2802
2803static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2804 .clock = 30000,
2805 .hdisplay = 800,
2806 .hsync_start = 800 + 39,
2807 .hsync_end = 800 + 39 + 47,
2808 .htotal = 800 + 39 + 47 + 39,
2809 .vdisplay = 480,
2810 .vsync_start = 480 + 13,
2811 .vsync_end = 480 + 13 + 2,
2812 .vtotal = 480 + 13 + 2 + 29,
2813 .vrefresh = 62,
2814};
2815
2816static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2817 .modes = &tfc_s9700rtwv43tr_01b_mode,
2818 .num_modes = 1,
2819 .bpc = 8,
2820 .size = {
2821 .width = 155,
2822 .height = 90,
2823 },
2824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2825 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2826};
2827
2828static const struct display_timing tianma_tm070jdhg30_timing = {
2829 .pixelclock = { 62600000, 68200000, 78100000 },
2830 .hactive = { 1280, 1280, 1280 },
2831 .hfront_porch = { 15, 64, 159 },
2832 .hback_porch = { 5, 5, 5 },
2833 .hsync_len = { 1, 1, 256 },
2834 .vactive = { 800, 800, 800 },
2835 .vfront_porch = { 3, 40, 99 },
2836 .vback_porch = { 2, 2, 2 },
2837 .vsync_len = { 1, 1, 128 },
2838 .flags = DISPLAY_FLAGS_DE_HIGH,
2839};
2840
2841static const struct panel_desc tianma_tm070jdhg30 = {
2842 .timings = &tianma_tm070jdhg30_timing,
2843 .num_timings = 1,
2844 .bpc = 8,
2845 .size = {
2846 .width = 151,
2847 .height = 95,
2848 },
2849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2850};
2851
2852static const struct display_timing tianma_tm070rvhg71_timing = {
2853 .pixelclock = { 27700000, 29200000, 39600000 },
2854 .hactive = { 800, 800, 800 },
2855 .hfront_porch = { 12, 40, 212 },
2856 .hback_porch = { 88, 88, 88 },
2857 .hsync_len = { 1, 1, 40 },
2858 .vactive = { 480, 480, 480 },
2859 .vfront_porch = { 1, 13, 88 },
2860 .vback_porch = { 32, 32, 32 },
2861 .vsync_len = { 1, 1, 3 },
2862 .flags = DISPLAY_FLAGS_DE_HIGH,
2863};
2864
2865static const struct panel_desc tianma_tm070rvhg71 = {
2866 .timings = &tianma_tm070rvhg71_timing,
2867 .num_timings = 1,
2868 .bpc = 8,
2869 .size = {
2870 .width = 154,
2871 .height = 86,
2872 },
2873 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2874};
2875
2876static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2877 {
2878 .clock = 10000,
2879 .hdisplay = 320,
2880 .hsync_start = 320 + 50,
2881 .hsync_end = 320 + 50 + 6,
2882 .htotal = 320 + 50 + 6 + 38,
2883 .vdisplay = 240,
2884 .vsync_start = 240 + 3,
2885 .vsync_end = 240 + 3 + 1,
2886 .vtotal = 240 + 3 + 1 + 17,
2887 .vrefresh = 60,
2888 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2889 },
2890};
2891
2892static const struct panel_desc ti_nspire_cx_lcd_panel = {
2893 .modes = ti_nspire_cx_lcd_mode,
2894 .num_modes = 1,
2895 .bpc = 8,
2896 .size = {
2897 .width = 65,
2898 .height = 49,
2899 },
2900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2901 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2902};
2903
2904static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2905 {
2906 .clock = 10000,
2907 .hdisplay = 320,
2908 .hsync_start = 320 + 6,
2909 .hsync_end = 320 + 6 + 6,
2910 .htotal = 320 + 6 + 6 + 6,
2911 .vdisplay = 240,
2912 .vsync_start = 240 + 0,
2913 .vsync_end = 240 + 0 + 1,
2914 .vtotal = 240 + 0 + 1 + 0,
2915 .vrefresh = 60,
2916 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2917 },
2918};
2919
2920static const struct panel_desc ti_nspire_classic_lcd_panel = {
2921 .modes = ti_nspire_classic_lcd_mode,
2922 .num_modes = 1,
2923 /* The grayscale panel has 8 bit for the color .. Y (black) */
2924 .bpc = 8,
2925 .size = {
2926 .width = 71,
2927 .height = 53,
2928 },
2929 /* This is the grayscale bus format */
2930 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2931 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2932};
2933
2934static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2935 .clock = 79500,
2936 .hdisplay = 1280,
2937 .hsync_start = 1280 + 192,
2938 .hsync_end = 1280 + 192 + 128,
2939 .htotal = 1280 + 192 + 128 + 64,
2940 .vdisplay = 768,
2941 .vsync_start = 768 + 20,
2942 .vsync_end = 768 + 20 + 7,
2943 .vtotal = 768 + 20 + 7 + 3,
2944 .vrefresh = 60,
2945};
2946
2947static const struct panel_desc toshiba_lt089ac29000 = {
2948 .modes = &toshiba_lt089ac29000_mode,
2949 .num_modes = 1,
2950 .size = {
2951 .width = 194,
2952 .height = 116,
2953 },
2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2956};
2957
2958static const struct drm_display_mode tpk_f07a_0102_mode = {
2959 .clock = 33260,
2960 .hdisplay = 800,
2961 .hsync_start = 800 + 40,
2962 .hsync_end = 800 + 40 + 128,
2963 .htotal = 800 + 40 + 128 + 88,
2964 .vdisplay = 480,
2965 .vsync_start = 480 + 10,
2966 .vsync_end = 480 + 10 + 2,
2967 .vtotal = 480 + 10 + 2 + 33,
2968 .vrefresh = 60,
2969};
2970
2971static const struct panel_desc tpk_f07a_0102 = {
2972 .modes = &tpk_f07a_0102_mode,
2973 .num_modes = 1,
2974 .size = {
2975 .width = 152,
2976 .height = 91,
2977 },
2978 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2979};
2980
2981static const struct drm_display_mode tpk_f10a_0102_mode = {
2982 .clock = 45000,
2983 .hdisplay = 1024,
2984 .hsync_start = 1024 + 176,
2985 .hsync_end = 1024 + 176 + 5,
2986 .htotal = 1024 + 176 + 5 + 88,
2987 .vdisplay = 600,
2988 .vsync_start = 600 + 20,
2989 .vsync_end = 600 + 20 + 5,
2990 .vtotal = 600 + 20 + 5 + 25,
2991 .vrefresh = 60,
2992};
2993
2994static const struct panel_desc tpk_f10a_0102 = {
2995 .modes = &tpk_f10a_0102_mode,
2996 .num_modes = 1,
2997 .size = {
2998 .width = 223,
2999 .height = 125,
3000 },
3001};
3002
3003static const struct display_timing urt_umsh_8596md_timing = {
3004 .pixelclock = { 33260000, 33260000, 33260000 },
3005 .hactive = { 800, 800, 800 },
3006 .hfront_porch = { 41, 41, 41 },
3007 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3008 .hsync_len = { 71, 128, 128 },
3009 .vactive = { 480, 480, 480 },
3010 .vfront_porch = { 10, 10, 10 },
3011 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3012 .vsync_len = { 2, 2, 2 },
3013 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3014 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3015};
3016
3017static const struct panel_desc urt_umsh_8596md_lvds = {
3018 .timings = &urt_umsh_8596md_timing,
3019 .num_timings = 1,
3020 .bpc = 6,
3021 .size = {
3022 .width = 152,
3023 .height = 91,
3024 },
3025 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3026};
3027
3028static const struct panel_desc urt_umsh_8596md_parallel = {
3029 .timings = &urt_umsh_8596md_timing,
3030 .num_timings = 1,
3031 .bpc = 6,
3032 .size = {
3033 .width = 152,
3034 .height = 91,
3035 },
3036 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3037};
3038
3039static const struct drm_display_mode vl050_8048nt_c01_mode = {
3040 .clock = 33333,
3041 .hdisplay = 800,
3042 .hsync_start = 800 + 210,
3043 .hsync_end = 800 + 210 + 20,
3044 .htotal = 800 + 210 + 20 + 46,
3045 .vdisplay = 480,
3046 .vsync_start = 480 + 22,
3047 .vsync_end = 480 + 22 + 10,
3048 .vtotal = 480 + 22 + 10 + 23,
3049 .vrefresh = 60,
3050 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3051};
3052
3053static const struct panel_desc vl050_8048nt_c01 = {
3054 .modes = &vl050_8048nt_c01_mode,
3055 .num_modes = 1,
3056 .bpc = 8,
3057 .size = {
3058 .width = 120,
3059 .height = 76,
3060 },
3061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3062 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3063};
3064
3065static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3066 .clock = 6410,
3067 .hdisplay = 320,
3068 .hsync_start = 320 + 20,
3069 .hsync_end = 320 + 20 + 30,
3070 .htotal = 320 + 20 + 30 + 38,
3071 .vdisplay = 240,
3072 .vsync_start = 240 + 4,
3073 .vsync_end = 240 + 4 + 3,
3074 .vtotal = 240 + 4 + 3 + 15,
3075 .vrefresh = 60,
3076 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3077};
3078
3079static const struct panel_desc winstar_wf35ltiacd = {
3080 .modes = &winstar_wf35ltiacd_mode,
3081 .num_modes = 1,
3082 .bpc = 8,
3083 .size = {
3084 .width = 70,
3085 .height = 53,
3086 },
3087 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3088};
3089
3090static const struct drm_display_mode arm_rtsm_mode[] = {
3091 {
3092 .clock = 65000,
3093 .hdisplay = 1024,
3094 .hsync_start = 1024 + 24,
3095 .hsync_end = 1024 + 24 + 136,
3096 .htotal = 1024 + 24 + 136 + 160,
3097 .vdisplay = 768,
3098 .vsync_start = 768 + 3,
3099 .vsync_end = 768 + 3 + 6,
3100 .vtotal = 768 + 3 + 6 + 29,
3101 .vrefresh = 60,
3102 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3103 },
3104};
3105
3106static const struct panel_desc arm_rtsm = {
3107 .modes = arm_rtsm_mode,
3108 .num_modes = 1,
3109 .bpc = 8,
3110 .size = {
3111 .width = 400,
3112 .height = 300,
3113 },
3114 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3115};
3116
3117static const struct of_device_id platform_of_match[] = {
3118 {
3119 .compatible = "ampire,am-480272h3tmqw-t01h",
3120 .data = &ampire_am_480272h3tmqw_t01h,
3121 }, {
3122 .compatible = "ampire,am800480r3tmqwa1h",
3123 .data = &ampire_am800480r3tmqwa1h,
3124 }, {
3125 .compatible = "arm,rtsm-display",
3126 .data = &arm_rtsm,
3127 }, {
3128 .compatible = "armadeus,st0700-adapt",
3129 .data = &armadeus_st0700_adapt,
3130 }, {
3131 .compatible = "auo,b101aw03",
3132 .data = &auo_b101aw03,
3133 }, {
3134 .compatible = "auo,b101ean01",
3135 .data = &auo_b101ean01,
3136 }, {
3137 .compatible = "auo,b101xtn01",
3138 .data = &auo_b101xtn01,
3139 }, {
3140 .compatible = "auo,b116xw03",
3141 .data = &auo_b116xw03,
3142 }, {
3143 .compatible = "auo,b133htn01",
3144 .data = &auo_b133htn01,
3145 }, {
3146 .compatible = "auo,b133xtn01",
3147 .data = &auo_b133xtn01,
3148 }, {
3149 .compatible = "auo,g070vvn01",
3150 .data = &auo_g070vvn01,
3151 }, {
3152 .compatible = "auo,g101evn010",
3153 .data = &auo_g101evn010,
3154 }, {
3155 .compatible = "auo,g104sn02",
3156 .data = &auo_g104sn02,
3157 }, {
3158 .compatible = "auo,g133han01",
3159 .data = &auo_g133han01,
3160 }, {
3161 .compatible = "auo,g185han01",
3162 .data = &auo_g185han01,
3163 }, {
3164 .compatible = "auo,p320hvn03",
3165 .data = &auo_p320hvn03,
3166 }, {
3167 .compatible = "auo,t215hvn01",
3168 .data = &auo_t215hvn01,
3169 }, {
3170 .compatible = "avic,tm070ddh03",
3171 .data = &avic_tm070ddh03,
3172 }, {
3173 .compatible = "bananapi,s070wv20-ct16",
3174 .data = &bananapi_s070wv20_ct16,
3175 }, {
3176 .compatible = "boe,hv070wsa-100",
3177 .data = &boe_hv070wsa
3178 }, {
3179 .compatible = "boe,nv101wxmn51",
3180 .data = &boe_nv101wxmn51,
3181 }, {
3182 .compatible = "cdtech,s043wq26h-ct7",
3183 .data = &cdtech_s043wq26h_ct7,
3184 }, {
3185 .compatible = "cdtech,s070wv95-ct16",
3186 .data = &cdtech_s070wv95_ct16,
3187 }, {
3188 .compatible = "chunghwa,claa070wp03xg",
3189 .data = &chunghwa_claa070wp03xg,
3190 }, {
3191 .compatible = "chunghwa,claa101wa01a",
3192 .data = &chunghwa_claa101wa01a
3193 }, {
3194 .compatible = "chunghwa,claa101wb01",
3195 .data = &chunghwa_claa101wb01
3196 }, {
3197 .compatible = "dataimage,scf0700c48ggu18",
3198 .data = &dataimage_scf0700c48ggu18,
3199 }, {
3200 .compatible = "dlc,dlc0700yzg-1",
3201 .data = &dlc_dlc0700yzg_1,
3202 }, {
3203 .compatible = "dlc,dlc1010gig",
3204 .data = &dlc_dlc1010gig,
3205 }, {
3206 .compatible = "edt,et035012dm6",
3207 .data = &edt_et035012dm6,
3208 }, {
3209 .compatible = "edt,etm0430g0dh6",
3210 .data = &edt_etm0430g0dh6,
3211 }, {
3212 .compatible = "edt,et057090dhu",
3213 .data = &edt_et057090dhu,
3214 }, {
3215 .compatible = "edt,et070080dh6",
3216 .data = &edt_etm0700g0dh6,
3217 }, {
3218 .compatible = "edt,etm0700g0dh6",
3219 .data = &edt_etm0700g0dh6,
3220 }, {
3221 .compatible = "edt,etm0700g0bdh6",
3222 .data = &edt_etm0700g0bdh6,
3223 }, {
3224 .compatible = "edt,etm0700g0edh6",
3225 .data = &edt_etm0700g0bdh6,
3226 }, {
3227 .compatible = "evervision,vgg804821",
3228 .data = &evervision_vgg804821,
3229 }, {
3230 .compatible = "foxlink,fl500wvr00-a0t",
3231 .data = &foxlink_fl500wvr00_a0t,
3232 }, {
3233 .compatible = "friendlyarm,hd702e",
3234 .data = &friendlyarm_hd702e,
3235 }, {
3236 .compatible = "giantplus,gpg482739qs5",
3237 .data = &giantplus_gpg482739qs5
3238 }, {
3239 .compatible = "giantplus,gpm940b0",
3240 .data = &giantplus_gpm940b0,
3241 }, {
3242 .compatible = "hannstar,hsd070pww1",
3243 .data = &hannstar_hsd070pww1,
3244 }, {
3245 .compatible = "hannstar,hsd100pxn1",
3246 .data = &hannstar_hsd100pxn1,
3247 }, {
3248 .compatible = "hit,tx23d38vm0caa",
3249 .data = &hitachi_tx23d38vm0caa
3250 }, {
3251 .compatible = "innolux,at043tn24",
3252 .data = &innolux_at043tn24,
3253 }, {
3254 .compatible = "innolux,at070tn92",
3255 .data = &innolux_at070tn92,
3256 }, {
3257 .compatible = "innolux,g070y2-l01",
3258 .data = &innolux_g070y2_l01,
3259 }, {
3260 .compatible = "innolux,g101ice-l01",
3261 .data = &innolux_g101ice_l01
3262 }, {
3263 .compatible = "innolux,g121i1-l01",
3264 .data = &innolux_g121i1_l01
3265 }, {
3266 .compatible = "innolux,g121x1-l03",
3267 .data = &innolux_g121x1_l03,
3268 }, {
3269 .compatible = "innolux,n116bge",
3270 .data = &innolux_n116bge,
3271 }, {
3272 .compatible = "innolux,n156bge-l21",
3273 .data = &innolux_n156bge_l21,
3274 }, {
3275 .compatible = "innolux,p120zdg-bf1",
3276 .data = &innolux_p120zdg_bf1,
3277 }, {
3278 .compatible = "innolux,zj070na-01p",
3279 .data = &innolux_zj070na_01p,
3280 }, {
3281 .compatible = "koe,tx14d24vm1bpa",
3282 .data = &koe_tx14d24vm1bpa,
3283 }, {
3284 .compatible = "koe,tx31d200vm0baa",
3285 .data = &koe_tx31d200vm0baa,
3286 }, {
3287 .compatible = "kyo,tcg121xglp",
3288 .data = &kyo_tcg121xglp,
3289 }, {
3290 .compatible = "lemaker,bl035-rgb-002",
3291 .data = &lemaker_bl035_rgb_002,
3292 }, {
3293 .compatible = "lg,lb070wv8",
3294 .data = &lg_lb070wv8,
3295 }, {
3296 .compatible = "lg,lp079qx1-sp0v",
3297 .data = &lg_lp079qx1_sp0v,
3298 }, {
3299 .compatible = "lg,lp097qx1-spa1",
3300 .data = &lg_lp097qx1_spa1,
3301 }, {
3302 .compatible = "lg,lp120up1",
3303 .data = &lg_lp120up1,
3304 }, {
3305 .compatible = "lg,lp129qe",
3306 .data = &lg_lp129qe,
3307 }, {
3308 .compatible = "logicpd,type28",
3309 .data = &logicpd_type_28,
3310 }, {
3311 .compatible = "mitsubishi,aa070mc01-ca1",
3312 .data = &mitsubishi_aa070mc01,
3313 }, {
3314 .compatible = "nec,nl12880bc20-05",
3315 .data = &nec_nl12880bc20_05,
3316 }, {
3317 .compatible = "nec,nl4827hc19-05b",
3318 .data = &nec_nl4827hc19_05b,
3319 }, {
3320 .compatible = "netron-dy,e231732",
3321 .data = &netron_dy_e231732,
3322 }, {
3323 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3324 .data = &newhaven_nhd_43_480272ef_atxl,
3325 }, {
3326 .compatible = "nlt,nl192108ac18-02d",
3327 .data = &nlt_nl192108ac18_02d,
3328 }, {
3329 .compatible = "nvd,9128",
3330 .data = &nvd_9128,
3331 }, {
3332 .compatible = "okaya,rs800480t-7x0gp",
3333 .data = &okaya_rs800480t_7x0gp,
3334 }, {
3335 .compatible = "olimex,lcd-olinuxino-43-ts",
3336 .data = &olimex_lcd_olinuxino_43ts,
3337 }, {
3338 .compatible = "ontat,yx700wv03",
3339 .data = &ontat_yx700wv03,
3340 }, {
3341 .compatible = "ortustech,com37h3m05dtc",
3342 .data = &ortustech_com37h3m,
3343 }, {
3344 .compatible = "ortustech,com37h3m99dtc",
3345 .data = &ortustech_com37h3m,
3346 }, {
3347 .compatible = "ortustech,com43h4m85ulc",
3348 .data = &ortustech_com43h4m85ulc,
3349 }, {
3350 .compatible = "osddisplays,osd070t1718-19ts",
3351 .data = &osddisplays_osd070t1718_19ts,
3352 }, {
3353 .compatible = "pda,91-00156-a0",
3354 .data = &pda_91_00156_a0,
3355 }, {
3356 .compatible = "qiaodian,qd43003c0-40",
3357 .data = &qd43003c0_40,
3358 }, {
3359 .compatible = "rocktech,rk070er9427",
3360 .data = &rocktech_rk070er9427,
3361 }, {
3362 .compatible = "samsung,lsn122dl01-c01",
3363 .data = &samsung_lsn122dl01_c01,
3364 }, {
3365 .compatible = "samsung,ltn101nt05",
3366 .data = &samsung_ltn101nt05,
3367 }, {
3368 .compatible = "samsung,ltn140at29-301",
3369 .data = &samsung_ltn140at29_301,
3370 }, {
3371 .compatible = "sharp,ld-d5116z01b",
3372 .data = &sharp_ld_d5116z01b,
3373 }, {
3374 .compatible = "sharp,lq035q7db03",
3375 .data = &sharp_lq035q7db03,
3376 }, {
3377 .compatible = "sharp,lq070y3dg3b",
3378 .data = &sharp_lq070y3dg3b,
3379 }, {
3380 .compatible = "sharp,lq101k1ly04",
3381 .data = &sharp_lq101k1ly04,
3382 }, {
3383 .compatible = "sharp,lq123p1jx31",
3384 .data = &sharp_lq123p1jx31,
3385 }, {
3386 .compatible = "sharp,lq150x1lg11",
3387 .data = &sharp_lq150x1lg11,
3388 }, {
3389 .compatible = "sharp,ls020b1dd01d",
3390 .data = &sharp_ls020b1dd01d,
3391 }, {
3392 .compatible = "shelly,sca07010-bfn-lnn",
3393 .data = &shelly_sca07010_bfn_lnn,
3394 }, {
3395 .compatible = "starry,kr122ea0sra",
3396 .data = &starry_kr122ea0sra,
3397 }, {
3398 .compatible = "tfc,s9700rtwv43tr-01b",
3399 .data = &tfc_s9700rtwv43tr_01b,
3400 }, {
3401 .compatible = "tianma,tm070jdhg30",
3402 .data = &tianma_tm070jdhg30,
3403 }, {
3404 .compatible = "tianma,tm070rvhg71",
3405 .data = &tianma_tm070rvhg71,
3406 }, {
3407 .compatible = "ti,nspire-cx-lcd-panel",
3408 .data = &ti_nspire_cx_lcd_panel,
3409 }, {
3410 .compatible = "ti,nspire-classic-lcd-panel",
3411 .data = &ti_nspire_classic_lcd_panel,
3412 }, {
3413 .compatible = "toshiba,lt089ac29000",
3414 .data = &toshiba_lt089ac29000,
3415 }, {
3416 .compatible = "tpk,f07a-0102",
3417 .data = &tpk_f07a_0102,
3418 }, {
3419 .compatible = "tpk,f10a-0102",
3420 .data = &tpk_f10a_0102,
3421 }, {
3422 .compatible = "urt,umsh-8596md-t",
3423 .data = &urt_umsh_8596md_parallel,
3424 }, {
3425 .compatible = "urt,umsh-8596md-1t",
3426 .data = &urt_umsh_8596md_parallel,
3427 }, {
3428 .compatible = "urt,umsh-8596md-7t",
3429 .data = &urt_umsh_8596md_parallel,
3430 }, {
3431 .compatible = "urt,umsh-8596md-11t",
3432 .data = &urt_umsh_8596md_lvds,
3433 }, {
3434 .compatible = "urt,umsh-8596md-19t",
3435 .data = &urt_umsh_8596md_lvds,
3436 }, {
3437 .compatible = "urt,umsh-8596md-20t",
3438 .data = &urt_umsh_8596md_parallel,
3439 }, {
3440 .compatible = "vxt,vl050-8048nt-c01",
3441 .data = &vl050_8048nt_c01,
3442 }, {
3443 .compatible = "winstar,wf35ltiacd",
3444 .data = &winstar_wf35ltiacd,
3445 }, {
3446 /* sentinel */
3447 }
3448};
3449MODULE_DEVICE_TABLE(of, platform_of_match);
3450
3451static int panel_simple_platform_probe(struct platform_device *pdev)
3452{
3453 const struct of_device_id *id;
3454
3455 id = of_match_node(platform_of_match, pdev->dev.of_node);
3456 if (!id)
3457 return -ENODEV;
3458
3459 return panel_simple_probe(&pdev->dev, id->data);
3460}
3461
3462static int panel_simple_platform_remove(struct platform_device *pdev)
3463{
3464 return panel_simple_remove(&pdev->dev);
3465}
3466
3467static void panel_simple_platform_shutdown(struct platform_device *pdev)
3468{
3469 panel_simple_shutdown(&pdev->dev);
3470}
3471
3472static struct platform_driver panel_simple_platform_driver = {
3473 .driver = {
3474 .name = "panel-simple",
3475 .of_match_table = platform_of_match,
3476 },
3477 .probe = panel_simple_platform_probe,
3478 .remove = panel_simple_platform_remove,
3479 .shutdown = panel_simple_platform_shutdown,
3480};
3481
3482struct panel_desc_dsi {
3483 struct panel_desc desc;
3484
3485 unsigned long flags;
3486 enum mipi_dsi_pixel_format format;
3487 unsigned int lanes;
3488};
3489
3490static const struct drm_display_mode auo_b080uan01_mode = {
3491 .clock = 154500,
3492 .hdisplay = 1200,
3493 .hsync_start = 1200 + 62,
3494 .hsync_end = 1200 + 62 + 4,
3495 .htotal = 1200 + 62 + 4 + 62,
3496 .vdisplay = 1920,
3497 .vsync_start = 1920 + 9,
3498 .vsync_end = 1920 + 9 + 2,
3499 .vtotal = 1920 + 9 + 2 + 8,
3500 .vrefresh = 60,
3501};
3502
3503static const struct panel_desc_dsi auo_b080uan01 = {
3504 .desc = {
3505 .modes = &auo_b080uan01_mode,
3506 .num_modes = 1,
3507 .bpc = 8,
3508 .size = {
3509 .width = 108,
3510 .height = 272,
3511 },
3512 },
3513 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3514 .format = MIPI_DSI_FMT_RGB888,
3515 .lanes = 4,
3516};
3517
3518static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3519 .clock = 160000,
3520 .hdisplay = 1200,
3521 .hsync_start = 1200 + 120,
3522 .hsync_end = 1200 + 120 + 20,
3523 .htotal = 1200 + 120 + 20 + 21,
3524 .vdisplay = 1920,
3525 .vsync_start = 1920 + 21,
3526 .vsync_end = 1920 + 21 + 3,
3527 .vtotal = 1920 + 21 + 3 + 18,
3528 .vrefresh = 60,
3529 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3530};
3531
3532static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3533 .desc = {
3534 .modes = &boe_tv080wum_nl0_mode,
3535 .num_modes = 1,
3536 .size = {
3537 .width = 107,
3538 .height = 172,
3539 },
3540 },
3541 .flags = MIPI_DSI_MODE_VIDEO |
3542 MIPI_DSI_MODE_VIDEO_BURST |
3543 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3544 .format = MIPI_DSI_FMT_RGB888,
3545 .lanes = 4,
3546};
3547
3548static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3549 .clock = 71000,
3550 .hdisplay = 800,
3551 .hsync_start = 800 + 32,
3552 .hsync_end = 800 + 32 + 1,
3553 .htotal = 800 + 32 + 1 + 57,
3554 .vdisplay = 1280,
3555 .vsync_start = 1280 + 28,
3556 .vsync_end = 1280 + 28 + 1,
3557 .vtotal = 1280 + 28 + 1 + 14,
3558 .vrefresh = 60,
3559};
3560
3561static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3562 .desc = {
3563 .modes = &lg_ld070wx3_sl01_mode,
3564 .num_modes = 1,
3565 .bpc = 8,
3566 .size = {
3567 .width = 94,
3568 .height = 151,
3569 },
3570 },
3571 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3572 .format = MIPI_DSI_FMT_RGB888,
3573 .lanes = 4,
3574};
3575
3576static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3577 .clock = 67000,
3578 .hdisplay = 720,
3579 .hsync_start = 720 + 12,
3580 .hsync_end = 720 + 12 + 4,
3581 .htotal = 720 + 12 + 4 + 112,
3582 .vdisplay = 1280,
3583 .vsync_start = 1280 + 8,
3584 .vsync_end = 1280 + 8 + 4,
3585 .vtotal = 1280 + 8 + 4 + 12,
3586 .vrefresh = 60,
3587};
3588
3589static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3590 .desc = {
3591 .modes = &lg_lh500wx1_sd03_mode,
3592 .num_modes = 1,
3593 .bpc = 8,
3594 .size = {
3595 .width = 62,
3596 .height = 110,
3597 },
3598 },
3599 .flags = MIPI_DSI_MODE_VIDEO,
3600 .format = MIPI_DSI_FMT_RGB888,
3601 .lanes = 4,
3602};
3603
3604static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3605 .clock = 157200,
3606 .hdisplay = 1920,
3607 .hsync_start = 1920 + 154,
3608 .hsync_end = 1920 + 154 + 16,
3609 .htotal = 1920 + 154 + 16 + 32,
3610 .vdisplay = 1200,
3611 .vsync_start = 1200 + 17,
3612 .vsync_end = 1200 + 17 + 2,
3613 .vtotal = 1200 + 17 + 2 + 16,
3614 .vrefresh = 60,
3615};
3616
3617static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3618 .desc = {
3619 .modes = &panasonic_vvx10f004b00_mode,
3620 .num_modes = 1,
3621 .bpc = 8,
3622 .size = {
3623 .width = 217,
3624 .height = 136,
3625 },
3626 },
3627 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3628 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3629 .format = MIPI_DSI_FMT_RGB888,
3630 .lanes = 4,
3631};
3632
3633static const struct drm_display_mode lg_acx467akm_7_mode = {
3634 .clock = 150000,
3635 .hdisplay = 1080,
3636 .hsync_start = 1080 + 2,
3637 .hsync_end = 1080 + 2 + 2,
3638 .htotal = 1080 + 2 + 2 + 2,
3639 .vdisplay = 1920,
3640 .vsync_start = 1920 + 2,
3641 .vsync_end = 1920 + 2 + 2,
3642 .vtotal = 1920 + 2 + 2 + 2,
3643 .vrefresh = 60,
3644};
3645
3646static const struct panel_desc_dsi lg_acx467akm_7 = {
3647 .desc = {
3648 .modes = &lg_acx467akm_7_mode,
3649 .num_modes = 1,
3650 .bpc = 8,
3651 .size = {
3652 .width = 62,
3653 .height = 110,
3654 },
3655 },
3656 .flags = 0,
3657 .format = MIPI_DSI_FMT_RGB888,
3658 .lanes = 4,
3659};
3660
3661static const struct drm_display_mode osd101t2045_53ts_mode = {
3662 .clock = 154500,
3663 .hdisplay = 1920,
3664 .hsync_start = 1920 + 112,
3665 .hsync_end = 1920 + 112 + 16,
3666 .htotal = 1920 + 112 + 16 + 32,
3667 .vdisplay = 1200,
3668 .vsync_start = 1200 + 16,
3669 .vsync_end = 1200 + 16 + 2,
3670 .vtotal = 1200 + 16 + 2 + 16,
3671 .vrefresh = 60,
3672 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3673};
3674
3675static const struct panel_desc_dsi osd101t2045_53ts = {
3676 .desc = {
3677 .modes = &osd101t2045_53ts_mode,
3678 .num_modes = 1,
3679 .bpc = 8,
3680 .size = {
3681 .width = 217,
3682 .height = 136,
3683 },
3684 },
3685 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3686 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3687 MIPI_DSI_MODE_EOT_PACKET,
3688 .format = MIPI_DSI_FMT_RGB888,
3689 .lanes = 4,
3690};
3691
3692static const struct of_device_id dsi_of_match[] = {
3693 {
3694 .compatible = "auo,b080uan01",
3695 .data = &auo_b080uan01
3696 }, {
3697 .compatible = "boe,tv080wum-nl0",
3698 .data = &boe_tv080wum_nl0
3699 }, {
3700 .compatible = "lg,ld070wx3-sl01",
3701 .data = &lg_ld070wx3_sl01
3702 }, {
3703 .compatible = "lg,lh500wx1-sd03",
3704 .data = &lg_lh500wx1_sd03
3705 }, {
3706 .compatible = "panasonic,vvx10f004b00",
3707 .data = &panasonic_vvx10f004b00
3708 }, {
3709 .compatible = "lg,acx467akm-7",
3710 .data = &lg_acx467akm_7
3711 }, {
3712 .compatible = "osddisplays,osd101t2045-53ts",
3713 .data = &osd101t2045_53ts
3714 }, {
3715 /* sentinel */
3716 }
3717};
3718MODULE_DEVICE_TABLE(of, dsi_of_match);
3719
3720static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3721{
3722 const struct panel_desc_dsi *desc;
3723 const struct of_device_id *id;
3724 int err;
3725
3726 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3727 if (!id)
3728 return -ENODEV;
3729
3730 desc = id->data;
3731
3732 err = panel_simple_probe(&dsi->dev, &desc->desc);
3733 if (err < 0)
3734 return err;
3735
3736 dsi->mode_flags = desc->flags;
3737 dsi->format = desc->format;
3738 dsi->lanes = desc->lanes;
3739
3740 err = mipi_dsi_attach(dsi);
3741 if (err) {
3742 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3743
3744 drm_panel_remove(&panel->base);
3745 }
3746
3747 return err;
3748}
3749
3750static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3751{
3752 int err;
3753
3754 err = mipi_dsi_detach(dsi);
3755 if (err < 0)
3756 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3757
3758 return panel_simple_remove(&dsi->dev);
3759}
3760
3761static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3762{
3763 panel_simple_shutdown(&dsi->dev);
3764}
3765
3766static struct mipi_dsi_driver panel_simple_dsi_driver = {
3767 .driver = {
3768 .name = "panel-simple-dsi",
3769 .of_match_table = dsi_of_match,
3770 },
3771 .probe = panel_simple_dsi_probe,
3772 .remove = panel_simple_dsi_remove,
3773 .shutdown = panel_simple_dsi_shutdown,
3774};
3775
3776static int __init panel_simple_init(void)
3777{
3778 int err;
3779
3780 err = platform_driver_register(&panel_simple_platform_driver);
3781 if (err < 0)
3782 return err;
3783
3784 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3785 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3786 if (err < 0)
3787 return err;
3788 }
3789
3790 return 0;
3791}
3792module_init(panel_simple_init);
3793
3794static void __exit panel_simple_exit(void)
3795{
3796 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3797 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3798
3799 platform_driver_unregister(&panel_simple_platform_driver);
3800}
3801module_exit(panel_simple_exit);
3802
3803MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3804MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3805MODULE_LICENSE("GPL and additional rights");