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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / gpu / drm / tegra / sor.c
blob: ccd084abc8c94aac8c9040a2dbf106252577f8d8 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>
9#include <linux/gpio.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17
18#include <soc/tegra/pmc.h>
19
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_debugfs.h>
22#include <drm/drm_dp_helper.h>
23#include <drm/drm_file.h>
24#include <drm/drm_panel.h>
25#include <drm/drm_scdc_helper.h>
26
27#include "dc.h"
28#include "drm.h"
29#include "hda.h"
30#include "sor.h"
31#include "trace.h"
32
33#define SOR_REKEY 0x38
34
35struct tegra_sor_hdmi_settings {
36 unsigned long frequency;
37
38 u8 vcocap;
39 u8 filter;
40 u8 ichpmp;
41 u8 loadadj;
42 u8 tmds_termadj;
43 u8 tx_pu_value;
44 u8 bg_temp_coef;
45 u8 bg_vref_level;
46 u8 avdd10_level;
47 u8 avdd14_level;
48 u8 sparepll;
49
50 u8 drive_current[4];
51 u8 preemphasis[4];
52};
53
54#if 1
55static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
56 {
57 .frequency = 54000000,
58 .vcocap = 0x0,
59 .filter = 0x0,
60 .ichpmp = 0x1,
61 .loadadj = 0x3,
62 .tmds_termadj = 0x9,
63 .tx_pu_value = 0x10,
64 .bg_temp_coef = 0x3,
65 .bg_vref_level = 0x8,
66 .avdd10_level = 0x4,
67 .avdd14_level = 0x4,
68 .sparepll = 0x0,
69 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
70 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
71 }, {
72 .frequency = 75000000,
73 .vcocap = 0x3,
74 .filter = 0x0,
75 .ichpmp = 0x1,
76 .loadadj = 0x3,
77 .tmds_termadj = 0x9,
78 .tx_pu_value = 0x40,
79 .bg_temp_coef = 0x3,
80 .bg_vref_level = 0x8,
81 .avdd10_level = 0x4,
82 .avdd14_level = 0x4,
83 .sparepll = 0x0,
84 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
85 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
86 }, {
87 .frequency = 150000000,
88 .vcocap = 0x3,
89 .filter = 0x0,
90 .ichpmp = 0x1,
91 .loadadj = 0x3,
92 .tmds_termadj = 0x9,
93 .tx_pu_value = 0x66,
94 .bg_temp_coef = 0x3,
95 .bg_vref_level = 0x8,
96 .avdd10_level = 0x4,
97 .avdd14_level = 0x4,
98 .sparepll = 0x0,
99 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
100 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
101 }, {
102 .frequency = 300000000,
103 .vcocap = 0x3,
104 .filter = 0x0,
105 .ichpmp = 0x1,
106 .loadadj = 0x3,
107 .tmds_termadj = 0x9,
108 .tx_pu_value = 0x66,
109 .bg_temp_coef = 0x3,
110 .bg_vref_level = 0xa,
111 .avdd10_level = 0x4,
112 .avdd14_level = 0x4,
113 .sparepll = 0x0,
114 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
115 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
116 }, {
117 .frequency = 600000000,
118 .vcocap = 0x3,
119 .filter = 0x0,
120 .ichpmp = 0x1,
121 .loadadj = 0x3,
122 .tmds_termadj = 0x9,
123 .tx_pu_value = 0x66,
124 .bg_temp_coef = 0x3,
125 .bg_vref_level = 0x8,
126 .avdd10_level = 0x4,
127 .avdd14_level = 0x4,
128 .sparepll = 0x0,
129 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
130 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
131 },
132};
133#else
134static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
135 {
136 .frequency = 75000000,
137 .vcocap = 0x3,
138 .filter = 0x0,
139 .ichpmp = 0x1,
140 .loadadj = 0x3,
141 .tmds_termadj = 0x9,
142 .tx_pu_value = 0x40,
143 .bg_temp_coef = 0x3,
144 .bg_vref_level = 0x8,
145 .avdd10_level = 0x4,
146 .avdd14_level = 0x4,
147 .sparepll = 0x0,
148 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
149 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
150 }, {
151 .frequency = 150000000,
152 .vcocap = 0x3,
153 .filter = 0x0,
154 .ichpmp = 0x1,
155 .loadadj = 0x3,
156 .tmds_termadj = 0x9,
157 .tx_pu_value = 0x66,
158 .bg_temp_coef = 0x3,
159 .bg_vref_level = 0x8,
160 .avdd10_level = 0x4,
161 .avdd14_level = 0x4,
162 .sparepll = 0x0,
163 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
164 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
165 }, {
166 .frequency = 300000000,
167 .vcocap = 0x3,
168 .filter = 0x0,
169 .ichpmp = 0x6,
170 .loadadj = 0x3,
171 .tmds_termadj = 0x9,
172 .tx_pu_value = 0x66,
173 .bg_temp_coef = 0x3,
174 .bg_vref_level = 0xf,
175 .avdd10_level = 0x4,
176 .avdd14_level = 0x4,
177 .sparepll = 0x0,
178 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
179 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
180 }, {
181 .frequency = 600000000,
182 .vcocap = 0x3,
183 .filter = 0x0,
184 .ichpmp = 0xa,
185 .loadadj = 0x3,
186 .tmds_termadj = 0xb,
187 .tx_pu_value = 0x66,
188 .bg_temp_coef = 0x3,
189 .bg_vref_level = 0xe,
190 .avdd10_level = 0x4,
191 .avdd14_level = 0x4,
192 .sparepll = 0x0,
193 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
194 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
195 },
196};
197#endif
198
199static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
200 {
201 .frequency = 54000000,
202 .vcocap = 0,
203 .filter = 5,
204 .ichpmp = 5,
205 .loadadj = 3,
206 .tmds_termadj = 0xf,
207 .tx_pu_value = 0,
208 .bg_temp_coef = 3,
209 .bg_vref_level = 8,
210 .avdd10_level = 4,
211 .avdd14_level = 4,
212 .sparepll = 0x54,
213 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
214 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
215 }, {
216 .frequency = 75000000,
217 .vcocap = 1,
218 .filter = 5,
219 .ichpmp = 5,
220 .loadadj = 3,
221 .tmds_termadj = 0xf,
222 .tx_pu_value = 0,
223 .bg_temp_coef = 3,
224 .bg_vref_level = 8,
225 .avdd10_level = 4,
226 .avdd14_level = 4,
227 .sparepll = 0x44,
228 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
229 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
230 }, {
231 .frequency = 150000000,
232 .vcocap = 3,
233 .filter = 5,
234 .ichpmp = 5,
235 .loadadj = 3,
236 .tmds_termadj = 15,
237 .tx_pu_value = 0x66 /* 0 */,
238 .bg_temp_coef = 3,
239 .bg_vref_level = 8,
240 .avdd10_level = 4,
241 .avdd14_level = 4,
242 .sparepll = 0x00, /* 0x34 */
243 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
244 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
245 }, {
246 .frequency = 300000000,
247 .vcocap = 3,
248 .filter = 5,
249 .ichpmp = 5,
250 .loadadj = 3,
251 .tmds_termadj = 15,
252 .tx_pu_value = 64,
253 .bg_temp_coef = 3,
254 .bg_vref_level = 8,
255 .avdd10_level = 4,
256 .avdd14_level = 4,
257 .sparepll = 0x34,
258 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
259 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
260 }, {
261 .frequency = 600000000,
262 .vcocap = 3,
263 .filter = 5,
264 .ichpmp = 5,
265 .loadadj = 3,
266 .tmds_termadj = 12,
267 .tx_pu_value = 96,
268 .bg_temp_coef = 3,
269 .bg_vref_level = 8,
270 .avdd10_level = 4,
271 .avdd14_level = 4,
272 .sparepll = 0x34,
273 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
274 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
275 }
276};
277
278static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
279 {
280 .frequency = 54000000,
281 .vcocap = 0,
282 .filter = 5,
283 .ichpmp = 5,
284 .loadadj = 3,
285 .tmds_termadj = 0xf,
286 .tx_pu_value = 0,
287 .bg_temp_coef = 3,
288 .bg_vref_level = 8,
289 .avdd10_level = 4,
290 .avdd14_level = 4,
291 .sparepll = 0x54,
292 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
293 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
294 }, {
295 .frequency = 75000000,
296 .vcocap = 1,
297 .filter = 5,
298 .ichpmp = 5,
299 .loadadj = 3,
300 .tmds_termadj = 0xf,
301 .tx_pu_value = 0,
302 .bg_temp_coef = 3,
303 .bg_vref_level = 8,
304 .avdd10_level = 4,
305 .avdd14_level = 4,
306 .sparepll = 0x44,
307 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
308 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
309 }, {
310 .frequency = 150000000,
311 .vcocap = 3,
312 .filter = 5,
313 .ichpmp = 5,
314 .loadadj = 3,
315 .tmds_termadj = 15,
316 .tx_pu_value = 0x66 /* 0 */,
317 .bg_temp_coef = 3,
318 .bg_vref_level = 8,
319 .avdd10_level = 4,
320 .avdd14_level = 4,
321 .sparepll = 0x00, /* 0x34 */
322 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
323 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
324 }, {
325 .frequency = 300000000,
326 .vcocap = 3,
327 .filter = 5,
328 .ichpmp = 5,
329 .loadadj = 3,
330 .tmds_termadj = 15,
331 .tx_pu_value = 64,
332 .bg_temp_coef = 3,
333 .bg_vref_level = 8,
334 .avdd10_level = 4,
335 .avdd14_level = 4,
336 .sparepll = 0x34,
337 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
338 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
339 }, {
340 .frequency = 600000000,
341 .vcocap = 3,
342 .filter = 5,
343 .ichpmp = 5,
344 .loadadj = 3,
345 .tmds_termadj = 12,
346 .tx_pu_value = 96,
347 .bg_temp_coef = 3,
348 .bg_vref_level = 8,
349 .avdd10_level = 4,
350 .avdd14_level = 4,
351 .sparepll = 0x34,
352 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
353 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
354 }
355};
356
357struct tegra_sor_regs {
358 unsigned int head_state0;
359 unsigned int head_state1;
360 unsigned int head_state2;
361 unsigned int head_state3;
362 unsigned int head_state4;
363 unsigned int head_state5;
364 unsigned int pll0;
365 unsigned int pll1;
366 unsigned int pll2;
367 unsigned int pll3;
368 unsigned int dp_padctl0;
369 unsigned int dp_padctl2;
370};
371
372struct tegra_sor_soc {
373 bool supports_edp;
374 bool supports_lvds;
375 bool supports_hdmi;
376 bool supports_dp;
377
378 const struct tegra_sor_regs *regs;
379 bool has_nvdisplay;
380
381 const struct tegra_sor_hdmi_settings *settings;
382 unsigned int num_settings;
383
384 const u8 *xbar_cfg;
385};
386
387struct tegra_sor;
388
389struct tegra_sor_ops {
390 const char *name;
391 int (*probe)(struct tegra_sor *sor);
392 int (*remove)(struct tegra_sor *sor);
393};
394
395struct tegra_sor {
396 struct host1x_client client;
397 struct tegra_output output;
398 struct device *dev;
399
400 const struct tegra_sor_soc *soc;
401 void __iomem *regs;
402 unsigned int index;
403 unsigned int irq;
404
405 struct reset_control *rst;
406 struct clk *clk_parent;
407 struct clk *clk_safe;
408 struct clk *clk_out;
409 struct clk *clk_pad;
410 struct clk *clk_dp;
411 struct clk *clk;
412
413 u8 xbar_cfg[5];
414
415 struct drm_dp_aux *aux;
416
417 struct drm_info_list *debugfs_files;
418
419 const struct tegra_sor_ops *ops;
420 enum tegra_io_pad pad;
421
422 /* for HDMI 2.0 */
423 struct tegra_sor_hdmi_settings *settings;
424 unsigned int num_settings;
425
426 struct regulator *avdd_io_supply;
427 struct regulator *vdd_pll_supply;
428 struct regulator *hdmi_supply;
429
430 struct delayed_work scdc;
431 bool scdc_enabled;
432
433 struct tegra_hda_format format;
434};
435
436struct tegra_sor_state {
437 struct drm_connector_state base;
438
439 unsigned int link_speed;
440 unsigned long pclk;
441 unsigned int bpc;
442};
443
444static inline struct tegra_sor_state *
445to_sor_state(struct drm_connector_state *state)
446{
447 return container_of(state, struct tegra_sor_state, base);
448}
449
450struct tegra_sor_config {
451 u32 bits_per_pixel;
452
453 u32 active_polarity;
454 u32 active_count;
455 u32 tu_size;
456 u32 active_frac;
457 u32 watermark;
458
459 u32 hblank_symbols;
460 u32 vblank_symbols;
461};
462
463static inline struct tegra_sor *
464host1x_client_to_sor(struct host1x_client *client)
465{
466 return container_of(client, struct tegra_sor, client);
467}
468
469static inline struct tegra_sor *to_sor(struct tegra_output *output)
470{
471 return container_of(output, struct tegra_sor, output);
472}
473
474static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
475{
476 u32 value = readl(sor->regs + (offset << 2));
477
478 trace_sor_readl(sor->dev, offset, value);
479
480 return value;
481}
482
483static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
484 unsigned int offset)
485{
486 trace_sor_writel(sor->dev, offset, value);
487 writel(value, sor->regs + (offset << 2));
488}
489
490static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
491{
492 int err;
493
494 clk_disable_unprepare(sor->clk);
495
496 err = clk_set_parent(sor->clk_out, parent);
497 if (err < 0)
498 return err;
499
500 err = clk_prepare_enable(sor->clk);
501 if (err < 0)
502 return err;
503
504 return 0;
505}
506
507struct tegra_clk_sor_pad {
508 struct clk_hw hw;
509 struct tegra_sor *sor;
510};
511
512static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
513{
514 return container_of(hw, struct tegra_clk_sor_pad, hw);
515}
516
517static const char * const tegra_clk_sor_pad_parents[] = {
518 "pll_d2_out0", "pll_dp"
519};
520
521static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
522{
523 struct tegra_clk_sor_pad *pad = to_pad(hw);
524 struct tegra_sor *sor = pad->sor;
525 u32 value;
526
527 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
528 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
529
530 switch (index) {
531 case 0:
532 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
533 break;
534
535 case 1:
536 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
537 break;
538 }
539
540 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
541
542 return 0;
543}
544
545static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
546{
547 struct tegra_clk_sor_pad *pad = to_pad(hw);
548 struct tegra_sor *sor = pad->sor;
549 u8 parent = U8_MAX;
550 u32 value;
551
552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
553
554 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
555 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
556 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
557 parent = 0;
558 break;
559
560 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
561 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
562 parent = 1;
563 break;
564 }
565
566 return parent;
567}
568
569static const struct clk_ops tegra_clk_sor_pad_ops = {
570 .set_parent = tegra_clk_sor_pad_set_parent,
571 .get_parent = tegra_clk_sor_pad_get_parent,
572};
573
574static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
575 const char *name)
576{
577 struct tegra_clk_sor_pad *pad;
578 struct clk_init_data init;
579 struct clk *clk;
580
581 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
582 if (!pad)
583 return ERR_PTR(-ENOMEM);
584
585 pad->sor = sor;
586
587 init.name = name;
588 init.flags = 0;
589 init.parent_names = tegra_clk_sor_pad_parents;
590 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
591 init.ops = &tegra_clk_sor_pad_ops;
592
593 pad->hw.init = &init;
594
595 clk = devm_clk_register(sor->dev, &pad->hw);
596
597 return clk;
598}
599
600static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
601 struct drm_dp_link *link)
602{
603 unsigned int i;
604 u8 pattern;
605 u32 value;
606 int err;
607
608 /* setup lane parameters */
609 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
610 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
611 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
612 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
613 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
614
615 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
616 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
617 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
618 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
619 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
620
621 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
622 SOR_LANE_POSTCURSOR_LANE2(0x00) |
623 SOR_LANE_POSTCURSOR_LANE1(0x00) |
624 SOR_LANE_POSTCURSOR_LANE0(0x00);
625 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
626
627 /* disable LVDS mode */
628 tegra_sor_writel(sor, 0, SOR_LVDS);
629
630 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
631 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
632 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
633 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
634 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
635
636 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
637 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
638 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
639 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
640
641 usleep_range(10, 100);
642
643 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
644 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
645 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
646 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
647
648 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
649 if (err < 0)
650 return err;
651
652 for (i = 0, value = 0; i < link->num_lanes; i++) {
653 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
654 SOR_DP_TPG_SCRAMBLER_NONE |
655 SOR_DP_TPG_PATTERN_TRAIN1;
656 value = (value << 8) | lane;
657 }
658
659 tegra_sor_writel(sor, value, SOR_DP_TPG);
660
661 pattern = DP_TRAINING_PATTERN_1;
662
663 err = drm_dp_aux_train(sor->aux, link, pattern);
664 if (err < 0)
665 return err;
666
667 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
668 value |= SOR_DP_SPARE_SEQ_ENABLE;
669 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
670 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
671 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
672
673 for (i = 0, value = 0; i < link->num_lanes; i++) {
674 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
675 SOR_DP_TPG_SCRAMBLER_NONE |
676 SOR_DP_TPG_PATTERN_TRAIN2;
677 value = (value << 8) | lane;
678 }
679
680 tegra_sor_writel(sor, value, SOR_DP_TPG);
681
682 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
683
684 err = drm_dp_aux_train(sor->aux, link, pattern);
685 if (err < 0)
686 return err;
687
688 for (i = 0, value = 0; i < link->num_lanes; i++) {
689 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
690 SOR_DP_TPG_SCRAMBLER_GALIOS |
691 SOR_DP_TPG_PATTERN_NONE;
692 value = (value << 8) | lane;
693 }
694
695 tegra_sor_writel(sor, value, SOR_DP_TPG);
696
697 pattern = DP_TRAINING_PATTERN_DISABLE;
698
699 err = drm_dp_aux_train(sor->aux, link, pattern);
700 if (err < 0)
701 return err;
702
703 return 0;
704}
705
706static void tegra_sor_super_update(struct tegra_sor *sor)
707{
708 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
709 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
710 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
711}
712
713static void tegra_sor_update(struct tegra_sor *sor)
714{
715 tegra_sor_writel(sor, 0, SOR_STATE0);
716 tegra_sor_writel(sor, 1, SOR_STATE0);
717 tegra_sor_writel(sor, 0, SOR_STATE0);
718}
719
720static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
721{
722 u32 value;
723
724 value = tegra_sor_readl(sor, SOR_PWM_DIV);
725 value &= ~SOR_PWM_DIV_MASK;
726 value |= 0x400; /* period */
727 tegra_sor_writel(sor, value, SOR_PWM_DIV);
728
729 value = tegra_sor_readl(sor, SOR_PWM_CTL);
730 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
731 value |= 0x400; /* duty cycle */
732 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
733 value |= SOR_PWM_CTL_TRIGGER;
734 tegra_sor_writel(sor, value, SOR_PWM_CTL);
735
736 timeout = jiffies + msecs_to_jiffies(timeout);
737
738 while (time_before(jiffies, timeout)) {
739 value = tegra_sor_readl(sor, SOR_PWM_CTL);
740 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
741 return 0;
742
743 usleep_range(25, 100);
744 }
745
746 return -ETIMEDOUT;
747}
748
749static int tegra_sor_attach(struct tegra_sor *sor)
750{
751 unsigned long value, timeout;
752
753 /* wake up in normal mode */
754 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
755 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
756 value |= SOR_SUPER_STATE_MODE_NORMAL;
757 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
758 tegra_sor_super_update(sor);
759
760 /* attach */
761 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
762 value |= SOR_SUPER_STATE_ATTACHED;
763 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
764 tegra_sor_super_update(sor);
765
766 timeout = jiffies + msecs_to_jiffies(250);
767
768 while (time_before(jiffies, timeout)) {
769 value = tegra_sor_readl(sor, SOR_TEST);
770 if ((value & SOR_TEST_ATTACHED) != 0)
771 return 0;
772
773 usleep_range(25, 100);
774 }
775
776 return -ETIMEDOUT;
777}
778
779static int tegra_sor_wakeup(struct tegra_sor *sor)
780{
781 unsigned long value, timeout;
782
783 timeout = jiffies + msecs_to_jiffies(250);
784
785 /* wait for head to wake up */
786 while (time_before(jiffies, timeout)) {
787 value = tegra_sor_readl(sor, SOR_TEST);
788 value &= SOR_TEST_HEAD_MODE_MASK;
789
790 if (value == SOR_TEST_HEAD_MODE_AWAKE)
791 return 0;
792
793 usleep_range(25, 100);
794 }
795
796 return -ETIMEDOUT;
797}
798
799static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
800{
801 u32 value;
802
803 value = tegra_sor_readl(sor, SOR_PWR);
804 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
805 tegra_sor_writel(sor, value, SOR_PWR);
806
807 timeout = jiffies + msecs_to_jiffies(timeout);
808
809 while (time_before(jiffies, timeout)) {
810 value = tegra_sor_readl(sor, SOR_PWR);
811 if ((value & SOR_PWR_TRIGGER) == 0)
812 return 0;
813
814 usleep_range(25, 100);
815 }
816
817 return -ETIMEDOUT;
818}
819
820struct tegra_sor_params {
821 /* number of link clocks per line */
822 unsigned int num_clocks;
823 /* ratio between input and output */
824 u64 ratio;
825 /* precision factor */
826 u64 precision;
827
828 unsigned int active_polarity;
829 unsigned int active_count;
830 unsigned int active_frac;
831 unsigned int tu_size;
832 unsigned int error;
833};
834
835static int tegra_sor_compute_params(struct tegra_sor *sor,
836 struct tegra_sor_params *params,
837 unsigned int tu_size)
838{
839 u64 active_sym, active_count, frac, approx;
840 u32 active_polarity, active_frac = 0;
841 const u64 f = params->precision;
842 s64 error;
843
844 active_sym = params->ratio * tu_size;
845 active_count = div_u64(active_sym, f) * f;
846 frac = active_sym - active_count;
847
848 /* fraction < 0.5 */
849 if (frac >= (f / 2)) {
850 active_polarity = 1;
851 frac = f - frac;
852 } else {
853 active_polarity = 0;
854 }
855
856 if (frac != 0) {
857 frac = div_u64(f * f, frac); /* 1/fraction */
858 if (frac <= (15 * f)) {
859 active_frac = div_u64(frac, f);
860
861 /* round up */
862 if (active_polarity)
863 active_frac++;
864 } else {
865 active_frac = active_polarity ? 1 : 15;
866 }
867 }
868
869 if (active_frac == 1)
870 active_polarity = 0;
871
872 if (active_polarity == 1) {
873 if (active_frac) {
874 approx = active_count + (active_frac * (f - 1)) * f;
875 approx = div_u64(approx, active_frac * f);
876 } else {
877 approx = active_count + f;
878 }
879 } else {
880 if (active_frac)
881 approx = active_count + div_u64(f, active_frac);
882 else
883 approx = active_count;
884 }
885
886 error = div_s64(active_sym - approx, tu_size);
887 error *= params->num_clocks;
888
889 if (error <= 0 && abs(error) < params->error) {
890 params->active_count = div_u64(active_count, f);
891 params->active_polarity = active_polarity;
892 params->active_frac = active_frac;
893 params->error = abs(error);
894 params->tu_size = tu_size;
895
896 if (error == 0)
897 return true;
898 }
899
900 return false;
901}
902
903static int tegra_sor_compute_config(struct tegra_sor *sor,
904 const struct drm_display_mode *mode,
905 struct tegra_sor_config *config,
906 struct drm_dp_link *link)
907{
908 const u64 f = 100000, link_rate = link->rate * 1000;
909 const u64 pclk = (u64)mode->clock * 1000;
910 u64 input, output, watermark, num;
911 struct tegra_sor_params params;
912 u32 num_syms_per_line;
913 unsigned int i;
914
915 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
916 return -EINVAL;
917
918 output = link_rate * 8 * link->num_lanes;
919 input = pclk * config->bits_per_pixel;
920
921 if (input >= output)
922 return -ERANGE;
923
924 memset(&params, 0, sizeof(params));
925 params.ratio = div64_u64(input * f, output);
926 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
927 params.precision = f;
928 params.error = 64 * f;
929 params.tu_size = 64;
930
931 for (i = params.tu_size; i >= 32; i--)
932 if (tegra_sor_compute_params(sor, &params, i))
933 break;
934
935 if (params.active_frac == 0) {
936 config->active_polarity = 0;
937 config->active_count = params.active_count;
938
939 if (!params.active_polarity)
940 config->active_count--;
941
942 config->tu_size = params.tu_size;
943 config->active_frac = 1;
944 } else {
945 config->active_polarity = params.active_polarity;
946 config->active_count = params.active_count;
947 config->active_frac = params.active_frac;
948 config->tu_size = params.tu_size;
949 }
950
951 dev_dbg(sor->dev,
952 "polarity: %d active count: %d tu size: %d active frac: %d\n",
953 config->active_polarity, config->active_count,
954 config->tu_size, config->active_frac);
955
956 watermark = params.ratio * config->tu_size * (f - params.ratio);
957 watermark = div_u64(watermark, f);
958
959 watermark = div_u64(watermark + params.error, f);
960 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
961 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
962 (link->num_lanes * 8);
963
964 if (config->watermark > 30) {
965 config->watermark = 30;
966 dev_err(sor->dev,
967 "unable to compute TU size, forcing watermark to %u\n",
968 config->watermark);
969 } else if (config->watermark > num_syms_per_line) {
970 config->watermark = num_syms_per_line;
971 dev_err(sor->dev, "watermark too high, forcing to %u\n",
972 config->watermark);
973 }
974
975 /* compute the number of symbols per horizontal blanking interval */
976 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
977 config->hblank_symbols = div_u64(num, pclk);
978
979 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
980 config->hblank_symbols -= 3;
981
982 config->hblank_symbols -= 12 / link->num_lanes;
983
984 /* compute the number of symbols per vertical blanking interval */
985 num = (mode->hdisplay - 25) * link_rate;
986 config->vblank_symbols = div_u64(num, pclk);
987 config->vblank_symbols -= 36 / link->num_lanes + 4;
988
989 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
990 config->vblank_symbols);
991
992 return 0;
993}
994
995static void tegra_sor_apply_config(struct tegra_sor *sor,
996 const struct tegra_sor_config *config)
997{
998 u32 value;
999
1000 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1001 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1002 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1003 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1004
1005 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1006 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1007 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1008
1009 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1010 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1011
1012 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1013 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1014
1015 if (config->active_polarity)
1016 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1017 else
1018 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1019
1020 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1021 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1022 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1023
1024 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1025 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1026 value |= config->hblank_symbols & 0xffff;
1027 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1028
1029 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1030 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1031 value |= config->vblank_symbols & 0xffff;
1032 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1033}
1034
1035static void tegra_sor_mode_set(struct tegra_sor *sor,
1036 const struct drm_display_mode *mode,
1037 struct tegra_sor_state *state)
1038{
1039 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1040 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1041 u32 value;
1042
1043 value = tegra_sor_readl(sor, SOR_STATE1);
1044 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1045 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1046 value &= ~SOR_STATE_ASY_OWNER_MASK;
1047
1048 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1049 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1050
1051 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1052 value &= ~SOR_STATE_ASY_HSYNCPOL;
1053
1054 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1055 value |= SOR_STATE_ASY_HSYNCPOL;
1056
1057 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1058 value &= ~SOR_STATE_ASY_VSYNCPOL;
1059
1060 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1061 value |= SOR_STATE_ASY_VSYNCPOL;
1062
1063 switch (state->bpc) {
1064 case 16:
1065 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1066 break;
1067
1068 case 12:
1069 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1070 break;
1071
1072 case 10:
1073 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1074 break;
1075
1076 case 8:
1077 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1078 break;
1079
1080 case 6:
1081 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1082 break;
1083
1084 default:
1085 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1086 break;
1087 }
1088
1089 tegra_sor_writel(sor, value, SOR_STATE1);
1090
1091 /*
1092 * TODO: The video timing programming below doesn't seem to match the
1093 * register definitions.
1094 */
1095
1096 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1097 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1098
1099 /* sync end = sync width - 1 */
1100 vse = mode->vsync_end - mode->vsync_start - 1;
1101 hse = mode->hsync_end - mode->hsync_start - 1;
1102
1103 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1104 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1105
1106 /* blank end = sync end + back porch */
1107 vbe = vse + (mode->vtotal - mode->vsync_end);
1108 hbe = hse + (mode->htotal - mode->hsync_end);
1109
1110 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1111 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1112
1113 /* blank start = blank end + active */
1114 vbs = vbe + mode->vdisplay;
1115 hbs = hbe + mode->hdisplay;
1116
1117 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1118 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1119
1120 /* XXX interlacing support */
1121 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1122}
1123
1124static int tegra_sor_detach(struct tegra_sor *sor)
1125{
1126 unsigned long value, timeout;
1127
1128 /* switch to safe mode */
1129 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1130 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1131 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1132 tegra_sor_super_update(sor);
1133
1134 timeout = jiffies + msecs_to_jiffies(250);
1135
1136 while (time_before(jiffies, timeout)) {
1137 value = tegra_sor_readl(sor, SOR_PWR);
1138 if (value & SOR_PWR_MODE_SAFE)
1139 break;
1140 }
1141
1142 if ((value & SOR_PWR_MODE_SAFE) == 0)
1143 return -ETIMEDOUT;
1144
1145 /* go to sleep */
1146 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1147 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1148 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1149 tegra_sor_super_update(sor);
1150
1151 /* detach */
1152 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1153 value &= ~SOR_SUPER_STATE_ATTACHED;
1154 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1155 tegra_sor_super_update(sor);
1156
1157 timeout = jiffies + msecs_to_jiffies(250);
1158
1159 while (time_before(jiffies, timeout)) {
1160 value = tegra_sor_readl(sor, SOR_TEST);
1161 if ((value & SOR_TEST_ATTACHED) == 0)
1162 break;
1163
1164 usleep_range(25, 100);
1165 }
1166
1167 if ((value & SOR_TEST_ATTACHED) != 0)
1168 return -ETIMEDOUT;
1169
1170 return 0;
1171}
1172
1173static int tegra_sor_power_down(struct tegra_sor *sor)
1174{
1175 unsigned long value, timeout;
1176 int err;
1177
1178 value = tegra_sor_readl(sor, SOR_PWR);
1179 value &= ~SOR_PWR_NORMAL_STATE_PU;
1180 value |= SOR_PWR_TRIGGER;
1181 tegra_sor_writel(sor, value, SOR_PWR);
1182
1183 timeout = jiffies + msecs_to_jiffies(250);
1184
1185 while (time_before(jiffies, timeout)) {
1186 value = tegra_sor_readl(sor, SOR_PWR);
1187 if ((value & SOR_PWR_TRIGGER) == 0)
1188 return 0;
1189
1190 usleep_range(25, 100);
1191 }
1192
1193 if ((value & SOR_PWR_TRIGGER) != 0)
1194 return -ETIMEDOUT;
1195
1196 /* switch to safe parent clock */
1197 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1198 if (err < 0) {
1199 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1200 return err;
1201 }
1202
1203 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1204 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1205 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1206 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1207
1208 /* stop lane sequencer */
1209 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1210 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1211 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1212
1213 timeout = jiffies + msecs_to_jiffies(250);
1214
1215 while (time_before(jiffies, timeout)) {
1216 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1217 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1218 break;
1219
1220 usleep_range(25, 100);
1221 }
1222
1223 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1224 return -ETIMEDOUT;
1225
1226 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1227 value |= SOR_PLL2_PORT_POWERDOWN;
1228 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1229
1230 usleep_range(20, 100);
1231
1232 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1233 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1234 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1235
1236 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1237 value |= SOR_PLL2_SEQ_PLLCAPPD;
1238 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1239 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1240
1241 usleep_range(20, 100);
1242
1243 return 0;
1244}
1245
1246static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1247{
1248 u32 value;
1249
1250 timeout = jiffies + msecs_to_jiffies(timeout);
1251
1252 while (time_before(jiffies, timeout)) {
1253 value = tegra_sor_readl(sor, SOR_CRCA);
1254 if (value & SOR_CRCA_VALID)
1255 return 0;
1256
1257 usleep_range(100, 200);
1258 }
1259
1260 return -ETIMEDOUT;
1261}
1262
1263static int tegra_sor_show_crc(struct seq_file *s, void *data)
1264{
1265 struct drm_info_node *node = s->private;
1266 struct tegra_sor *sor = node->info_ent->data;
1267 struct drm_crtc *crtc = sor->output.encoder.crtc;
1268 struct drm_device *drm = node->minor->dev;
1269 int err = 0;
1270 u32 value;
1271
1272 drm_modeset_lock_all(drm);
1273
1274 if (!crtc || !crtc->state->active) {
1275 err = -EBUSY;
1276 goto unlock;
1277 }
1278
1279 value = tegra_sor_readl(sor, SOR_STATE1);
1280 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1281 tegra_sor_writel(sor, value, SOR_STATE1);
1282
1283 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1284 value |= SOR_CRC_CNTRL_ENABLE;
1285 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1286
1287 value = tegra_sor_readl(sor, SOR_TEST);
1288 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1289 tegra_sor_writel(sor, value, SOR_TEST);
1290
1291 err = tegra_sor_crc_wait(sor, 100);
1292 if (err < 0)
1293 goto unlock;
1294
1295 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1296 value = tegra_sor_readl(sor, SOR_CRCB);
1297
1298 seq_printf(s, "%08x\n", value);
1299
1300unlock:
1301 drm_modeset_unlock_all(drm);
1302 return err;
1303}
1304
1305#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1306
1307static const struct debugfs_reg32 tegra_sor_regs[] = {
1308 DEBUGFS_REG32(SOR_CTXSW),
1309 DEBUGFS_REG32(SOR_SUPER_STATE0),
1310 DEBUGFS_REG32(SOR_SUPER_STATE1),
1311 DEBUGFS_REG32(SOR_STATE0),
1312 DEBUGFS_REG32(SOR_STATE1),
1313 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1314 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1315 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1316 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1317 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1318 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1319 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1320 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1321 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1322 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1323 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1324 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1325 DEBUGFS_REG32(SOR_CRC_CNTRL),
1326 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1327 DEBUGFS_REG32(SOR_CLK_CNTRL),
1328 DEBUGFS_REG32(SOR_CAP),
1329 DEBUGFS_REG32(SOR_PWR),
1330 DEBUGFS_REG32(SOR_TEST),
1331 DEBUGFS_REG32(SOR_PLL0),
1332 DEBUGFS_REG32(SOR_PLL1),
1333 DEBUGFS_REG32(SOR_PLL2),
1334 DEBUGFS_REG32(SOR_PLL3),
1335 DEBUGFS_REG32(SOR_CSTM),
1336 DEBUGFS_REG32(SOR_LVDS),
1337 DEBUGFS_REG32(SOR_CRCA),
1338 DEBUGFS_REG32(SOR_CRCB),
1339 DEBUGFS_REG32(SOR_BLANK),
1340 DEBUGFS_REG32(SOR_SEQ_CTL),
1341 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1342 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1343 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1344 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1345 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1346 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1347 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1348 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1349 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1350 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1351 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1352 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1353 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1354 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1355 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1356 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1357 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1358 DEBUGFS_REG32(SOR_PWM_DIV),
1359 DEBUGFS_REG32(SOR_PWM_CTL),
1360 DEBUGFS_REG32(SOR_VCRC_A0),
1361 DEBUGFS_REG32(SOR_VCRC_A1),
1362 DEBUGFS_REG32(SOR_VCRC_B0),
1363 DEBUGFS_REG32(SOR_VCRC_B1),
1364 DEBUGFS_REG32(SOR_CCRC_A0),
1365 DEBUGFS_REG32(SOR_CCRC_A1),
1366 DEBUGFS_REG32(SOR_CCRC_B0),
1367 DEBUGFS_REG32(SOR_CCRC_B1),
1368 DEBUGFS_REG32(SOR_EDATA_A0),
1369 DEBUGFS_REG32(SOR_EDATA_A1),
1370 DEBUGFS_REG32(SOR_EDATA_B0),
1371 DEBUGFS_REG32(SOR_EDATA_B1),
1372 DEBUGFS_REG32(SOR_COUNT_A0),
1373 DEBUGFS_REG32(SOR_COUNT_A1),
1374 DEBUGFS_REG32(SOR_COUNT_B0),
1375 DEBUGFS_REG32(SOR_COUNT_B1),
1376 DEBUGFS_REG32(SOR_DEBUG_A0),
1377 DEBUGFS_REG32(SOR_DEBUG_A1),
1378 DEBUGFS_REG32(SOR_DEBUG_B0),
1379 DEBUGFS_REG32(SOR_DEBUG_B1),
1380 DEBUGFS_REG32(SOR_TRIG),
1381 DEBUGFS_REG32(SOR_MSCHECK),
1382 DEBUGFS_REG32(SOR_XBAR_CTRL),
1383 DEBUGFS_REG32(SOR_XBAR_POL),
1384 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1385 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1386 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1387 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1388 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1389 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1390 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1391 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1392 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1393 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1394 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1395 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1396 DEBUGFS_REG32(SOR_DP_CONFIG0),
1397 DEBUGFS_REG32(SOR_DP_CONFIG1),
1398 DEBUGFS_REG32(SOR_DP_MN0),
1399 DEBUGFS_REG32(SOR_DP_MN1),
1400 DEBUGFS_REG32(SOR_DP_PADCTL0),
1401 DEBUGFS_REG32(SOR_DP_PADCTL1),
1402 DEBUGFS_REG32(SOR_DP_PADCTL2),
1403 DEBUGFS_REG32(SOR_DP_DEBUG0),
1404 DEBUGFS_REG32(SOR_DP_DEBUG1),
1405 DEBUGFS_REG32(SOR_DP_SPARE0),
1406 DEBUGFS_REG32(SOR_DP_SPARE1),
1407 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1408 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1409 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1410 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1411 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1415 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1416 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1417 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1418 DEBUGFS_REG32(SOR_DP_TPG),
1419 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1420 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1421 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1422 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1423};
1424
1425static int tegra_sor_show_regs(struct seq_file *s, void *data)
1426{
1427 struct drm_info_node *node = s->private;
1428 struct tegra_sor *sor = node->info_ent->data;
1429 struct drm_crtc *crtc = sor->output.encoder.crtc;
1430 struct drm_device *drm = node->minor->dev;
1431 unsigned int i;
1432 int err = 0;
1433
1434 drm_modeset_lock_all(drm);
1435
1436 if (!crtc || !crtc->state->active) {
1437 err = -EBUSY;
1438 goto unlock;
1439 }
1440
1441 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1442 unsigned int offset = tegra_sor_regs[i].offset;
1443
1444 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1445 offset, tegra_sor_readl(sor, offset));
1446 }
1447
1448unlock:
1449 drm_modeset_unlock_all(drm);
1450 return err;
1451}
1452
1453static const struct drm_info_list debugfs_files[] = {
1454 { "crc", tegra_sor_show_crc, 0, NULL },
1455 { "regs", tegra_sor_show_regs, 0, NULL },
1456};
1457
1458static int tegra_sor_late_register(struct drm_connector *connector)
1459{
1460 struct tegra_output *output = connector_to_output(connector);
1461 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1462 struct drm_minor *minor = connector->dev->primary;
1463 struct dentry *root = connector->debugfs_entry;
1464 struct tegra_sor *sor = to_sor(output);
1465 int err;
1466
1467 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1468 GFP_KERNEL);
1469 if (!sor->debugfs_files)
1470 return -ENOMEM;
1471
1472 for (i = 0; i < count; i++)
1473 sor->debugfs_files[i].data = sor;
1474
1475 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1476 if (err < 0)
1477 goto free;
1478
1479 return 0;
1480
1481free:
1482 kfree(sor->debugfs_files);
1483 sor->debugfs_files = NULL;
1484
1485 return err;
1486}
1487
1488static void tegra_sor_early_unregister(struct drm_connector *connector)
1489{
1490 struct tegra_output *output = connector_to_output(connector);
1491 unsigned int count = ARRAY_SIZE(debugfs_files);
1492 struct tegra_sor *sor = to_sor(output);
1493
1494 drm_debugfs_remove_files(sor->debugfs_files, count,
1495 connector->dev->primary);
1496 kfree(sor->debugfs_files);
1497 sor->debugfs_files = NULL;
1498}
1499
1500static void tegra_sor_connector_reset(struct drm_connector *connector)
1501{
1502 struct tegra_sor_state *state;
1503
1504 state = kzalloc(sizeof(*state), GFP_KERNEL);
1505 if (!state)
1506 return;
1507
1508 if (connector->state) {
1509 __drm_atomic_helper_connector_destroy_state(connector->state);
1510 kfree(connector->state);
1511 }
1512
1513 __drm_atomic_helper_connector_reset(connector, &state->base);
1514}
1515
1516static enum drm_connector_status
1517tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1518{
1519 struct tegra_output *output = connector_to_output(connector);
1520 struct tegra_sor *sor = to_sor(output);
1521
1522 if (sor->aux)
1523 return drm_dp_aux_detect(sor->aux);
1524
1525 return tegra_output_connector_detect(connector, force);
1526}
1527
1528static struct drm_connector_state *
1529tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1530{
1531 struct tegra_sor_state *state = to_sor_state(connector->state);
1532 struct tegra_sor_state *copy;
1533
1534 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1535 if (!copy)
1536 return NULL;
1537
1538 __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1539
1540 return &copy->base;
1541}
1542
1543static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1544 .reset = tegra_sor_connector_reset,
1545 .detect = tegra_sor_connector_detect,
1546 .fill_modes = drm_helper_probe_single_connector_modes,
1547 .destroy = tegra_output_connector_destroy,
1548 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1549 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1550 .late_register = tegra_sor_late_register,
1551 .early_unregister = tegra_sor_early_unregister,
1552};
1553
1554static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1555{
1556 struct tegra_output *output = connector_to_output(connector);
1557 struct tegra_sor *sor = to_sor(output);
1558 int err;
1559
1560 if (sor->aux)
1561 drm_dp_aux_enable(sor->aux);
1562
1563 err = tegra_output_connector_get_modes(connector);
1564
1565 if (sor->aux)
1566 drm_dp_aux_disable(sor->aux);
1567
1568 return err;
1569}
1570
1571static enum drm_mode_status
1572tegra_sor_connector_mode_valid(struct drm_connector *connector,
1573 struct drm_display_mode *mode)
1574{
1575 return MODE_OK;
1576}
1577
1578static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1579 .get_modes = tegra_sor_connector_get_modes,
1580 .mode_valid = tegra_sor_connector_mode_valid,
1581};
1582
1583static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1584 .destroy = tegra_output_encoder_destroy,
1585};
1586
1587static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1588{
1589 struct tegra_output *output = encoder_to_output(encoder);
1590 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1591 struct tegra_sor *sor = to_sor(output);
1592 u32 value;
1593 int err;
1594
1595 if (output->panel)
1596 drm_panel_disable(output->panel);
1597
1598 err = tegra_sor_detach(sor);
1599 if (err < 0)
1600 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1601
1602 tegra_sor_writel(sor, 0, SOR_STATE1);
1603 tegra_sor_update(sor);
1604
1605 /*
1606 * The following accesses registers of the display controller, so make
1607 * sure it's only executed when the output is attached to one.
1608 */
1609 if (dc) {
1610 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1611 value &= ~SOR_ENABLE(0);
1612 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1613
1614 tegra_dc_commit(dc);
1615 }
1616
1617 err = tegra_sor_power_down(sor);
1618 if (err < 0)
1619 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1620
1621 if (sor->aux) {
1622 err = drm_dp_aux_disable(sor->aux);
1623 if (err < 0)
1624 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1625 }
1626
1627 err = tegra_io_pad_power_disable(sor->pad);
1628 if (err < 0)
1629 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1630
1631 if (output->panel)
1632 drm_panel_unprepare(output->panel);
1633
1634 pm_runtime_put(sor->dev);
1635}
1636
1637#if 0
1638static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1639 unsigned int *value)
1640{
1641 unsigned int hfp, hsw, hbp, a = 0, b;
1642
1643 hfp = mode->hsync_start - mode->hdisplay;
1644 hsw = mode->hsync_end - mode->hsync_start;
1645 hbp = mode->htotal - mode->hsync_end;
1646
1647 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1648
1649 b = hfp - 1;
1650
1651 pr_info("a: %u, b: %u\n", a, b);
1652 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1653
1654 if (a + hsw + hbp <= 11) {
1655 a = 1 + 11 - hsw - hbp;
1656 pr_info("a: %u\n", a);
1657 }
1658
1659 if (a > b)
1660 return -EINVAL;
1661
1662 if (hsw < 1)
1663 return -EINVAL;
1664
1665 if (mode->hdisplay < 16)
1666 return -EINVAL;
1667
1668 if (value) {
1669 if (b > a && a % 2)
1670 *value = a + 1;
1671 else
1672 *value = a;
1673 }
1674
1675 return 0;
1676}
1677#endif
1678
1679static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1680{
1681 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1682 struct tegra_output *output = encoder_to_output(encoder);
1683 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1684 struct tegra_sor *sor = to_sor(output);
1685 struct tegra_sor_config config;
1686 struct tegra_sor_state *state;
1687 struct drm_dp_link link;
1688 u8 rate, lanes;
1689 unsigned int i;
1690 int err = 0;
1691 u32 value;
1692
1693 state = to_sor_state(output->connector.state);
1694
1695 pm_runtime_get_sync(sor->dev);
1696
1697 if (output->panel)
1698 drm_panel_prepare(output->panel);
1699
1700 err = drm_dp_aux_enable(sor->aux);
1701 if (err < 0)
1702 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1703
1704 err = drm_dp_link_probe(sor->aux, &link);
1705 if (err < 0) {
1706 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1707 return;
1708 }
1709
1710 /* switch to safe parent clock */
1711 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1712 if (err < 0)
1713 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1714
1715 memset(&config, 0, sizeof(config));
1716 config.bits_per_pixel = state->bpc * 3;
1717
1718 err = tegra_sor_compute_config(sor, mode, &config, &link);
1719 if (err < 0)
1720 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1721
1722 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1723 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1724 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1725 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1726
1727 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1728 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1729 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1730 usleep_range(20, 100);
1731
1732 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1733 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1734 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1735
1736 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1737 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1739
1740 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1741 value |= SOR_PLL2_SEQ_PLLCAPPD;
1742 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1743 value |= SOR_PLL2_LVDS_ENABLE;
1744 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1745
1746 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1747 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1748
1749 while (true) {
1750 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1751 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1752 break;
1753
1754 usleep_range(250, 1000);
1755 }
1756
1757 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1758 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1759 value &= ~SOR_PLL2_PORT_POWERDOWN;
1760 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1761
1762 /*
1763 * power up
1764 */
1765
1766 /* set safe link bandwidth (1.62 Gbps) */
1767 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1768 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1769 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1770 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1771
1772 /* step 1 */
1773 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1774 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1775 SOR_PLL2_BANDGAP_POWERDOWN;
1776 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1777
1778 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1779 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1780 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1781
1782 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1783 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1784 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1785
1786 /* step 2 */
1787 err = tegra_io_pad_power_enable(sor->pad);
1788 if (err < 0)
1789 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1790
1791 usleep_range(5, 100);
1792
1793 /* step 3 */
1794 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1795 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1796 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1797
1798 usleep_range(20, 100);
1799
1800 /* step 4 */
1801 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1802 value &= ~SOR_PLL0_VCOPD;
1803 value &= ~SOR_PLL0_PWR;
1804 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1805
1806 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1807 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1808 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1809
1810 usleep_range(200, 1000);
1811
1812 /* step 5 */
1813 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1814 value &= ~SOR_PLL2_PORT_POWERDOWN;
1815 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1816
1817 /* XXX not in TRM */
1818 for (value = 0, i = 0; i < 5; i++)
1819 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1820 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1821
1822 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1823 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1824
1825 /* switch to DP parent clock */
1826 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1827 if (err < 0)
1828 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1829
1830 /* power DP lanes */
1831 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1832
1833 if (link.num_lanes <= 2)
1834 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1835 else
1836 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1837
1838 if (link.num_lanes <= 1)
1839 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1840 else
1841 value |= SOR_DP_PADCTL_PD_TXD_1;
1842
1843 if (link.num_lanes == 0)
1844 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1845 else
1846 value |= SOR_DP_PADCTL_PD_TXD_0;
1847
1848 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1849
1850 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1851 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1852 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1853 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1854
1855 /* start lane sequencer */
1856 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1857 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1858 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1859
1860 while (true) {
1861 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1862 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1863 break;
1864
1865 usleep_range(250, 1000);
1866 }
1867
1868 /* set link bandwidth */
1869 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1870 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1871 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1872 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1873
1874 tegra_sor_apply_config(sor, &config);
1875
1876 /* enable link */
1877 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1878 value |= SOR_DP_LINKCTL_ENABLE;
1879 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1880 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1881
1882 for (i = 0, value = 0; i < 4; i++) {
1883 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1884 SOR_DP_TPG_SCRAMBLER_GALIOS |
1885 SOR_DP_TPG_PATTERN_NONE;
1886 value = (value << 8) | lane;
1887 }
1888
1889 tegra_sor_writel(sor, value, SOR_DP_TPG);
1890
1891 /* enable pad calibration logic */
1892 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1893 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1894 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1895
1896 err = drm_dp_link_probe(sor->aux, &link);
1897 if (err < 0)
1898 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1899
1900 err = drm_dp_link_power_up(sor->aux, &link);
1901 if (err < 0)
1902 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1903
1904 err = drm_dp_link_configure(sor->aux, &link);
1905 if (err < 0)
1906 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1907
1908 rate = drm_dp_link_rate_to_bw_code(link.rate);
1909 lanes = link.num_lanes;
1910
1911 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1912 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1913 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1914 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1915
1916 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1917 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1918 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1919
1920 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1921 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1922
1923 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1924
1925 /* disable training pattern generator */
1926
1927 for (i = 0; i < link.num_lanes; i++) {
1928 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1929 SOR_DP_TPG_SCRAMBLER_GALIOS |
1930 SOR_DP_TPG_PATTERN_NONE;
1931 value = (value << 8) | lane;
1932 }
1933
1934 tegra_sor_writel(sor, value, SOR_DP_TPG);
1935
1936 err = tegra_sor_dp_train_fast(sor, &link);
1937 if (err < 0)
1938 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1939
1940 dev_dbg(sor->dev, "fast link training succeeded\n");
1941
1942 err = tegra_sor_power_up(sor, 250);
1943 if (err < 0)
1944 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1945
1946 /* CSTM (LVDS, link A/B, upper) */
1947 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1948 SOR_CSTM_UPPER;
1949 tegra_sor_writel(sor, value, SOR_CSTM);
1950
1951 /* use DP-A protocol */
1952 value = tegra_sor_readl(sor, SOR_STATE1);
1953 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1954 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1955 tegra_sor_writel(sor, value, SOR_STATE1);
1956
1957 tegra_sor_mode_set(sor, mode, state);
1958
1959 /* PWM setup */
1960 err = tegra_sor_setup_pwm(sor, 250);
1961 if (err < 0)
1962 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1963
1964 tegra_sor_update(sor);
1965
1966 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1967 value |= SOR_ENABLE(0);
1968 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1969
1970 tegra_dc_commit(dc);
1971
1972 err = tegra_sor_attach(sor);
1973 if (err < 0)
1974 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1975
1976 err = tegra_sor_wakeup(sor);
1977 if (err < 0)
1978 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1979
1980 if (output->panel)
1981 drm_panel_enable(output->panel);
1982}
1983
1984static int
1985tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1986 struct drm_crtc_state *crtc_state,
1987 struct drm_connector_state *conn_state)
1988{
1989 struct tegra_output *output = encoder_to_output(encoder);
1990 struct tegra_sor_state *state = to_sor_state(conn_state);
1991 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1992 unsigned long pclk = crtc_state->mode.clock * 1000;
1993 struct tegra_sor *sor = to_sor(output);
1994 struct drm_display_info *info;
1995 int err;
1996
1997 info = &output->connector.display_info;
1998
1999 /*
2000 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2001 * the pixel clock must be corrected accordingly.
2002 */
2003 if (pclk >= 340000000) {
2004 state->link_speed = 20;
2005 state->pclk = pclk / 2;
2006 } else {
2007 state->link_speed = 10;
2008 state->pclk = pclk;
2009 }
2010
2011 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2012 pclk, 0);
2013 if (err < 0) {
2014 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2015 return err;
2016 }
2017
2018 switch (info->bpc) {
2019 case 8:
2020 case 6:
2021 state->bpc = info->bpc;
2022 break;
2023
2024 default:
2025 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2026 state->bpc = 8;
2027 break;
2028 }
2029
2030 return 0;
2031}
2032
2033static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2034 .disable = tegra_sor_edp_disable,
2035 .enable = tegra_sor_edp_enable,
2036 .atomic_check = tegra_sor_encoder_atomic_check,
2037};
2038
2039static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2040{
2041 u32 value = 0;
2042 size_t i;
2043
2044 for (i = size; i > 0; i--)
2045 value = (value << 8) | ptr[i - 1];
2046
2047 return value;
2048}
2049
2050static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2051 const void *data, size_t size)
2052{
2053 const u8 *ptr = data;
2054 unsigned long offset;
2055 size_t i, j;
2056 u32 value;
2057
2058 switch (ptr[0]) {
2059 case HDMI_INFOFRAME_TYPE_AVI:
2060 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2061 break;
2062
2063 case HDMI_INFOFRAME_TYPE_AUDIO:
2064 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2065 break;
2066
2067 case HDMI_INFOFRAME_TYPE_VENDOR:
2068 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2069 break;
2070
2071 default:
2072 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2073 ptr[0]);
2074 return;
2075 }
2076
2077 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2078 INFOFRAME_HEADER_VERSION(ptr[1]) |
2079 INFOFRAME_HEADER_LEN(ptr[2]);
2080 tegra_sor_writel(sor, value, offset);
2081 offset++;
2082
2083 /*
2084 * Each subpack contains 7 bytes, divided into:
2085 * - subpack_low: bytes 0 - 3
2086 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2087 */
2088 for (i = 3, j = 0; i < size; i += 7, j += 8) {
2089 size_t rem = size - i, num = min_t(size_t, rem, 4);
2090
2091 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2092 tegra_sor_writel(sor, value, offset++);
2093
2094 num = min_t(size_t, rem - num, 3);
2095
2096 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2097 tegra_sor_writel(sor, value, offset++);
2098 }
2099}
2100
2101static int
2102tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2103 const struct drm_display_mode *mode)
2104{
2105 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2106 struct hdmi_avi_infoframe frame;
2107 u32 value;
2108 int err;
2109
2110 /* disable AVI infoframe */
2111 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2112 value &= ~INFOFRAME_CTRL_SINGLE;
2113 value &= ~INFOFRAME_CTRL_OTHER;
2114 value &= ~INFOFRAME_CTRL_ENABLE;
2115 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2116
2117 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2118 &sor->output.connector, mode);
2119 if (err < 0) {
2120 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2121 return err;
2122 }
2123
2124 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2125 if (err < 0) {
2126 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2127 return err;
2128 }
2129
2130 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2131
2132 /* enable AVI infoframe */
2133 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2134 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2135 value |= INFOFRAME_CTRL_ENABLE;
2136 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2137
2138 return 0;
2139}
2140
2141static void tegra_sor_write_eld(struct tegra_sor *sor)
2142{
2143 size_t length = drm_eld_size(sor->output.connector.eld), i;
2144
2145 for (i = 0; i < length; i++)
2146 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2147 SOR_AUDIO_HDA_ELD_BUFWR);
2148
2149 /*
2150 * The HDA codec will always report an ELD buffer size of 96 bytes and
2151 * the HDA codec driver will check that each byte read from the buffer
2152 * is valid. Therefore every byte must be written, even if no 96 bytes
2153 * were parsed from EDID.
2154 */
2155 for (i = length; i < 96; i++)
2156 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2157}
2158
2159static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2160{
2161 u32 value;
2162
2163 tegra_sor_write_eld(sor);
2164
2165 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2166 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2167}
2168
2169static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2170{
2171 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2172}
2173
2174static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2175{
2176 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2177 struct hdmi_audio_infoframe frame;
2178 u32 value;
2179 int err;
2180
2181 err = hdmi_audio_infoframe_init(&frame);
2182 if (err < 0) {
2183 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2184 return err;
2185 }
2186
2187 frame.channels = sor->format.channels;
2188
2189 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2190 if (err < 0) {
2191 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2192 return err;
2193 }
2194
2195 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2196
2197 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2198 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2199 value |= INFOFRAME_CTRL_ENABLE;
2200 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2201
2202 return 0;
2203}
2204
2205static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2206{
2207 u32 value;
2208
2209 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2210
2211 /* select HDA audio input */
2212 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2213 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2214
2215 /* inject null samples */
2216 if (sor->format.channels != 2)
2217 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2218 else
2219 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2220
2221 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2222
2223 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2224
2225 /* enable advertising HBR capability */
2226 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2227
2228 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2229
2230 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2231 SOR_HDMI_SPARE_CTS_RESET(1) |
2232 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2233 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2234
2235 /* enable HW CTS */
2236 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2237 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2238
2239 /* allow packet to be sent */
2240 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2241 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2242
2243 /* reset N counter and enable lookup */
2244 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2245 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2246
2247 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2248 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2249 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2250
2251 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2252 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2253
2254 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2255 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2256
2257 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2258 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2259
2260 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2261 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2262 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2263
2264 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2265 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2266 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2267
2268 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2269 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2270 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2271
2272 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2273 value &= ~SOR_HDMI_AUDIO_N_RESET;
2274 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2275
2276 tegra_sor_hdmi_enable_audio_infoframe(sor);
2277}
2278
2279static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2280{
2281 u32 value;
2282
2283 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2284 value &= ~INFOFRAME_CTRL_ENABLE;
2285 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2286}
2287
2288static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2289{
2290 tegra_sor_hdmi_disable_audio_infoframe(sor);
2291}
2292
2293static struct tegra_sor_hdmi_settings *
2294tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2295{
2296 unsigned int i;
2297
2298 for (i = 0; i < sor->num_settings; i++)
2299 if (frequency <= sor->settings[i].frequency)
2300 return &sor->settings[i];
2301
2302 return NULL;
2303}
2304
2305static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2306{
2307 u32 value;
2308
2309 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2310 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2311 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2312 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2313}
2314
2315static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2316{
2317 struct i2c_adapter *ddc = sor->output.ddc;
2318
2319 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2320 drm_scdc_set_scrambling(ddc, false);
2321
2322 tegra_sor_hdmi_disable_scrambling(sor);
2323}
2324
2325static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2326{
2327 if (sor->scdc_enabled) {
2328 cancel_delayed_work_sync(&sor->scdc);
2329 tegra_sor_hdmi_scdc_disable(sor);
2330 }
2331}
2332
2333static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2334{
2335 u32 value;
2336
2337 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2338 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2339 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2340 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2341}
2342
2343static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2344{
2345 struct i2c_adapter *ddc = sor->output.ddc;
2346
2347 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2348 drm_scdc_set_scrambling(ddc, true);
2349
2350 tegra_sor_hdmi_enable_scrambling(sor);
2351}
2352
2353static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2354{
2355 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2356 struct i2c_adapter *ddc = sor->output.ddc;
2357
2358 if (!drm_scdc_get_scrambling_status(ddc)) {
2359 DRM_DEBUG_KMS("SCDC not scrambled\n");
2360 tegra_sor_hdmi_scdc_enable(sor);
2361 }
2362
2363 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2364}
2365
2366static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2367{
2368 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2369 struct drm_display_mode *mode;
2370
2371 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2372
2373 if (mode->clock >= 340000 && scdc->supported) {
2374 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2375 tegra_sor_hdmi_scdc_enable(sor);
2376 sor->scdc_enabled = true;
2377 }
2378}
2379
2380static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2381{
2382 struct tegra_output *output = encoder_to_output(encoder);
2383 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2384 struct tegra_sor *sor = to_sor(output);
2385 u32 value;
2386 int err;
2387
2388 tegra_sor_audio_unprepare(sor);
2389 tegra_sor_hdmi_scdc_stop(sor);
2390
2391 err = tegra_sor_detach(sor);
2392 if (err < 0)
2393 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2394
2395 tegra_sor_writel(sor, 0, SOR_STATE1);
2396 tegra_sor_update(sor);
2397
2398 /* disable display to SOR clock */
2399 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2400
2401 if (!sor->soc->has_nvdisplay)
2402 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2403 else
2404 value &= ~SOR_ENABLE(sor->index);
2405
2406 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2407
2408 tegra_dc_commit(dc);
2409
2410 err = tegra_sor_power_down(sor);
2411 if (err < 0)
2412 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2413
2414 err = tegra_io_pad_power_disable(sor->pad);
2415 if (err < 0)
2416 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2417
2418 pm_runtime_put(sor->dev);
2419}
2420
2421static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2422{
2423 struct tegra_output *output = encoder_to_output(encoder);
2424 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2425 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2426 struct tegra_sor_hdmi_settings *settings;
2427 struct tegra_sor *sor = to_sor(output);
2428 struct tegra_sor_state *state;
2429 struct drm_display_mode *mode;
2430 unsigned long rate, pclk;
2431 unsigned int div, i;
2432 u32 value;
2433 int err;
2434
2435 state = to_sor_state(output->connector.state);
2436 mode = &encoder->crtc->state->adjusted_mode;
2437 pclk = mode->clock * 1000;
2438
2439 pm_runtime_get_sync(sor->dev);
2440
2441 /* switch to safe parent clock */
2442 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2443 if (err < 0) {
2444 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2445 return;
2446 }
2447
2448 div = clk_get_rate(sor->clk) / 1000000 * 4;
2449
2450 err = tegra_io_pad_power_enable(sor->pad);
2451 if (err < 0)
2452 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2453
2454 usleep_range(20, 100);
2455
2456 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2457 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2458 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2459
2460 usleep_range(20, 100);
2461
2462 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2463 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2464 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2465
2466 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2467 value &= ~SOR_PLL0_VCOPD;
2468 value &= ~SOR_PLL0_PWR;
2469 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2470
2471 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2472 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2473 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2474
2475 usleep_range(200, 400);
2476
2477 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2478 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2479 value &= ~SOR_PLL2_PORT_POWERDOWN;
2480 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2481
2482 usleep_range(20, 100);
2483
2484 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2485 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2486 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2487 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2488
2489 while (true) {
2490 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2491 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2492 break;
2493
2494 usleep_range(250, 1000);
2495 }
2496
2497 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2498 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2499 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2500
2501 while (true) {
2502 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2503 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2504 break;
2505
2506 usleep_range(250, 1000);
2507 }
2508
2509 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2510 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2511 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2512
2513 if (mode->clock < 340000) {
2514 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2515 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2516 } else {
2517 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2518 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2519 }
2520
2521 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2522 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2523
2524 /* SOR pad PLL stabilization time */
2525 usleep_range(250, 1000);
2526
2527 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2528 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2529 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2530 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2531
2532 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2533 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2534 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2535 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2536 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2537 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2538
2539 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2540 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2541 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2542
2543 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2544 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2545 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2546 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2547
2548 if (!sor->soc->has_nvdisplay) {
2549 /* program the reference clock */
2550 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2551 tegra_sor_writel(sor, value, SOR_REFCLK);
2552 }
2553
2554 /* XXX not in TRM */
2555 for (value = 0, i = 0; i < 5; i++)
2556 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2557 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2558
2559 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2560 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2561
2562 /* switch to parent clock */
2563 err = clk_set_parent(sor->clk, sor->clk_parent);
2564 if (err < 0) {
2565 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2566 return;
2567 }
2568
2569 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2570 if (err < 0) {
2571 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2572 return;
2573 }
2574
2575 /* adjust clock rate for HDMI 2.0 modes */
2576 rate = clk_get_rate(sor->clk_parent);
2577
2578 if (mode->clock >= 340000)
2579 rate /= 2;
2580
2581 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2582
2583 clk_set_rate(sor->clk, rate);
2584
2585 if (!sor->soc->has_nvdisplay) {
2586 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2587
2588 /* XXX is this the proper check? */
2589 if (mode->clock < 75000)
2590 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2591
2592 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2593 }
2594
2595 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2596
2597 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2598 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2599 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2600
2601 if (!dc->soc->has_nvdisplay) {
2602 /* H_PULSE2 setup */
2603 pulse_start = h_ref_to_sync +
2604 (mode->hsync_end - mode->hsync_start) +
2605 (mode->htotal - mode->hsync_end) - 10;
2606
2607 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2608 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2609 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2610
2611 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2612 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2613
2614 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2615 value |= H_PULSE2_ENABLE;
2616 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2617 }
2618
2619 /* infoframe setup */
2620 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2621 if (err < 0)
2622 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2623
2624 /* XXX HDMI audio support not implemented yet */
2625 tegra_sor_hdmi_disable_audio_infoframe(sor);
2626
2627 /* use single TMDS protocol */
2628 value = tegra_sor_readl(sor, SOR_STATE1);
2629 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2630 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2631 tegra_sor_writel(sor, value, SOR_STATE1);
2632
2633 /* power up pad calibration */
2634 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2635 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2637
2638 /* production settings */
2639 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2640 if (!settings) {
2641 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2642 mode->clock * 1000);
2643 return;
2644 }
2645
2646 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2647 value &= ~SOR_PLL0_ICHPMP_MASK;
2648 value &= ~SOR_PLL0_FILTER_MASK;
2649 value &= ~SOR_PLL0_VCOCAP_MASK;
2650 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2651 value |= SOR_PLL0_FILTER(settings->filter);
2652 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2653 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2654
2655 /* XXX not in TRM */
2656 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2657 value &= ~SOR_PLL1_LOADADJ_MASK;
2658 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2659 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2660 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2661 value |= SOR_PLL1_TMDS_TERM;
2662 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2663
2664 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2665 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2666 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2667 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2668 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2669 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2670 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2671 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2672 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2673 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2674
2675 value = settings->drive_current[3] << 24 |
2676 settings->drive_current[2] << 16 |
2677 settings->drive_current[1] << 8 |
2678 settings->drive_current[0] << 0;
2679 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2680
2681 value = settings->preemphasis[3] << 24 |
2682 settings->preemphasis[2] << 16 |
2683 settings->preemphasis[1] << 8 |
2684 settings->preemphasis[0] << 0;
2685 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2686
2687 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2688 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2689 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2690 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2691 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2692
2693 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2694 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2695 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2696 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2697
2698 /* power down pad calibration */
2699 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2700 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2701 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2702
2703 if (!dc->soc->has_nvdisplay) {
2704 /* miscellaneous display controller settings */
2705 value = VSYNC_H_POSITION(1);
2706 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2707 }
2708
2709 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2710 value &= ~DITHER_CONTROL_MASK;
2711 value &= ~BASE_COLOR_SIZE_MASK;
2712
2713 switch (state->bpc) {
2714 case 6:
2715 value |= BASE_COLOR_SIZE_666;
2716 break;
2717
2718 case 8:
2719 value |= BASE_COLOR_SIZE_888;
2720 break;
2721
2722 case 10:
2723 value |= BASE_COLOR_SIZE_101010;
2724 break;
2725
2726 case 12:
2727 value |= BASE_COLOR_SIZE_121212;
2728 break;
2729
2730 default:
2731 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2732 value |= BASE_COLOR_SIZE_888;
2733 break;
2734 }
2735
2736 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2737
2738 /* XXX set display head owner */
2739 value = tegra_sor_readl(sor, SOR_STATE1);
2740 value &= ~SOR_STATE_ASY_OWNER_MASK;
2741 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2742 tegra_sor_writel(sor, value, SOR_STATE1);
2743
2744 err = tegra_sor_power_up(sor, 250);
2745 if (err < 0)
2746 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2747
2748 /* configure dynamic range of output */
2749 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2750 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2751 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2752 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2753
2754 /* configure colorspace */
2755 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2756 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2757 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2758 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2759
2760 tegra_sor_mode_set(sor, mode, state);
2761
2762 tegra_sor_update(sor);
2763
2764 /* program preamble timing in SOR (XXX) */
2765 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2766 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2767 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2768
2769 err = tegra_sor_attach(sor);
2770 if (err < 0)
2771 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2772
2773 /* enable display to SOR clock and generate HDMI preamble */
2774 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2775
2776 if (!sor->soc->has_nvdisplay)
2777 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2778 else
2779 value |= SOR_ENABLE(sor->index);
2780
2781 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2782
2783 if (dc->soc->has_nvdisplay) {
2784 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2785 value &= ~PROTOCOL_MASK;
2786 value |= PROTOCOL_SINGLE_TMDS_A;
2787 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2788 }
2789
2790 tegra_dc_commit(dc);
2791
2792 err = tegra_sor_wakeup(sor);
2793 if (err < 0)
2794 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2795
2796 tegra_sor_hdmi_scdc_start(sor);
2797 tegra_sor_audio_prepare(sor);
2798}
2799
2800static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2801 .disable = tegra_sor_hdmi_disable,
2802 .enable = tegra_sor_hdmi_enable,
2803 .atomic_check = tegra_sor_encoder_atomic_check,
2804};
2805
2806static int tegra_sor_init(struct host1x_client *client)
2807{
2808 struct drm_device *drm = dev_get_drvdata(client->parent);
2809 const struct drm_encoder_helper_funcs *helpers = NULL;
2810 struct tegra_sor *sor = host1x_client_to_sor(client);
2811 int connector = DRM_MODE_CONNECTOR_Unknown;
2812 int encoder = DRM_MODE_ENCODER_NONE;
2813 u32 value;
2814 int err;
2815
2816 if (!sor->aux) {
2817 if (sor->soc->supports_hdmi) {
2818 connector = DRM_MODE_CONNECTOR_HDMIA;
2819 encoder = DRM_MODE_ENCODER_TMDS;
2820 helpers = &tegra_sor_hdmi_helpers;
2821 } else if (sor->soc->supports_lvds) {
2822 connector = DRM_MODE_CONNECTOR_LVDS;
2823 encoder = DRM_MODE_ENCODER_LVDS;
2824 }
2825 } else {
2826 if (sor->soc->supports_edp) {
2827 connector = DRM_MODE_CONNECTOR_eDP;
2828 encoder = DRM_MODE_ENCODER_TMDS;
2829 helpers = &tegra_sor_edp_helpers;
2830 } else if (sor->soc->supports_dp) {
2831 connector = DRM_MODE_CONNECTOR_DisplayPort;
2832 encoder = DRM_MODE_ENCODER_TMDS;
2833 }
2834 }
2835
2836 sor->output.dev = sor->dev;
2837
2838 drm_connector_init(drm, &sor->output.connector,
2839 &tegra_sor_connector_funcs,
2840 connector);
2841 drm_connector_helper_add(&sor->output.connector,
2842 &tegra_sor_connector_helper_funcs);
2843 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2844
2845 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2846 encoder, NULL);
2847 drm_encoder_helper_add(&sor->output.encoder, helpers);
2848
2849 drm_connector_attach_encoder(&sor->output.connector,
2850 &sor->output.encoder);
2851 drm_connector_register(&sor->output.connector);
2852
2853 err = tegra_output_init(drm, &sor->output);
2854 if (err < 0) {
2855 dev_err(client->dev, "failed to initialize output: %d\n", err);
2856 return err;
2857 }
2858
2859 tegra_output_find_possible_crtcs(&sor->output, drm);
2860
2861 if (sor->aux) {
2862 err = drm_dp_aux_attach(sor->aux, &sor->output);
2863 if (err < 0) {
2864 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2865 return err;
2866 }
2867 }
2868
2869 /*
2870 * XXX: Remove this reset once proper hand-over from firmware to
2871 * kernel is possible.
2872 */
2873 if (sor->rst) {
2874 err = reset_control_acquire(sor->rst);
2875 if (err < 0) {
2876 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
2877 err);
2878 goto rpm_put;
2879 }
2880
2881 err = reset_control_assert(sor->rst);
2882 if (err < 0) {
2883 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2884 err);
2885 goto rpm_put;
2886 }
2887 }
2888
2889 err = clk_prepare_enable(sor->clk);
2890 if (err < 0) {
2891 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2892 goto rpm_put;
2893 }
2894
2895 usleep_range(1000, 3000);
2896
2897 if (sor->rst) {
2898 err = reset_control_deassert(sor->rst);
2899 if (err < 0) {
2900 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2901 err);
2902 clk_disable_unprepare(sor->clk);
2903 goto rpm_put;
2904 }
2905
2906 reset_control_release(sor->rst);
2907 }
2908
2909 err = clk_prepare_enable(sor->clk_safe);
2910 if (err < 0) {
2911 clk_disable_unprepare(sor->clk);
2912 return err;
2913 }
2914
2915 err = clk_prepare_enable(sor->clk_dp);
2916 if (err < 0) {
2917 clk_disable_unprepare(sor->clk_safe);
2918 clk_disable_unprepare(sor->clk);
2919 return err;
2920 }
2921
2922 /*
2923 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2924 * is used for interoperability between the HDA codec driver and the
2925 * HDMI/DP driver.
2926 */
2927 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2928 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2929 tegra_sor_writel(sor, value, SOR_INT_MASK);
2930
2931 return 0;
2932
2933rpm_put:
2934 if (sor->rst)
2935 pm_runtime_put(sor->dev);
2936
2937 return err;
2938}
2939
2940static int tegra_sor_exit(struct host1x_client *client)
2941{
2942 struct tegra_sor *sor = host1x_client_to_sor(client);
2943 int err;
2944
2945 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2946 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2947
2948 tegra_output_exit(&sor->output);
2949
2950 if (sor->aux) {
2951 err = drm_dp_aux_detach(sor->aux);
2952 if (err < 0) {
2953 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2954 return err;
2955 }
2956 }
2957
2958 clk_disable_unprepare(sor->clk_safe);
2959 clk_disable_unprepare(sor->clk_dp);
2960 clk_disable_unprepare(sor->clk);
2961
2962 return 0;
2963}
2964
2965static const struct host1x_client_ops sor_client_ops = {
2966 .init = tegra_sor_init,
2967 .exit = tegra_sor_exit,
2968};
2969
2970static const struct tegra_sor_ops tegra_sor_edp_ops = {
2971 .name = "eDP",
2972};
2973
2974static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2975{
2976 int err;
2977
2978 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2979 if (IS_ERR(sor->avdd_io_supply)) {
2980 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2981 PTR_ERR(sor->avdd_io_supply));
2982 return PTR_ERR(sor->avdd_io_supply);
2983 }
2984
2985 err = regulator_enable(sor->avdd_io_supply);
2986 if (err < 0) {
2987 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2988 err);
2989 return err;
2990 }
2991
2992 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2993 if (IS_ERR(sor->vdd_pll_supply)) {
2994 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2995 PTR_ERR(sor->vdd_pll_supply));
2996 return PTR_ERR(sor->vdd_pll_supply);
2997 }
2998
2999 err = regulator_enable(sor->vdd_pll_supply);
3000 if (err < 0) {
3001 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
3002 err);
3003 return err;
3004 }
3005
3006 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
3007 if (IS_ERR(sor->hdmi_supply)) {
3008 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
3009 PTR_ERR(sor->hdmi_supply));
3010 return PTR_ERR(sor->hdmi_supply);
3011 }
3012
3013 err = regulator_enable(sor->hdmi_supply);
3014 if (err < 0) {
3015 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3016 return err;
3017 }
3018
3019 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3020
3021 return 0;
3022}
3023
3024static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3025{
3026 regulator_disable(sor->hdmi_supply);
3027 regulator_disable(sor->vdd_pll_supply);
3028 regulator_disable(sor->avdd_io_supply);
3029
3030 return 0;
3031}
3032
3033static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3034 .name = "HDMI",
3035 .probe = tegra_sor_hdmi_probe,
3036 .remove = tegra_sor_hdmi_remove,
3037};
3038
3039static const u8 tegra124_sor_xbar_cfg[5] = {
3040 0, 1, 2, 3, 4
3041};
3042
3043static const struct tegra_sor_regs tegra124_sor_regs = {
3044 .head_state0 = 0x05,
3045 .head_state1 = 0x07,
3046 .head_state2 = 0x09,
3047 .head_state3 = 0x0b,
3048 .head_state4 = 0x0d,
3049 .head_state5 = 0x0f,
3050 .pll0 = 0x17,
3051 .pll1 = 0x18,
3052 .pll2 = 0x19,
3053 .pll3 = 0x1a,
3054 .dp_padctl0 = 0x5c,
3055 .dp_padctl2 = 0x73,
3056};
3057
3058static const struct tegra_sor_soc tegra124_sor = {
3059 .supports_edp = true,
3060 .supports_lvds = true,
3061 .supports_hdmi = false,
3062 .supports_dp = false,
3063 .regs = &tegra124_sor_regs,
3064 .has_nvdisplay = false,
3065 .xbar_cfg = tegra124_sor_xbar_cfg,
3066};
3067
3068static const struct tegra_sor_regs tegra210_sor_regs = {
3069 .head_state0 = 0x05,
3070 .head_state1 = 0x07,
3071 .head_state2 = 0x09,
3072 .head_state3 = 0x0b,
3073 .head_state4 = 0x0d,
3074 .head_state5 = 0x0f,
3075 .pll0 = 0x17,
3076 .pll1 = 0x18,
3077 .pll2 = 0x19,
3078 .pll3 = 0x1a,
3079 .dp_padctl0 = 0x5c,
3080 .dp_padctl2 = 0x73,
3081};
3082
3083static const struct tegra_sor_soc tegra210_sor = {
3084 .supports_edp = true,
3085 .supports_lvds = false,
3086 .supports_hdmi = false,
3087 .supports_dp = false,
3088 .regs = &tegra210_sor_regs,
3089 .has_nvdisplay = false,
3090 .xbar_cfg = tegra124_sor_xbar_cfg,
3091};
3092
3093static const u8 tegra210_sor_xbar_cfg[5] = {
3094 2, 1, 0, 3, 4
3095};
3096
3097static const struct tegra_sor_soc tegra210_sor1 = {
3098 .supports_edp = false,
3099 .supports_lvds = false,
3100 .supports_hdmi = true,
3101 .supports_dp = true,
3102
3103 .regs = &tegra210_sor_regs,
3104 .has_nvdisplay = false,
3105
3106 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3107 .settings = tegra210_sor_hdmi_defaults,
3108
3109 .xbar_cfg = tegra210_sor_xbar_cfg,
3110};
3111
3112static const struct tegra_sor_regs tegra186_sor_regs = {
3113 .head_state0 = 0x151,
3114 .head_state1 = 0x154,
3115 .head_state2 = 0x157,
3116 .head_state3 = 0x15a,
3117 .head_state4 = 0x15d,
3118 .head_state5 = 0x160,
3119 .pll0 = 0x163,
3120 .pll1 = 0x164,
3121 .pll2 = 0x165,
3122 .pll3 = 0x166,
3123 .dp_padctl0 = 0x168,
3124 .dp_padctl2 = 0x16a,
3125};
3126
3127static const struct tegra_sor_soc tegra186_sor = {
3128 .supports_edp = false,
3129 .supports_lvds = false,
3130 .supports_hdmi = false,
3131 .supports_dp = true,
3132
3133 .regs = &tegra186_sor_regs,
3134 .has_nvdisplay = true,
3135
3136 .xbar_cfg = tegra124_sor_xbar_cfg,
3137};
3138
3139static const struct tegra_sor_soc tegra186_sor1 = {
3140 .supports_edp = false,
3141 .supports_lvds = false,
3142 .supports_hdmi = true,
3143 .supports_dp = true,
3144
3145 .regs = &tegra186_sor_regs,
3146 .has_nvdisplay = true,
3147
3148 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3149 .settings = tegra186_sor_hdmi_defaults,
3150
3151 .xbar_cfg = tegra124_sor_xbar_cfg,
3152};
3153
3154static const struct tegra_sor_regs tegra194_sor_regs = {
3155 .head_state0 = 0x151,
3156 .head_state1 = 0x155,
3157 .head_state2 = 0x159,
3158 .head_state3 = 0x15d,
3159 .head_state4 = 0x161,
3160 .head_state5 = 0x165,
3161 .pll0 = 0x169,
3162 .pll1 = 0x16a,
3163 .pll2 = 0x16b,
3164 .pll3 = 0x16c,
3165 .dp_padctl0 = 0x16e,
3166 .dp_padctl2 = 0x16f,
3167};
3168
3169static const struct tegra_sor_soc tegra194_sor = {
3170 .supports_edp = true,
3171 .supports_lvds = false,
3172 .supports_hdmi = true,
3173 .supports_dp = true,
3174
3175 .regs = &tegra194_sor_regs,
3176 .has_nvdisplay = true,
3177
3178 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3179 .settings = tegra194_sor_hdmi_defaults,
3180
3181 .xbar_cfg = tegra210_sor_xbar_cfg,
3182};
3183
3184static const struct of_device_id tegra_sor_of_match[] = {
3185 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3186 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3187 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3188 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3189 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3190 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3191 { },
3192};
3193MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3194
3195static int tegra_sor_parse_dt(struct tegra_sor *sor)
3196{
3197 struct device_node *np = sor->dev->of_node;
3198 u32 xbar_cfg[5];
3199 unsigned int i;
3200 u32 value;
3201 int err;
3202
3203 if (sor->soc->has_nvdisplay) {
3204 err = of_property_read_u32(np, "nvidia,interface", &value);
3205 if (err < 0)
3206 return err;
3207
3208 sor->index = value;
3209
3210 /*
3211 * override the default that we already set for Tegra210 and
3212 * earlier
3213 */
3214 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3215 } else {
3216 if (sor->soc->supports_edp)
3217 sor->index = 0;
3218 else
3219 sor->index = 1;
3220 }
3221
3222 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3223 if (err < 0) {
3224 /* fall back to default per-SoC XBAR configuration */
3225 for (i = 0; i < 5; i++)
3226 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3227 } else {
3228 /* copy cells to SOR XBAR configuration */
3229 for (i = 0; i < 5; i++)
3230 sor->xbar_cfg[i] = xbar_cfg[i];
3231 }
3232
3233 return 0;
3234}
3235
3236static irqreturn_t tegra_sor_irq(int irq, void *data)
3237{
3238 struct tegra_sor *sor = data;
3239 u32 value;
3240
3241 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3242 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3243
3244 if (value & SOR_INT_CODEC_SCRATCH0) {
3245 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3246
3247 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3248 unsigned int format;
3249
3250 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3251
3252 tegra_hda_parse_format(format, &sor->format);
3253
3254 tegra_sor_hdmi_audio_enable(sor);
3255 } else {
3256 tegra_sor_hdmi_audio_disable(sor);
3257 }
3258 }
3259
3260 return IRQ_HANDLED;
3261}
3262
3263static int tegra_sor_probe(struct platform_device *pdev)
3264{
3265 struct device_node *np;
3266 struct tegra_sor *sor;
3267 struct resource *regs;
3268 int err;
3269
3270 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3271 if (!sor)
3272 return -ENOMEM;
3273
3274 sor->soc = of_device_get_match_data(&pdev->dev);
3275 sor->output.dev = sor->dev = &pdev->dev;
3276
3277 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3278 sor->soc->num_settings *
3279 sizeof(*sor->settings),
3280 GFP_KERNEL);
3281 if (!sor->settings)
3282 return -ENOMEM;
3283
3284 sor->num_settings = sor->soc->num_settings;
3285
3286 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3287 if (np) {
3288 sor->aux = drm_dp_aux_find_by_of_node(np);
3289 of_node_put(np);
3290
3291 if (!sor->aux)
3292 return -EPROBE_DEFER;
3293 }
3294
3295 if (!sor->aux) {
3296 if (sor->soc->supports_hdmi) {
3297 sor->ops = &tegra_sor_hdmi_ops;
3298 sor->pad = TEGRA_IO_PAD_HDMI;
3299 } else if (sor->soc->supports_lvds) {
3300 dev_err(&pdev->dev, "LVDS not supported yet\n");
3301 return -ENODEV;
3302 } else {
3303 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3304 return -ENODEV;
3305 }
3306 } else {
3307 if (sor->soc->supports_edp) {
3308 sor->ops = &tegra_sor_edp_ops;
3309 sor->pad = TEGRA_IO_PAD_LVDS;
3310 } else if (sor->soc->supports_dp) {
3311 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3312 return -ENODEV;
3313 } else {
3314 dev_err(&pdev->dev, "unknown (DP) support\n");
3315 return -ENODEV;
3316 }
3317 }
3318
3319 err = tegra_sor_parse_dt(sor);
3320 if (err < 0)
3321 return err;
3322
3323 err = tegra_output_probe(&sor->output);
3324 if (err < 0) {
3325 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3326 return err;
3327 }
3328
3329 if (sor->ops && sor->ops->probe) {
3330 err = sor->ops->probe(sor);
3331 if (err < 0) {
3332 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3333 sor->ops->name, err);
3334 goto output;
3335 }
3336 }
3337
3338 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3339 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3340 if (IS_ERR(sor->regs)) {
3341 err = PTR_ERR(sor->regs);
3342 goto remove;
3343 }
3344
3345 err = platform_get_irq(pdev, 0);
3346 if (err < 0) {
3347 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3348 goto remove;
3349 }
3350
3351 sor->irq = err;
3352
3353 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3354 dev_name(sor->dev), sor);
3355 if (err < 0) {
3356 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3357 goto remove;
3358 }
3359
3360 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3361 if (IS_ERR(sor->rst)) {
3362 err = PTR_ERR(sor->rst);
3363
3364 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3365 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3366 err);
3367 goto remove;
3368 }
3369
3370 /*
3371 * At this point, the reset control is most likely being used
3372 * by the generic power domain implementation. With any luck
3373 * the power domain will have taken care of resetting the SOR
3374 * and we don't have to do anything.
3375 */
3376 sor->rst = NULL;
3377 }
3378
3379 sor->clk = devm_clk_get(&pdev->dev, NULL);
3380 if (IS_ERR(sor->clk)) {
3381 err = PTR_ERR(sor->clk);
3382 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3383 goto remove;
3384 }
3385
3386 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3387 struct device_node *np = pdev->dev.of_node;
3388 const char *name;
3389
3390 /*
3391 * For backwards compatibility with Tegra210 device trees,
3392 * fall back to the old clock name "source" if the new "out"
3393 * clock is not available.
3394 */
3395 if (of_property_match_string(np, "clock-names", "out") < 0)
3396 name = "source";
3397 else
3398 name = "out";
3399
3400 sor->clk_out = devm_clk_get(&pdev->dev, name);
3401 if (IS_ERR(sor->clk_out)) {
3402 err = PTR_ERR(sor->clk_out);
3403 dev_err(sor->dev, "failed to get %s clock: %d\n",
3404 name, err);
3405 goto remove;
3406 }
3407 } else {
3408 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3409 sor->clk_out = sor->clk;
3410 }
3411
3412 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3413 if (IS_ERR(sor->clk_parent)) {
3414 err = PTR_ERR(sor->clk_parent);
3415 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3416 goto remove;
3417 }
3418
3419 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3420 if (IS_ERR(sor->clk_safe)) {
3421 err = PTR_ERR(sor->clk_safe);
3422 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3423 goto remove;
3424 }
3425
3426 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3427 if (IS_ERR(sor->clk_dp)) {
3428 err = PTR_ERR(sor->clk_dp);
3429 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3430 goto remove;
3431 }
3432
3433 /*
3434 * Starting with Tegra186, the BPMP provides an implementation for
3435 * the pad output clock, so we have to look it up from device tree.
3436 */
3437 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3438 if (IS_ERR(sor->clk_pad)) {
3439 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3440 err = PTR_ERR(sor->clk_pad);
3441 goto remove;
3442 }
3443
3444 /*
3445 * If the pad output clock is not available, then we assume
3446 * we're on Tegra210 or earlier and have to provide our own
3447 * implementation.
3448 */
3449 sor->clk_pad = NULL;
3450 }
3451
3452 /*
3453 * The bootloader may have set up the SOR such that it's module clock
3454 * is sourced by one of the display PLLs. However, that doesn't work
3455 * without properly having set up other bits of the SOR.
3456 */
3457 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3458 if (err < 0) {
3459 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3460 goto remove;
3461 }
3462
3463 platform_set_drvdata(pdev, sor);
3464 pm_runtime_enable(&pdev->dev);
3465
3466 /*
3467 * On Tegra210 and earlier, provide our own implementation for the
3468 * pad output clock.
3469 */
3470 if (!sor->clk_pad) {
3471 err = pm_runtime_get_sync(&pdev->dev);
3472 if (err < 0) {
3473 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3474 err);
3475 goto remove;
3476 }
3477
3478 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3479 "sor1_pad_clkout");
3480 pm_runtime_put(&pdev->dev);
3481 }
3482
3483 if (IS_ERR(sor->clk_pad)) {
3484 err = PTR_ERR(sor->clk_pad);
3485 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3486 err);
3487 goto remove;
3488 }
3489
3490 INIT_LIST_HEAD(&sor->client.list);
3491 sor->client.ops = &sor_client_ops;
3492 sor->client.dev = &pdev->dev;
3493
3494 err = host1x_client_register(&sor->client);
3495 if (err < 0) {
3496 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3497 err);
3498 goto remove;
3499 }
3500
3501 return 0;
3502
3503remove:
3504 if (sor->ops && sor->ops->remove)
3505 sor->ops->remove(sor);
3506output:
3507 tegra_output_remove(&sor->output);
3508 return err;
3509}
3510
3511static int tegra_sor_remove(struct platform_device *pdev)
3512{
3513 struct tegra_sor *sor = platform_get_drvdata(pdev);
3514 int err;
3515
3516 pm_runtime_disable(&pdev->dev);
3517
3518 err = host1x_client_unregister(&sor->client);
3519 if (err < 0) {
3520 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3521 err);
3522 return err;
3523 }
3524
3525 if (sor->ops && sor->ops->remove) {
3526 err = sor->ops->remove(sor);
3527 if (err < 0)
3528 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3529 }
3530
3531 tegra_output_remove(&sor->output);
3532
3533 return 0;
3534}
3535
3536#ifdef CONFIG_PM
3537static int tegra_sor_suspend(struct device *dev)
3538{
3539 struct tegra_sor *sor = dev_get_drvdata(dev);
3540 int err;
3541
3542 if (sor->rst) {
3543 err = reset_control_assert(sor->rst);
3544 if (err < 0) {
3545 dev_err(dev, "failed to assert reset: %d\n", err);
3546 return err;
3547 }
3548
3549 reset_control_release(sor->rst);
3550 }
3551
3552 usleep_range(1000, 2000);
3553
3554 clk_disable_unprepare(sor->clk);
3555
3556 return 0;
3557}
3558
3559static int tegra_sor_resume(struct device *dev)
3560{
3561 struct tegra_sor *sor = dev_get_drvdata(dev);
3562 int err;
3563
3564 err = clk_prepare_enable(sor->clk);
3565 if (err < 0) {
3566 dev_err(dev, "failed to enable clock: %d\n", err);
3567 return err;
3568 }
3569
3570 usleep_range(1000, 2000);
3571
3572 if (sor->rst) {
3573 err = reset_control_acquire(sor->rst);
3574 if (err < 0) {
3575 dev_err(dev, "failed to acquire reset: %d\n", err);
3576 clk_disable_unprepare(sor->clk);
3577 return err;
3578 }
3579
3580 err = reset_control_deassert(sor->rst);
3581 if (err < 0) {
3582 dev_err(dev, "failed to deassert reset: %d\n", err);
3583 reset_control_release(sor->rst);
3584 clk_disable_unprepare(sor->clk);
3585 return err;
3586 }
3587 }
3588
3589 return 0;
3590}
3591#endif
3592
3593static const struct dev_pm_ops tegra_sor_pm_ops = {
3594 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3595};
3596
3597struct platform_driver tegra_sor_driver = {
3598 .driver = {
3599 .name = "tegra-sor",
3600 .of_match_table = tegra_sor_of_match,
3601 .pm = &tegra_sor_pm_ops,
3602 },
3603 .probe = tegra_sor_probe,
3604 .remove = tegra_sor_remove,
3605};