Gitiles
Code Review Sign In
192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / gpu / drm / v3d / v3d_trace.h
blob: 7aa8dc356e54c2226991f4534f37b3f29ff3c721 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2015-2018 Broadcom */
3
4#if !defined(_V3D_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
5#define _V3D_TRACE_H_
6
7#include <linux/stringify.h>
8#include <linux/types.h>
9#include <linux/tracepoint.h>
10
11#undef TRACE_SYSTEM
12#define TRACE_SYSTEM v3d
13#define TRACE_INCLUDE_FILE v3d_trace
14
15TRACE_EVENT(v3d_submit_cl_ioctl,
16 TP_PROTO(struct drm_device *dev, u32 ct1qba, u32 ct1qea),
17 TP_ARGS(dev, ct1qba, ct1qea),
18
19 TP_STRUCT__entry(
20 __field(u32, dev)
21 __field(u32, ct1qba)
22 __field(u32, ct1qea)
23 ),
24
25 TP_fast_assign(
26 __entry->dev = dev->primary->index;
27 __entry->ct1qba = ct1qba;
28 __entry->ct1qea = ct1qea;
29 ),
30
31 TP_printk("dev=%u, RCL 0x%08x..0x%08x",
32 __entry->dev,
33 __entry->ct1qba,
34 __entry->ct1qea)
35);
36
37TRACE_EVENT(v3d_submit_cl,
38 TP_PROTO(struct drm_device *dev, bool is_render,
39 uint64_t seqno,
40 u32 ctnqba, u32 ctnqea),
41 TP_ARGS(dev, is_render, seqno, ctnqba, ctnqea),
42
43 TP_STRUCT__entry(
44 __field(u32, dev)
45 __field(bool, is_render)
46 __field(u64, seqno)
47 __field(u32, ctnqba)
48 __field(u32, ctnqea)
49 ),
50
51 TP_fast_assign(
52 __entry->dev = dev->primary->index;
53 __entry->is_render = is_render;
54 __entry->seqno = seqno;
55 __entry->ctnqba = ctnqba;
56 __entry->ctnqea = ctnqea;
57 ),
58
59 TP_printk("dev=%u, %s, seqno=%llu, 0x%08x..0x%08x",
60 __entry->dev,
61 __entry->is_render ? "RCL" : "BCL",
62 __entry->seqno,
63 __entry->ctnqba,
64 __entry->ctnqea)
65);
66
67TRACE_EVENT(v3d_bcl_irq,
68 TP_PROTO(struct drm_device *dev,
69 uint64_t seqno),
70 TP_ARGS(dev, seqno),
71
72 TP_STRUCT__entry(
73 __field(u32, dev)
74 __field(u64, seqno)
75 ),
76
77 TP_fast_assign(
78 __entry->dev = dev->primary->index;
79 __entry->seqno = seqno;
80 ),
81
82 TP_printk("dev=%u, seqno=%llu",
83 __entry->dev,
84 __entry->seqno)
85);
86
87TRACE_EVENT(v3d_rcl_irq,
88 TP_PROTO(struct drm_device *dev,
89 uint64_t seqno),
90 TP_ARGS(dev, seqno),
91
92 TP_STRUCT__entry(
93 __field(u32, dev)
94 __field(u64, seqno)
95 ),
96
97 TP_fast_assign(
98 __entry->dev = dev->primary->index;
99 __entry->seqno = seqno;
100 ),
101
102 TP_printk("dev=%u, seqno=%llu",
103 __entry->dev,
104 __entry->seqno)
105);
106
107TRACE_EVENT(v3d_tfu_irq,
108 TP_PROTO(struct drm_device *dev,
109 uint64_t seqno),
110 TP_ARGS(dev, seqno),
111
112 TP_STRUCT__entry(
113 __field(u32, dev)
114 __field(u64, seqno)
115 ),
116
117 TP_fast_assign(
118 __entry->dev = dev->primary->index;
119 __entry->seqno = seqno;
120 ),
121
122 TP_printk("dev=%u, seqno=%llu",
123 __entry->dev,
124 __entry->seqno)
125);
126
127TRACE_EVENT(v3d_csd_irq,
128 TP_PROTO(struct drm_device *dev,
129 uint64_t seqno),
130 TP_ARGS(dev, seqno),
131
132 TP_STRUCT__entry(
133 __field(u32, dev)
134 __field(u64, seqno)
135 ),
136
137 TP_fast_assign(
138 __entry->dev = dev->primary->index;
139 __entry->seqno = seqno;
140 ),
141
142 TP_printk("dev=%u, seqno=%llu",
143 __entry->dev,
144 __entry->seqno)
145);
146
147TRACE_EVENT(v3d_submit_tfu_ioctl,
148 TP_PROTO(struct drm_device *dev, u32 iia),
149 TP_ARGS(dev, iia),
150
151 TP_STRUCT__entry(
152 __field(u32, dev)
153 __field(u32, iia)
154 ),
155
156 TP_fast_assign(
157 __entry->dev = dev->primary->index;
158 __entry->iia = iia;
159 ),
160
161 TP_printk("dev=%u, IIA 0x%08x",
162 __entry->dev,
163 __entry->iia)
164);
165
166TRACE_EVENT(v3d_submit_tfu,
167 TP_PROTO(struct drm_device *dev,
168 uint64_t seqno),
169 TP_ARGS(dev, seqno),
170
171 TP_STRUCT__entry(
172 __field(u32, dev)
173 __field(u64, seqno)
174 ),
175
176 TP_fast_assign(
177 __entry->dev = dev->primary->index;
178 __entry->seqno = seqno;
179 ),
180
181 TP_printk("dev=%u, seqno=%llu",
182 __entry->dev,
183 __entry->seqno)
184);
185
186TRACE_EVENT(v3d_submit_csd_ioctl,
187 TP_PROTO(struct drm_device *dev, u32 cfg5, u32 cfg6),
188 TP_ARGS(dev, cfg5, cfg6),
189
190 TP_STRUCT__entry(
191 __field(u32, dev)
192 __field(u32, cfg5)
193 __field(u32, cfg6)
194 ),
195
196 TP_fast_assign(
197 __entry->dev = dev->primary->index;
198 __entry->cfg5 = cfg5;
199 __entry->cfg6 = cfg6;
200 ),
201
202 TP_printk("dev=%u, CFG5 0x%08x, CFG6 0x%08x",
203 __entry->dev,
204 __entry->cfg5,
205 __entry->cfg6)
206);
207
208TRACE_EVENT(v3d_submit_csd,
209 TP_PROTO(struct drm_device *dev,
210 uint64_t seqno),
211 TP_ARGS(dev, seqno),
212
213 TP_STRUCT__entry(
214 __field(u32, dev)
215 __field(u64, seqno)
216 ),
217
218 TP_fast_assign(
219 __entry->dev = dev->primary->index;
220 __entry->seqno = seqno;
221 ),
222
223 TP_printk("dev=%u, seqno=%llu",
224 __entry->dev,
225 __entry->seqno)
226);
227
228TRACE_EVENT(v3d_cache_clean_begin,
229 TP_PROTO(struct drm_device *dev),
230 TP_ARGS(dev),
231
232 TP_STRUCT__entry(
233 __field(u32, dev)
234 ),
235
236 TP_fast_assign(
237 __entry->dev = dev->primary->index;
238 ),
239
240 TP_printk("dev=%u",
241 __entry->dev)
242);
243
244TRACE_EVENT(v3d_cache_clean_end,
245 TP_PROTO(struct drm_device *dev),
246 TP_ARGS(dev),
247
248 TP_STRUCT__entry(
249 __field(u32, dev)
250 ),
251
252 TP_fast_assign(
253 __entry->dev = dev->primary->index;
254 ),
255
256 TP_printk("dev=%u",
257 __entry->dev)
258);
259
260TRACE_EVENT(v3d_reset_begin,
261 TP_PROTO(struct drm_device *dev),
262 TP_ARGS(dev),
263
264 TP_STRUCT__entry(
265 __field(u32, dev)
266 ),
267
268 TP_fast_assign(
269 __entry->dev = dev->primary->index;
270 ),
271
272 TP_printk("dev=%u",
273 __entry->dev)
274);
275
276TRACE_EVENT(v3d_reset_end,
277 TP_PROTO(struct drm_device *dev),
278 TP_ARGS(dev),
279
280 TP_STRUCT__entry(
281 __field(u32, dev)
282 ),
283
284 TP_fast_assign(
285 __entry->dev = dev->primary->index;
286 ),
287
288 TP_printk("dev=%u",
289 __entry->dev)
290);
291
292#endif /* _V3D_TRACE_H_ */
293
294/* This part must be outside protection */
295#undef TRACE_INCLUDE_PATH
296#define TRACE_INCLUDE_PATH .
297#include <trace/define_trace.h>