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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / net / ethernet / realtek / r8169_main.c
blob: 14bac7c0e6f90898f9e4ea6a83f476c25c5fe6a1 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/pci.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/ethtool.h>
20#include <linux/phy.h>
21#include <linux/if_vlan.h>
22#include <linux/crc32.h>
23#include <linux/in.h>
24#include <linux/io.h>
25#include <linux/ip.h>
26#include <linux/tcp.h>
27#include <linux/interrupt.h>
28#include <linux/dma-mapping.h>
29#include <linux/pm_runtime.h>
30#include <linux/prefetch.h>
31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
33
34#include "r8169_firmware.h"
35
36#define MODULENAME "r8169"
37
38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58
59#define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
64#define MC_FILTER_LIMIT 32
65
66#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
67#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69#define R8169_REGS_SIZE 256
70#define R8169_RX_BUF_SIZE (SZ_16K - 1)
71#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
73#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76#define RTL_CFG_NO_GBIT 1
77
78/* write/read MMIO register */
79#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86enum mac_version {
87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_VER_60,
139 RTL_GIGA_MAC_VER_61,
140 RTL_GIGA_MAC_NONE
141};
142
143#define JUMBO_1K ETH_DATA_LEN
144#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
145#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
146#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
147#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
148
149static const struct {
150 const char *name;
151 const char *fw_name;
152} rtl_chip_infos[] = {
153 /* PCI devices. */
154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
159 /* PCI-E devices. */
160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
207};
208
209static const struct pci_device_id rtl8169_pci_tbl[] = {
210 { PCI_VDEVICE(REALTEK, 0x2502) },
211 { PCI_VDEVICE(REALTEK, 0x2600) },
212 { PCI_VDEVICE(REALTEK, 0x8129) },
213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
214 { PCI_VDEVICE(REALTEK, 0x8161) },
215 { PCI_VDEVICE(REALTEK, 0x8162) },
216 { PCI_VDEVICE(REALTEK, 0x8167) },
217 { PCI_VDEVICE(REALTEK, 0x8168) },
218 { PCI_VDEVICE(NCUBE, 0x8168) },
219 { PCI_VDEVICE(REALTEK, 0x8169) },
220 { PCI_VENDOR_ID_DLINK, 0x4300,
221 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
222 { PCI_VDEVICE(DLINK, 0x4300) },
223 { PCI_VDEVICE(DLINK, 0x4302) },
224 { PCI_VDEVICE(AT, 0xc107) },
225 { PCI_VDEVICE(USR, 0x0116) },
226 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
227 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
228 { PCI_VDEVICE(REALTEK, 0x8125) },
229 { PCI_VDEVICE(REALTEK, 0x3000) },
230 {}
231};
232
233MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
234
235static struct {
236 u32 msg_enable;
237} debug = { -1 };
238
239enum rtl_registers {
240 MAC0 = 0, /* Ethernet hardware address. */
241 MAC4 = 4,
242 MAR0 = 8, /* Multicast filter. */
243 CounterAddrLow = 0x10,
244 CounterAddrHigh = 0x14,
245 TxDescStartAddrLow = 0x20,
246 TxDescStartAddrHigh = 0x24,
247 TxHDescStartAddrLow = 0x28,
248 TxHDescStartAddrHigh = 0x2c,
249 FLASH = 0x30,
250 ERSR = 0x36,
251 ChipCmd = 0x37,
252 TxPoll = 0x38,
253 IntrMask = 0x3c,
254 IntrStatus = 0x3e,
255
256 TxConfig = 0x40,
257#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
258#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
259
260 RxConfig = 0x44,
261#define RX128_INT_EN (1 << 15) /* 8111c and later */
262#define RX_MULTI_EN (1 << 14) /* 8111c only */
263#define RXCFG_FIFO_SHIFT 13
264 /* No threshold before first PCI xfer */
265#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
266#define RX_EARLY_OFF (1 << 11)
267#define RXCFG_DMA_SHIFT 8
268 /* Unlimited maximum PCI burst. */
269#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
270
271 RxMissed = 0x4c,
272 Cfg9346 = 0x50,
273 Config0 = 0x51,
274 Config1 = 0x52,
275 Config2 = 0x53,
276#define PME_SIGNAL (1 << 5) /* 8168c and later */
277
278 Config3 = 0x54,
279 Config4 = 0x55,
280 Config5 = 0x56,
281 PHYAR = 0x60,
282 PHYstatus = 0x6c,
283 RxMaxSize = 0xda,
284 CPlusCmd = 0xe0,
285 IntrMitigate = 0xe2,
286
287#define RTL_COALESCE_MASK 0x0f
288#define RTL_COALESCE_SHIFT 4
289#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
290#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
291
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
295
296#define NoEarlyTx 0x3f /* Max value : no early transmit. */
297
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299
300#define TxPacketMax (8064 >> 7)
301#define EarlySize 0x27
302
303 FuncEvent = 0xf0,
304 FuncEventMask = 0xf4,
305 FuncPresetState = 0xf8,
306 IBCR0 = 0xf8,
307 IBCR2 = 0xf9,
308 IBIMR0 = 0xfa,
309 IBISR0 = 0xfb,
310 FuncForceEvent = 0xfc,
311};
312
313enum rtl8168_8101_registers {
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316#define CSIAR_FLAG 0x80000000
317#define CSIAR_WRITE_CMD 0x80000000
318#define CSIAR_BYTE_ENABLE 0x0000f000
319#define CSIAR_ADDR_MASK 0x00000fff
320 PMCH = 0x6f,
321 EPHYAR = 0x80,
322#define EPHYAR_FLAG 0x80000000
323#define EPHYAR_WRITE_CMD 0x80000000
324#define EPHYAR_REG_MASK 0x1f
325#define EPHYAR_REG_SHIFT 16
326#define EPHYAR_DATA_MASK 0xffff
327 DLLPR = 0xd0,
328#define PFM_EN (1 << 6)
329#define TX_10M_PS_EN (1 << 7)
330 DBG_REG = 0xd1,
331#define FIX_NAK_1 (1 << 4)
332#define FIX_NAK_2 (1 << 3)
333 TWSI = 0xd2,
334 MCU = 0xd3,
335#define NOW_IS_OOB (1 << 7)
336#define TX_EMPTY (1 << 5)
337#define RX_EMPTY (1 << 4)
338#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
339#define EN_NDP (1 << 3)
340#define EN_OOB_RESET (1 << 2)
341#define LINK_LIST_RDY (1 << 1)
342 EFUSEAR = 0xdc,
343#define EFUSEAR_FLAG 0x80000000
344#define EFUSEAR_WRITE_CMD 0x80000000
345#define EFUSEAR_READ_CMD 0x00000000
346#define EFUSEAR_REG_MASK 0x03ff
347#define EFUSEAR_REG_SHIFT 8
348#define EFUSEAR_DATA_MASK 0xff
349 MISC_1 = 0xf2,
350#define PFM_D3COLD_EN (1 << 6)
351};
352
353enum rtl8168_registers {
354 LED_FREQ = 0x1a,
355 EEE_LED = 0x1b,
356 ERIDR = 0x70,
357 ERIAR = 0x74,
358#define ERIAR_FLAG 0x80000000
359#define ERIAR_WRITE_CMD 0x80000000
360#define ERIAR_READ_CMD 0x00000000
361#define ERIAR_ADDR_BYTE_ALIGN 4
362#define ERIAR_TYPE_SHIFT 16
363#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
364#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
365#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
366#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
367#define ERIAR_MASK_SHIFT 12
368#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
369#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
370#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
371#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
372#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
373 EPHY_RXER_NUM = 0x7c,
374 OCPDR = 0xb0, /* OCP GPHY access */
375#define OCPDR_WRITE_CMD 0x80000000
376#define OCPDR_READ_CMD 0x00000000
377#define OCPDR_REG_MASK 0x7f
378#define OCPDR_GPHY_REG_SHIFT 16
379#define OCPDR_DATA_MASK 0xffff
380 OCPAR = 0xb4,
381#define OCPAR_FLAG 0x80000000
382#define OCPAR_GPHY_WRITE_CMD 0x8000f060
383#define OCPAR_GPHY_READ_CMD 0x0000f060
384 GPHY_OCP = 0xb8,
385 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
386 MISC = 0xf0, /* 8168e only. */
387#define TXPLA_RST (1 << 29)
388#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
389#define PWM_EN (1 << 22)
390#define RXDV_GATED_EN (1 << 19)
391#define EARLY_TALLY_EN (1 << 16)
392};
393
394enum rtl8125_registers {
395 IntrMask_8125 = 0x38,
396 IntrStatus_8125 = 0x3c,
397 TxPoll_8125 = 0x90,
398 MAC0_BKP = 0x19e0,
399};
400
401#define RX_VLAN_INNER_8125 BIT(22)
402#define RX_VLAN_OUTER_8125 BIT(23)
403#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
404
405#define RX_FETCH_DFLT_8125 (8 << 27)
406
407enum rtl_register_content {
408 /* InterruptStatusBits */
409 SYSErr = 0x8000,
410 PCSTimeout = 0x4000,
411 SWInt = 0x0100,
412 TxDescUnavail = 0x0080,
413 RxFIFOOver = 0x0040,
414 LinkChg = 0x0020,
415 RxOverflow = 0x0010,
416 TxErr = 0x0008,
417 TxOK = 0x0004,
418 RxErr = 0x0002,
419 RxOK = 0x0001,
420
421 /* RxStatusDesc */
422 RxRWT = (1 << 22),
423 RxRES = (1 << 21),
424 RxRUNT = (1 << 20),
425 RxCRC = (1 << 19),
426
427 /* ChipCmdBits */
428 StopReq = 0x80,
429 CmdReset = 0x10,
430 CmdRxEnb = 0x08,
431 CmdTxEnb = 0x04,
432 RxBufEmpty = 0x01,
433
434 /* TXPoll register p.5 */
435 HPQ = 0x80, /* Poll cmd on the high prio queue */
436 NPQ = 0x40, /* Poll cmd on the low prio queue */
437 FSWInt = 0x01, /* Forced software interrupt */
438
439 /* Cfg9346Bits */
440 Cfg9346_Lock = 0x00,
441 Cfg9346_Unlock = 0xc0,
442
443 /* rx_mode_bits */
444 AcceptErr = 0x20,
445 AcceptRunt = 0x10,
446 AcceptBroadcast = 0x08,
447 AcceptMulticast = 0x04,
448 AcceptMyPhys = 0x02,
449 AcceptAllPhys = 0x01,
450#define RX_CONFIG_ACCEPT_MASK 0x3f
451
452 /* TxConfigBits */
453 TxInterFrameGapShift = 24,
454 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
455
456 /* Config1 register p.24 */
457 LEDS1 = (1 << 7),
458 LEDS0 = (1 << 6),
459 Speed_down = (1 << 4),
460 MEMMAP = (1 << 3),
461 IOMAP = (1 << 2),
462 VPD = (1 << 1),
463 PMEnable = (1 << 0), /* Power Management Enable */
464
465 /* Config2 register p. 25 */
466 ClkReqEn = (1 << 7), /* Clock Request Enable */
467 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
468 PCI_Clock_66MHz = 0x01,
469 PCI_Clock_33MHz = 0x00,
470
471 /* Config3 register p.25 */
472 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
473 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
474 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
475 Rdy_to_L23 = (1 << 1), /* L23 Enable */
476 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
477
478 /* Config4 register */
479 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
480
481 /* Config5 register p.27 */
482 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
483 MWF = (1 << 5), /* Accept Multicast wakeup frame */
484 UWF = (1 << 4), /* Accept Unicast wakeup frame */
485 Spi_en = (1 << 3),
486 LanWake = (1 << 1), /* LanWake enable/disable */
487 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
488 ASPM_en = (1 << 0), /* ASPM enable */
489
490 /* CPlusCmd p.31 */
491 EnableBist = (1 << 15), // 8168 8101
492 Mac_dbgo_oe = (1 << 14), // 8168 8101
493 Normal_mode = (1 << 13), // unused
494 Force_half_dup = (1 << 12), // 8168 8101
495 Force_rxflow_en = (1 << 11), // 8168 8101
496 Force_txflow_en = (1 << 10), // 8168 8101
497 Cxpl_dbg_sel = (1 << 9), // 8168 8101
498 ASF = (1 << 8), // 8168 8101
499 PktCntrDisable = (1 << 7), // 8168 8101
500 Mac_dbgo_sel = 0x001c, // 8168
501 RxVlan = (1 << 6),
502 RxChkSum = (1 << 5),
503 PCIDAC = (1 << 4),
504 PCIMulRW = (1 << 3),
505#define INTT_MASK GENMASK(1, 0)
506#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
507
508 /* rtl8169_PHYstatus */
509 TBI_Enable = 0x80,
510 TxFlowCtrl = 0x40,
511 RxFlowCtrl = 0x20,
512 _1000bpsF = 0x10,
513 _100bps = 0x08,
514 _10bps = 0x04,
515 LinkStatus = 0x02,
516 FullDup = 0x01,
517
518 /* ResetCounterCommand */
519 CounterReset = 0x1,
520
521 /* DumpCounterCommand */
522 CounterDump = 0x8,
523
524 /* magic enable v2 */
525 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
526};
527
528enum rtl_desc_bit {
529 /* First doubleword. */
530 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
531 RingEnd = (1 << 30), /* End of descriptor ring */
532 FirstFrag = (1 << 29), /* First segment of a packet */
533 LastFrag = (1 << 28), /* Final segment of a packet */
534};
535
536/* Generic case. */
537enum rtl_tx_desc_bit {
538 /* First doubleword. */
539 TD_LSO = (1 << 27), /* Large Send Offload */
540#define TD_MSS_MAX 0x07ffu /* MSS value */
541
542 /* Second doubleword. */
543 TxVlanTag = (1 << 17), /* Add VLAN tag */
544};
545
546/* 8169, 8168b and 810x except 8102e. */
547enum rtl_tx_desc_bit_0 {
548 /* First doubleword. */
549#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
550 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
551 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
552 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
553};
554
555/* 8102e, 8168c and beyond. */
556enum rtl_tx_desc_bit_1 {
557 /* First doubleword. */
558 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
559 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
560#define GTTCPHO_SHIFT 18
561#define GTTCPHO_MAX 0x7f
562
563 /* Second doubleword. */
564#define TCPHO_SHIFT 18
565#define TCPHO_MAX 0x3ff
566#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
567 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
568 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
569 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
570 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
571};
572
573enum rtl_rx_desc_bit {
574 /* Rx private */
575 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
576 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
577
578#define RxProtoUDP (PID1)
579#define RxProtoTCP (PID0)
580#define RxProtoIP (PID1 | PID0)
581#define RxProtoMask RxProtoIP
582
583 IPFail = (1 << 16), /* IP checksum failed */
584 UDPFail = (1 << 15), /* UDP/IP checksum failed */
585 TCPFail = (1 << 14), /* TCP/IP checksum failed */
586 RxVlanTag = (1 << 16), /* VLAN tag available */
587};
588
589#define RsvdMask 0x3fffc000
590
591#define RTL_GSO_MAX_SIZE_V1 32000
592#define RTL_GSO_MAX_SEGS_V1 24
593#define RTL_GSO_MAX_SIZE_V2 64000
594#define RTL_GSO_MAX_SEGS_V2 64
595
596struct TxDesc {
597 __le32 opts1;
598 __le32 opts2;
599 __le64 addr;
600};
601
602struct RxDesc {
603 __le32 opts1;
604 __le32 opts2;
605 __le64 addr;
606};
607
608struct ring_info {
609 struct sk_buff *skb;
610 u32 len;
611};
612
613struct rtl8169_counters {
614 __le64 tx_packets;
615 __le64 rx_packets;
616 __le64 tx_errors;
617 __le32 rx_errors;
618 __le16 rx_missed;
619 __le16 align_errors;
620 __le32 tx_one_collision;
621 __le32 tx_multi_collision;
622 __le64 rx_unicast;
623 __le64 rx_broadcast;
624 __le32 rx_multicast;
625 __le16 tx_aborted;
626 __le16 tx_underrun;
627 /* new since RTL8125 */
628 __le64 tx_octets;
629 __le64 rx_octets;
630 __le64 rx_multicast64;
631 __le64 tx_unicast64;
632 __le64 tx_broadcast64;
633 __le64 tx_multicast64;
634 __le32 tx_pause_on;
635 __le32 tx_pause_off;
636 __le32 tx_pause_all;
637 __le32 tx_deferred;
638 __le32 tx_late_collision;
639 __le32 tx_all_collision;
640 __le32 tx_aborted32;
641 __le32 align_errors32;
642 __le32 rx_frame_too_long;
643 __le32 rx_runt;
644 __le32 rx_pause_on;
645 __le32 rx_pause_off;
646 __le32 rx_pause_all;
647 __le32 rx_unknown_opcode;
648 __le32 rx_mac_error;
649 __le32 tx_underrun32;
650 __le32 rx_mac_missed;
651 __le32 rx_tcam_dropped;
652 __le32 tdu;
653 __le32 rdu;
654};
655
656struct rtl8169_tc_offsets {
657 bool inited;
658 __le64 tx_errors;
659 __le32 tx_multi_collision;
660 __le16 tx_aborted;
661};
662
663enum rtl_flag {
664 RTL_FLAG_TASK_ENABLED = 0,
665 RTL_FLAG_TASK_RESET_PENDING,
666 RTL_FLAG_MAX
667};
668
669struct rtl8169_stats {
670 u64 packets;
671 u64 bytes;
672 struct u64_stats_sync syncp;
673};
674
675struct rtl8169_private {
676 void __iomem *mmio_addr; /* memory map physical address */
677 struct pci_dev *pci_dev;
678 struct net_device *dev;
679 struct phy_device *phydev;
680 struct napi_struct napi;
681 u32 msg_enable;
682 enum mac_version mac_version;
683 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
684 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
685 u32 dirty_tx;
686 struct rtl8169_stats rx_stats;
687 struct rtl8169_stats tx_stats;
688 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
689 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
690 dma_addr_t TxPhyAddr;
691 dma_addr_t RxPhyAddr;
692 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
693 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
694 u16 cp_cmd;
695 u32 irq_mask;
696 struct clk *clk;
697
698 struct {
699 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
700 struct mutex mutex;
701 struct work_struct work;
702 } wk;
703
704 unsigned irq_enabled:1;
705 unsigned supports_gmii:1;
706 unsigned aspm_manageable:1;
707 dma_addr_t counters_phys_addr;
708 struct rtl8169_counters *counters;
709 struct rtl8169_tc_offsets tc_offset;
710 u32 saved_wolopts;
711 int eee_adv;
712
713 const char *fw_name;
714 struct rtl_fw *rtl_fw;
715
716 u32 ocp_base;
717};
718
719typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
720
721MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
722MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
723module_param_named(debug, debug.msg_enable, int, 0);
724MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
725MODULE_SOFTDEP("pre: realtek");
726MODULE_LICENSE("GPL");
727MODULE_FIRMWARE(FIRMWARE_8168D_1);
728MODULE_FIRMWARE(FIRMWARE_8168D_2);
729MODULE_FIRMWARE(FIRMWARE_8168E_1);
730MODULE_FIRMWARE(FIRMWARE_8168E_2);
731MODULE_FIRMWARE(FIRMWARE_8168E_3);
732MODULE_FIRMWARE(FIRMWARE_8105E_1);
733MODULE_FIRMWARE(FIRMWARE_8168F_1);
734MODULE_FIRMWARE(FIRMWARE_8168F_2);
735MODULE_FIRMWARE(FIRMWARE_8402_1);
736MODULE_FIRMWARE(FIRMWARE_8411_1);
737MODULE_FIRMWARE(FIRMWARE_8411_2);
738MODULE_FIRMWARE(FIRMWARE_8106E_1);
739MODULE_FIRMWARE(FIRMWARE_8106E_2);
740MODULE_FIRMWARE(FIRMWARE_8168G_2);
741MODULE_FIRMWARE(FIRMWARE_8168G_3);
742MODULE_FIRMWARE(FIRMWARE_8168H_1);
743MODULE_FIRMWARE(FIRMWARE_8168H_2);
744MODULE_FIRMWARE(FIRMWARE_8107E_1);
745MODULE_FIRMWARE(FIRMWARE_8107E_2);
746MODULE_FIRMWARE(FIRMWARE_8125A_3);
747
748static inline struct device *tp_to_dev(struct rtl8169_private *tp)
749{
750 return &tp->pci_dev->dev;
751}
752
753static void rtl_lock_work(struct rtl8169_private *tp)
754{
755 mutex_lock(&tp->wk.mutex);
756}
757
758static void rtl_unlock_work(struct rtl8169_private *tp)
759{
760 mutex_unlock(&tp->wk.mutex);
761}
762
763static void rtl_lock_config_regs(struct rtl8169_private *tp)
764{
765 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
766}
767
768static void rtl_unlock_config_regs(struct rtl8169_private *tp)
769{
770 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
771}
772
773static bool rtl_is_8125(struct rtl8169_private *tp)
774{
775 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
776}
777
778static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
779{
780 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
781 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
782 tp->mac_version <= RTL_GIGA_MAC_VER_51;
783}
784
785static bool rtl_supports_eee(struct rtl8169_private *tp)
786{
787 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
788 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
789 tp->mac_version != RTL_GIGA_MAC_VER_39;
790}
791
792static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
793{
794 int i;
795
796 for (i = 0; i < ETH_ALEN; i++)
797 mac[i] = RTL_R8(tp, reg + i);
798}
799
800struct rtl_cond {
801 bool (*check)(struct rtl8169_private *);
802 const char *msg;
803};
804
805static void rtl_udelay(unsigned int d)
806{
807 udelay(d);
808}
809
810static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
811 void (*delay)(unsigned int), unsigned int d, int n,
812 bool high)
813{
814 int i;
815
816 for (i = 0; i < n; i++) {
817 if (c->check(tp) == high)
818 return true;
819 delay(d);
820 }
821 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
822 c->msg, !high, n, d);
823 return false;
824}
825
826static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
827 const struct rtl_cond *c,
828 unsigned int d, int n)
829{
830 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
831}
832
833static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
834 const struct rtl_cond *c,
835 unsigned int d, int n)
836{
837 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
838}
839
840static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
841 const struct rtl_cond *c,
842 unsigned int d, int n)
843{
844 return rtl_loop_wait(tp, c, msleep, d, n, true);
845}
846
847static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
848 const struct rtl_cond *c,
849 unsigned int d, int n)
850{
851 return rtl_loop_wait(tp, c, msleep, d, n, false);
852}
853
854#define DECLARE_RTL_COND(name) \
855static bool name ## _check(struct rtl8169_private *); \
856 \
857static const struct rtl_cond name = { \
858 .check = name ## _check, \
859 .msg = #name \
860}; \
861 \
862static bool name ## _check(struct rtl8169_private *tp)
863
864static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
865{
866 if (reg & 0xffff0001) {
867 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
868 return true;
869 }
870 return false;
871}
872
873DECLARE_RTL_COND(rtl_ocp_gphy_cond)
874{
875 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
876}
877
878static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
879{
880 if (rtl_ocp_reg_failure(tp, reg))
881 return;
882
883 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
884
885 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
886}
887
888static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
889{
890 if (rtl_ocp_reg_failure(tp, reg))
891 return 0;
892
893 RTL_W32(tp, GPHY_OCP, reg << 15);
894
895 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
896 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
897}
898
899static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
900{
901 if (rtl_ocp_reg_failure(tp, reg))
902 return;
903
904 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
905}
906
907static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
908{
909 if (rtl_ocp_reg_failure(tp, reg))
910 return 0;
911
912 RTL_W32(tp, OCPDR, reg << 15);
913
914 return RTL_R32(tp, OCPDR);
915}
916
917static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
918 u16 set)
919{
920 u16 data = r8168_mac_ocp_read(tp, reg);
921
922 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
923}
924
925#define OCP_STD_PHY_BASE 0xa400
926
927static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
928{
929 if (reg == 0x1f) {
930 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
931 return;
932 }
933
934 if (tp->ocp_base != OCP_STD_PHY_BASE)
935 reg -= 0x10;
936
937 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
938}
939
940static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
941{
942 if (reg == 0x1f)
943 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
944
945 if (tp->ocp_base != OCP_STD_PHY_BASE)
946 reg -= 0x10;
947
948 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
949}
950
951static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
952{
953 if (reg == 0x1f) {
954 tp->ocp_base = value << 4;
955 return;
956 }
957
958 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
959}
960
961static int mac_mcu_read(struct rtl8169_private *tp, int reg)
962{
963 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
964}
965
966DECLARE_RTL_COND(rtl_phyar_cond)
967{
968 return RTL_R32(tp, PHYAR) & 0x80000000;
969}
970
971static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
972{
973 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
974
975 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
976 /*
977 * According to hardware specs a 20us delay is required after write
978 * complete indication, but before sending next command.
979 */
980 udelay(20);
981}
982
983static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
984{
985 int value;
986
987 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
988
989 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
990 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
991
992 /*
993 * According to hardware specs a 20us delay is required after read
994 * complete indication, but before sending next command.
995 */
996 udelay(20);
997
998 return value;
999}
1000
1001DECLARE_RTL_COND(rtl_ocpar_cond)
1002{
1003 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1004}
1005
1006static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1007{
1008 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1009 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1010 RTL_W32(tp, EPHY_RXER_NUM, 0);
1011
1012 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1013}
1014
1015static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1016{
1017 r8168dp_1_mdio_access(tp, reg,
1018 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1019}
1020
1021static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1022{
1023 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1024
1025 mdelay(1);
1026 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1027 RTL_W32(tp, EPHY_RXER_NUM, 0);
1028
1029 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1030 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1031}
1032
1033#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1034
1035static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1036{
1037 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1038}
1039
1040static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1041{
1042 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1043}
1044
1045static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1046{
1047 r8168dp_2_mdio_start(tp);
1048
1049 r8169_mdio_write(tp, reg, value);
1050
1051 r8168dp_2_mdio_stop(tp);
1052}
1053
1054static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1055{
1056 int value;
1057
1058 /* Work around issue with chip reporting wrong PHY ID */
1059 if (reg == MII_PHYSID2)
1060 return 0xc912;
1061
1062 r8168dp_2_mdio_start(tp);
1063
1064 value = r8169_mdio_read(tp, reg);
1065
1066 r8168dp_2_mdio_stop(tp);
1067
1068 return value;
1069}
1070
1071static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1072{
1073 switch (tp->mac_version) {
1074 case RTL_GIGA_MAC_VER_27:
1075 r8168dp_1_mdio_write(tp, location, val);
1076 break;
1077 case RTL_GIGA_MAC_VER_28:
1078 case RTL_GIGA_MAC_VER_31:
1079 r8168dp_2_mdio_write(tp, location, val);
1080 break;
1081 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1082 r8168g_mdio_write(tp, location, val);
1083 break;
1084 default:
1085 r8169_mdio_write(tp, location, val);
1086 break;
1087 }
1088}
1089
1090static int rtl_readphy(struct rtl8169_private *tp, int location)
1091{
1092 switch (tp->mac_version) {
1093 case RTL_GIGA_MAC_VER_27:
1094 return r8168dp_1_mdio_read(tp, location);
1095 case RTL_GIGA_MAC_VER_28:
1096 case RTL_GIGA_MAC_VER_31:
1097 return r8168dp_2_mdio_read(tp, location);
1098 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1099 return r8168g_mdio_read(tp, location);
1100 default:
1101 return r8169_mdio_read(tp, location);
1102 }
1103}
1104
1105static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1106{
1107 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1108}
1109
1110static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1111{
1112 int val;
1113
1114 val = rtl_readphy(tp, reg_addr);
1115 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1116}
1117
1118DECLARE_RTL_COND(rtl_ephyar_cond)
1119{
1120 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1121}
1122
1123static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1124{
1125 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1126 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1127
1128 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1129
1130 udelay(10);
1131}
1132
1133static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1134{
1135 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1136
1137 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1138 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1139}
1140
1141DECLARE_RTL_COND(rtl_eriar_cond)
1142{
1143 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1144}
1145
1146static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1147 u32 val, int type)
1148{
1149 BUG_ON((addr & 3) || (mask == 0));
1150 RTL_W32(tp, ERIDR, val);
1151 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1152
1153 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1154}
1155
1156static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1157 u32 val)
1158{
1159 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1160}
1161
1162static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1163{
1164 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1165
1166 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1167 RTL_R32(tp, ERIDR) : ~0;
1168}
1169
1170static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1171{
1172 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1173}
1174
1175static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1176 u32 m)
1177{
1178 u32 val;
1179
1180 val = rtl_eri_read(tp, addr);
1181 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1182}
1183
1184static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1185 u32 p)
1186{
1187 rtl_w0w1_eri(tp, addr, mask, p, 0);
1188}
1189
1190static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1191 u32 m)
1192{
1193 rtl_w0w1_eri(tp, addr, mask, 0, m);
1194}
1195
1196static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1197{
1198 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1199 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1200 RTL_R32(tp, OCPDR) : ~0;
1201}
1202
1203static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1204{
1205 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1206}
1207
1208static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1209 u32 data)
1210{
1211 RTL_W32(tp, OCPDR, data);
1212 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1213 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1214}
1215
1216static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1217 u32 data)
1218{
1219 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1220 data, ERIAR_OOB);
1221}
1222
1223static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1224{
1225 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1226
1227 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1228}
1229
1230#define OOB_CMD_RESET 0x00
1231#define OOB_CMD_DRIVER_START 0x05
1232#define OOB_CMD_DRIVER_STOP 0x06
1233
1234static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1235{
1236 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1237}
1238
1239DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1240{
1241 u16 reg;
1242
1243 reg = rtl8168_get_ocp_reg(tp);
1244
1245 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1246}
1247
1248DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1249{
1250 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1251}
1252
1253DECLARE_RTL_COND(rtl_ocp_tx_cond)
1254{
1255 return RTL_R8(tp, IBISR0) & 0x20;
1256}
1257
1258static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1259{
1260 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1261 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1262 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1263 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1264}
1265
1266static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1267{
1268 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1269 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1270}
1271
1272static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1273{
1274 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1275 r8168ep_ocp_write(tp, 0x01, 0x30,
1276 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1277 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1278}
1279
1280static void rtl8168_driver_start(struct rtl8169_private *tp)
1281{
1282 switch (tp->mac_version) {
1283 case RTL_GIGA_MAC_VER_27:
1284 case RTL_GIGA_MAC_VER_28:
1285 case RTL_GIGA_MAC_VER_31:
1286 rtl8168dp_driver_start(tp);
1287 break;
1288 case RTL_GIGA_MAC_VER_49:
1289 case RTL_GIGA_MAC_VER_50:
1290 case RTL_GIGA_MAC_VER_51:
1291 rtl8168ep_driver_start(tp);
1292 break;
1293 default:
1294 BUG();
1295 break;
1296 }
1297}
1298
1299static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1300{
1301 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1302 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1303}
1304
1305static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1306{
1307 rtl8168ep_stop_cmac(tp);
1308 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1309 r8168ep_ocp_write(tp, 0x01, 0x30,
1310 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1311 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1312}
1313
1314static void rtl8168_driver_stop(struct rtl8169_private *tp)
1315{
1316 switch (tp->mac_version) {
1317 case RTL_GIGA_MAC_VER_27:
1318 case RTL_GIGA_MAC_VER_28:
1319 case RTL_GIGA_MAC_VER_31:
1320 rtl8168dp_driver_stop(tp);
1321 break;
1322 case RTL_GIGA_MAC_VER_49:
1323 case RTL_GIGA_MAC_VER_50:
1324 case RTL_GIGA_MAC_VER_51:
1325 rtl8168ep_driver_stop(tp);
1326 break;
1327 default:
1328 BUG();
1329 break;
1330 }
1331}
1332
1333static bool r8168dp_check_dash(struct rtl8169_private *tp)
1334{
1335 u16 reg = rtl8168_get_ocp_reg(tp);
1336
1337 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1338}
1339
1340static bool r8168ep_check_dash(struct rtl8169_private *tp)
1341{
1342 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1343}
1344
1345static bool r8168_check_dash(struct rtl8169_private *tp)
1346{
1347 switch (tp->mac_version) {
1348 case RTL_GIGA_MAC_VER_27:
1349 case RTL_GIGA_MAC_VER_28:
1350 case RTL_GIGA_MAC_VER_31:
1351 return r8168dp_check_dash(tp);
1352 case RTL_GIGA_MAC_VER_49:
1353 case RTL_GIGA_MAC_VER_50:
1354 case RTL_GIGA_MAC_VER_51:
1355 return r8168ep_check_dash(tp);
1356 default:
1357 return false;
1358 }
1359}
1360
1361static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1362{
1363 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1364 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1365}
1366
1367DECLARE_RTL_COND(rtl_efusear_cond)
1368{
1369 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1370}
1371
1372static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1373{
1374 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1375
1376 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1377 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1378}
1379
1380static u32 rtl_get_events(struct rtl8169_private *tp)
1381{
1382 if (rtl_is_8125(tp))
1383 return RTL_R32(tp, IntrStatus_8125);
1384 else
1385 return RTL_R16(tp, IntrStatus);
1386}
1387
1388static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1389{
1390 if (rtl_is_8125(tp))
1391 RTL_W32(tp, IntrStatus_8125, bits);
1392 else
1393 RTL_W16(tp, IntrStatus, bits);
1394}
1395
1396static void rtl_irq_disable(struct rtl8169_private *tp)
1397{
1398 if (rtl_is_8125(tp))
1399 RTL_W32(tp, IntrMask_8125, 0);
1400 else
1401 RTL_W16(tp, IntrMask, 0);
1402 tp->irq_enabled = 0;
1403}
1404
1405#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1406#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1407#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1408
1409static void rtl_irq_enable(struct rtl8169_private *tp)
1410{
1411 tp->irq_enabled = 1;
1412 if (rtl_is_8125(tp))
1413 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1414 else
1415 RTL_W16(tp, IntrMask, tp->irq_mask);
1416}
1417
1418static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1419{
1420 rtl_irq_disable(tp);
1421 rtl_ack_events(tp, 0xffffffff);
1422 /* PCI commit */
1423 RTL_R8(tp, ChipCmd);
1424}
1425
1426static void rtl_link_chg_patch(struct rtl8169_private *tp)
1427{
1428 struct net_device *dev = tp->dev;
1429 struct phy_device *phydev = tp->phydev;
1430
1431 if (!netif_running(dev))
1432 return;
1433
1434 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1435 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1436 if (phydev->speed == SPEED_1000) {
1437 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1439 } else if (phydev->speed == SPEED_100) {
1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1442 } else {
1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1445 }
1446 rtl_reset_packet_filter(tp);
1447 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1448 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1449 if (phydev->speed == SPEED_1000) {
1450 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1451 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1452 } else {
1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1455 }
1456 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1457 if (phydev->speed == SPEED_10) {
1458 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1459 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1460 } else {
1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1462 }
1463 }
1464}
1465
1466#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1467
1468static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1469{
1470 struct rtl8169_private *tp = netdev_priv(dev);
1471
1472 rtl_lock_work(tp);
1473 wol->supported = WAKE_ANY;
1474 wol->wolopts = tp->saved_wolopts;
1475 rtl_unlock_work(tp);
1476}
1477
1478static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1479{
1480 static const struct {
1481 u32 opt;
1482 u16 reg;
1483 u8 mask;
1484 } cfg[] = {
1485 { WAKE_PHY, Config3, LinkUp },
1486 { WAKE_UCAST, Config5, UWF },
1487 { WAKE_BCAST, Config5, BWF },
1488 { WAKE_MCAST, Config5, MWF },
1489 { WAKE_ANY, Config5, LanWake },
1490 { WAKE_MAGIC, Config3, MagicPacket }
1491 };
1492 unsigned int i, tmp = ARRAY_SIZE(cfg);
1493 u8 options;
1494
1495 rtl_unlock_config_regs(tp);
1496
1497 if (rtl_is_8168evl_up(tp)) {
1498 tmp--;
1499 if (wolopts & WAKE_MAGIC)
1500 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1501 MagicPacket_v2);
1502 else
1503 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1504 MagicPacket_v2);
1505 } else if (rtl_is_8125(tp)) {
1506 tmp--;
1507 if (wolopts & WAKE_MAGIC)
1508 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1509 else
1510 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1511 }
1512
1513 for (i = 0; i < tmp; i++) {
1514 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1515 if (wolopts & cfg[i].opt)
1516 options |= cfg[i].mask;
1517 RTL_W8(tp, cfg[i].reg, options);
1518 }
1519
1520 switch (tp->mac_version) {
1521 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1522 options = RTL_R8(tp, Config1) & ~PMEnable;
1523 if (wolopts)
1524 options |= PMEnable;
1525 RTL_W8(tp, Config1, options);
1526 break;
1527 case RTL_GIGA_MAC_VER_34:
1528 case RTL_GIGA_MAC_VER_37:
1529 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1530 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1531 if (wolopts)
1532 options |= PME_SIGNAL;
1533 RTL_W8(tp, Config2, options);
1534 break;
1535 default:
1536 break;
1537 }
1538
1539 rtl_lock_config_regs(tp);
1540
1541 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1542 tp->dev->wol_enabled = wolopts ? 1 : 0;
1543}
1544
1545static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1546{
1547 struct rtl8169_private *tp = netdev_priv(dev);
1548 struct device *d = tp_to_dev(tp);
1549
1550 if (wol->wolopts & ~WAKE_ANY)
1551 return -EINVAL;
1552
1553 pm_runtime_get_noresume(d);
1554
1555 rtl_lock_work(tp);
1556
1557 tp->saved_wolopts = wol->wolopts;
1558
1559 if (pm_runtime_active(d))
1560 __rtl8169_set_wol(tp, tp->saved_wolopts);
1561
1562 rtl_unlock_work(tp);
1563
1564 pm_runtime_put_noidle(d);
1565
1566 return 0;
1567}
1568
1569static void rtl8169_get_drvinfo(struct net_device *dev,
1570 struct ethtool_drvinfo *info)
1571{
1572 struct rtl8169_private *tp = netdev_priv(dev);
1573 struct rtl_fw *rtl_fw = tp->rtl_fw;
1574
1575 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1576 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1577 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1578 if (rtl_fw)
1579 strlcpy(info->fw_version, rtl_fw->version,
1580 sizeof(info->fw_version));
1581}
1582
1583static int rtl8169_get_regs_len(struct net_device *dev)
1584{
1585 return R8169_REGS_SIZE;
1586}
1587
1588static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1589 netdev_features_t features)
1590{
1591 struct rtl8169_private *tp = netdev_priv(dev);
1592
1593 if (dev->mtu > TD_MSS_MAX)
1594 features &= ~NETIF_F_ALL_TSO;
1595
1596 if (dev->mtu > JUMBO_1K &&
1597 tp->mac_version > RTL_GIGA_MAC_VER_06)
1598 features &= ~NETIF_F_IP_CSUM;
1599
1600 return features;
1601}
1602
1603static int rtl8169_set_features(struct net_device *dev,
1604 netdev_features_t features)
1605{
1606 struct rtl8169_private *tp = netdev_priv(dev);
1607 u32 rx_config;
1608
1609 rtl_lock_work(tp);
1610
1611 rx_config = RTL_R32(tp, RxConfig);
1612 if (features & NETIF_F_RXALL)
1613 rx_config |= (AcceptErr | AcceptRunt);
1614 else
1615 rx_config &= ~(AcceptErr | AcceptRunt);
1616
1617 if (rtl_is_8125(tp)) {
1618 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1619 rx_config |= RX_VLAN_8125;
1620 else
1621 rx_config &= ~RX_VLAN_8125;
1622 }
1623
1624 RTL_W32(tp, RxConfig, rx_config);
1625
1626 if (features & NETIF_F_RXCSUM)
1627 tp->cp_cmd |= RxChkSum;
1628 else
1629 tp->cp_cmd &= ~RxChkSum;
1630
1631 if (!rtl_is_8125(tp)) {
1632 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1633 tp->cp_cmd |= RxVlan;
1634 else
1635 tp->cp_cmd &= ~RxVlan;
1636 }
1637
1638 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1639 RTL_R16(tp, CPlusCmd);
1640
1641 rtl_unlock_work(tp);
1642
1643 return 0;
1644}
1645
1646static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1647{
1648 return (skb_vlan_tag_present(skb)) ?
1649 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1650}
1651
1652static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1653{
1654 u32 opts2 = le32_to_cpu(desc->opts2);
1655
1656 if (opts2 & RxVlanTag)
1657 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1658}
1659
1660static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1661 void *p)
1662{
1663 struct rtl8169_private *tp = netdev_priv(dev);
1664 u32 __iomem *data = tp->mmio_addr;
1665 u32 *dw = p;
1666 int i;
1667
1668 rtl_lock_work(tp);
1669 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1670 memcpy_fromio(dw++, data++, 4);
1671 rtl_unlock_work(tp);
1672}
1673
1674static u32 rtl8169_get_msglevel(struct net_device *dev)
1675{
1676 struct rtl8169_private *tp = netdev_priv(dev);
1677
1678 return tp->msg_enable;
1679}
1680
1681static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1682{
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684
1685 tp->msg_enable = value;
1686}
1687
1688static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1689 "tx_packets",
1690 "rx_packets",
1691 "tx_errors",
1692 "rx_errors",
1693 "rx_missed",
1694 "align_errors",
1695 "tx_single_collisions",
1696 "tx_multi_collisions",
1697 "unicast",
1698 "broadcast",
1699 "multicast",
1700 "tx_aborted",
1701 "tx_underrun",
1702};
1703
1704static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1705{
1706 switch (sset) {
1707 case ETH_SS_STATS:
1708 return ARRAY_SIZE(rtl8169_gstrings);
1709 default:
1710 return -EOPNOTSUPP;
1711 }
1712}
1713
1714DECLARE_RTL_COND(rtl_counters_cond)
1715{
1716 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1717}
1718
1719static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1720{
1721 dma_addr_t paddr = tp->counters_phys_addr;
1722 u32 cmd;
1723
1724 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1725 RTL_R32(tp, CounterAddrHigh);
1726 cmd = (u64)paddr & DMA_BIT_MASK(32);
1727 RTL_W32(tp, CounterAddrLow, cmd);
1728 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1729
1730 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1731}
1732
1733static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1734{
1735 /*
1736 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1737 * tally counters.
1738 */
1739 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1740 return true;
1741
1742 return rtl8169_do_counters(tp, CounterReset);
1743}
1744
1745static bool rtl8169_update_counters(struct rtl8169_private *tp)
1746{
1747 u8 val = RTL_R8(tp, ChipCmd);
1748
1749 /*
1750 * Some chips are unable to dump tally counters when the receiver
1751 * is disabled. If 0xff chip may be in a PCI power-save state.
1752 */
1753 if (!(val & CmdRxEnb) || val == 0xff)
1754 return true;
1755
1756 return rtl8169_do_counters(tp, CounterDump);
1757}
1758
1759static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1760{
1761 struct rtl8169_counters *counters = tp->counters;
1762 bool ret = false;
1763
1764 /*
1765 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1766 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1767 * reset by a power cycle, while the counter values collected by the
1768 * driver are reset at every driver unload/load cycle.
1769 *
1770 * To make sure the HW values returned by @get_stats64 match the SW
1771 * values, we collect the initial values at first open(*) and use them
1772 * as offsets to normalize the values returned by @get_stats64.
1773 *
1774 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1775 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1776 * set at open time by rtl_hw_start.
1777 */
1778
1779 if (tp->tc_offset.inited)
1780 return true;
1781
1782 /* If both, reset and update fail, propagate to caller. */
1783 if (rtl8169_reset_counters(tp))
1784 ret = true;
1785
1786 if (rtl8169_update_counters(tp))
1787 ret = true;
1788
1789 tp->tc_offset.tx_errors = counters->tx_errors;
1790 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1791 tp->tc_offset.tx_aborted = counters->tx_aborted;
1792 tp->tc_offset.inited = true;
1793
1794 return ret;
1795}
1796
1797static void rtl8169_get_ethtool_stats(struct net_device *dev,
1798 struct ethtool_stats *stats, u64 *data)
1799{
1800 struct rtl8169_private *tp = netdev_priv(dev);
1801 struct device *d = tp_to_dev(tp);
1802 struct rtl8169_counters *counters = tp->counters;
1803
1804 ASSERT_RTNL();
1805
1806 pm_runtime_get_noresume(d);
1807
1808 if (pm_runtime_active(d))
1809 rtl8169_update_counters(tp);
1810
1811 pm_runtime_put_noidle(d);
1812
1813 data[0] = le64_to_cpu(counters->tx_packets);
1814 data[1] = le64_to_cpu(counters->rx_packets);
1815 data[2] = le64_to_cpu(counters->tx_errors);
1816 data[3] = le32_to_cpu(counters->rx_errors);
1817 data[4] = le16_to_cpu(counters->rx_missed);
1818 data[5] = le16_to_cpu(counters->align_errors);
1819 data[6] = le32_to_cpu(counters->tx_one_collision);
1820 data[7] = le32_to_cpu(counters->tx_multi_collision);
1821 data[8] = le64_to_cpu(counters->rx_unicast);
1822 data[9] = le64_to_cpu(counters->rx_broadcast);
1823 data[10] = le32_to_cpu(counters->rx_multicast);
1824 data[11] = le16_to_cpu(counters->tx_aborted);
1825 data[12] = le16_to_cpu(counters->tx_underrun);
1826}
1827
1828static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1829{
1830 switch(stringset) {
1831 case ETH_SS_STATS:
1832 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1833 break;
1834 }
1835}
1836
1837/*
1838 * Interrupt coalescing
1839 *
1840 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1841 * > 8169, 8168 and 810x line of chipsets
1842 *
1843 * 8169, 8168, and 8136(810x) serial chipsets support it.
1844 *
1845 * > 2 - the Tx timer unit at gigabit speed
1846 *
1847 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1848 * (0xe0) bit 1 and bit 0.
1849 *
1850 * For 8169
1851 * bit[1:0] \ speed 1000M 100M 10M
1852 * 0 0 320ns 2.56us 40.96us
1853 * 0 1 2.56us 20.48us 327.7us
1854 * 1 0 5.12us 40.96us 655.4us
1855 * 1 1 10.24us 81.92us 1.31ms
1856 *
1857 * For the other
1858 * bit[1:0] \ speed 1000M 100M 10M
1859 * 0 0 5us 2.56us 40.96us
1860 * 0 1 40us 20.48us 327.7us
1861 * 1 0 80us 40.96us 655.4us
1862 * 1 1 160us 81.92us 1.31ms
1863 */
1864
1865/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1866struct rtl_coalesce_scale {
1867 /* Rx / Tx */
1868 u32 nsecs[2];
1869};
1870
1871/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1872struct rtl_coalesce_info {
1873 u32 speed;
1874 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1875};
1876
1877/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1878#define rxtx_x1822(r, t) { \
1879 {{(r), (t)}}, \
1880 {{(r)*8, (t)*8}}, \
1881 {{(r)*8*2, (t)*8*2}}, \
1882 {{(r)*8*2*2, (t)*8*2*2}}, \
1883}
1884static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1885 /* speed delays: rx00 tx00 */
1886 { SPEED_10, rxtx_x1822(40960, 40960) },
1887 { SPEED_100, rxtx_x1822( 2560, 2560) },
1888 { SPEED_1000, rxtx_x1822( 320, 320) },
1889 { 0 },
1890};
1891
1892static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1893 /* speed delays: rx00 tx00 */
1894 { SPEED_10, rxtx_x1822(40960, 40960) },
1895 { SPEED_100, rxtx_x1822( 2560, 2560) },
1896 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1897 { 0 },
1898};
1899#undef rxtx_x1822
1900
1901/* get rx/tx scale vector corresponding to current speed */
1902static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1903{
1904 struct rtl8169_private *tp = netdev_priv(dev);
1905 const struct rtl_coalesce_info *ci;
1906
1907 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1908 ci = rtl_coalesce_info_8169;
1909 else
1910 ci = rtl_coalesce_info_8168_8136;
1911
1912 for (; ci->speed; ci++) {
1913 if (tp->phydev->speed == ci->speed)
1914 return ci;
1915 }
1916
1917 return ERR_PTR(-ELNRNG);
1918}
1919
1920static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1921{
1922 struct rtl8169_private *tp = netdev_priv(dev);
1923 const struct rtl_coalesce_info *ci;
1924 const struct rtl_coalesce_scale *scale;
1925 struct {
1926 u32 *max_frames;
1927 u32 *usecs;
1928 } coal_settings [] = {
1929 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1930 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1931 }, *p = coal_settings;
1932 int i;
1933 u16 w;
1934
1935 if (rtl_is_8125(tp))
1936 return -EOPNOTSUPP;
1937
1938 memset(ec, 0, sizeof(*ec));
1939
1940 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1941 ci = rtl_coalesce_info(dev);
1942 if (IS_ERR(ci))
1943 return PTR_ERR(ci);
1944
1945 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1946
1947 /* read IntrMitigate and adjust according to scale */
1948 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1949 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1950 w >>= RTL_COALESCE_SHIFT;
1951 *p->usecs = w & RTL_COALESCE_MASK;
1952 }
1953
1954 for (i = 0; i < 2; i++) {
1955 p = coal_settings + i;
1956 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1957
1958 /*
1959 * ethtool_coalesce says it is illegal to set both usecs and
1960 * max_frames to 0.
1961 */
1962 if (!*p->usecs && !*p->max_frames)
1963 *p->max_frames = 1;
1964 }
1965
1966 return 0;
1967}
1968
1969/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1970static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1971 struct net_device *dev, u32 nsec, u16 *cp01)
1972{
1973 const struct rtl_coalesce_info *ci;
1974 u16 i;
1975
1976 ci = rtl_coalesce_info(dev);
1977 if (IS_ERR(ci))
1978 return ERR_CAST(ci);
1979
1980 for (i = 0; i < 4; i++) {
1981 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1982 ci->scalev[i].nsecs[1]);
1983 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1984 *cp01 = i;
1985 return &ci->scalev[i];
1986 }
1987 }
1988
1989 return ERR_PTR(-EINVAL);
1990}
1991
1992static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995 const struct rtl_coalesce_scale *scale;
1996 struct {
1997 u32 frames;
1998 u32 usecs;
1999 } coal_settings [] = {
2000 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2001 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2002 }, *p = coal_settings;
2003 u16 w = 0, cp01;
2004 int i;
2005
2006 if (rtl_is_8125(tp))
2007 return -EOPNOTSUPP;
2008
2009 scale = rtl_coalesce_choose_scale(dev,
2010 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2011 if (IS_ERR(scale))
2012 return PTR_ERR(scale);
2013
2014 for (i = 0; i < 2; i++, p++) {
2015 u32 units;
2016
2017 /*
2018 * accept max_frames=1 we returned in rtl_get_coalesce.
2019 * accept it not only when usecs=0 because of e.g. the following scenario:
2020 *
2021 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2022 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2023 * - then user does `ethtool -C eth0 rx-usecs 100`
2024 *
2025 * since ethtool sends to kernel whole ethtool_coalesce
2026 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2027 * we'll reject it below in `frames % 4 != 0`.
2028 */
2029 if (p->frames == 1) {
2030 p->frames = 0;
2031 }
2032
2033 units = p->usecs * 1000 / scale->nsecs[i];
2034 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2035 return -EINVAL;
2036
2037 w <<= RTL_COALESCE_SHIFT;
2038 w |= units;
2039 w <<= RTL_COALESCE_SHIFT;
2040 w |= p->frames >> 2;
2041 }
2042
2043 rtl_lock_work(tp);
2044
2045 RTL_W16(tp, IntrMitigate, swab16(w));
2046
2047 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2048 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2049 RTL_R16(tp, CPlusCmd);
2050
2051 rtl_unlock_work(tp);
2052
2053 return 0;
2054}
2055
2056static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2057{
2058 struct rtl8169_private *tp = netdev_priv(dev);
2059 struct device *d = tp_to_dev(tp);
2060 int ret;
2061
2062 if (!rtl_supports_eee(tp))
2063 return -EOPNOTSUPP;
2064
2065 pm_runtime_get_noresume(d);
2066
2067 if (!pm_runtime_active(d)) {
2068 ret = -EOPNOTSUPP;
2069 } else {
2070 ret = phy_ethtool_get_eee(tp->phydev, data);
2071 }
2072
2073 pm_runtime_put_noidle(d);
2074
2075 return ret;
2076}
2077
2078static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2079{
2080 struct rtl8169_private *tp = netdev_priv(dev);
2081 struct device *d = tp_to_dev(tp);
2082 int ret;
2083
2084 if (!rtl_supports_eee(tp))
2085 return -EOPNOTSUPP;
2086
2087 pm_runtime_get_noresume(d);
2088
2089 if (!pm_runtime_active(d)) {
2090 ret = -EOPNOTSUPP;
2091 goto out;
2092 }
2093
2094 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2095 dev->phydev->duplex != DUPLEX_FULL) {
2096 ret = -EPROTONOSUPPORT;
2097 goto out;
2098 }
2099
2100 ret = phy_ethtool_set_eee(tp->phydev, data);
2101
2102 if (!ret)
2103 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2104 MDIO_AN_EEE_ADV);
2105out:
2106 pm_runtime_put_noidle(d);
2107 return ret;
2108}
2109
2110static const struct ethtool_ops rtl8169_ethtool_ops = {
2111 .get_drvinfo = rtl8169_get_drvinfo,
2112 .get_regs_len = rtl8169_get_regs_len,
2113 .get_link = ethtool_op_get_link,
2114 .get_coalesce = rtl_get_coalesce,
2115 .set_coalesce = rtl_set_coalesce,
2116 .get_msglevel = rtl8169_get_msglevel,
2117 .set_msglevel = rtl8169_set_msglevel,
2118 .get_regs = rtl8169_get_regs,
2119 .get_wol = rtl8169_get_wol,
2120 .set_wol = rtl8169_set_wol,
2121 .get_strings = rtl8169_get_strings,
2122 .get_sset_count = rtl8169_get_sset_count,
2123 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2124 .get_ts_info = ethtool_op_get_ts_info,
2125 .nway_reset = phy_ethtool_nway_reset,
2126 .get_eee = rtl8169_get_eee,
2127 .set_eee = rtl8169_set_eee,
2128 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2129 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2130};
2131
2132static void rtl_enable_eee(struct rtl8169_private *tp)
2133{
2134 struct phy_device *phydev = tp->phydev;
2135 int adv;
2136
2137 /* respect EEE advertisement the user may have set */
2138 if (tp->eee_adv >= 0)
2139 adv = tp->eee_adv;
2140 else
2141 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2142
2143 if (adv >= 0)
2144 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2145}
2146
2147static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2148{
2149 /*
2150 * The driver currently handles the 8168Bf and the 8168Be identically
2151 * but they can be identified more specifically through the test below
2152 * if needed:
2153 *
2154 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2155 *
2156 * Same thing for the 8101Eb and the 8101Ec:
2157 *
2158 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2159 */
2160 static const struct rtl_mac_info {
2161 u16 mask;
2162 u16 val;
2163 u16 mac_version;
2164 } mac_info[] = {
2165 /* 8125 family. */
2166 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2167 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2168
2169 /* 8168EP family. */
2170 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2171 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2172 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2173
2174 /* 8168H family. */
2175 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2176 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2177
2178 /* 8168G family. */
2179 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2180 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2181 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2182 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2183
2184 /* 8168F family. */
2185 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2186 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2187 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2188
2189 /* 8168E family. */
2190 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2191 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2192 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2193
2194 /* 8168D family. */
2195 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2196 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2197
2198 /* 8168DP family. */
2199 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2200 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2201 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2202
2203 /* 8168C family. */
2204 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2205 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2206 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2207 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2208 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2209 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2210 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2211
2212 /* 8168B family. */
2213 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2214 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2215 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2216
2217 /* 8101 family. */
2218 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2219 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2220 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2221 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2222 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2223 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2224 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2225 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2226 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2227 /* RTL8401, reportedly works if treated as RTL8101e */
2228 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 },
2229 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2230 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2231 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2232 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2233 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2234 /* FIXME: where did these entries come from ? -- FR */
2235 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2236 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2237
2238 /* 8110 family. */
2239 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2240 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2241 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2242 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2243 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2244
2245 /* Catch-all */
2246 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2247 };
2248 const struct rtl_mac_info *p = mac_info;
2249 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2250
2251 while ((reg & p->mask) != p->val)
2252 p++;
2253 tp->mac_version = p->mac_version;
2254
2255 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2256 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2257 } else if (!tp->supports_gmii) {
2258 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2259 tp->mac_version = RTL_GIGA_MAC_VER_43;
2260 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2261 tp->mac_version = RTL_GIGA_MAC_VER_47;
2262 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2263 tp->mac_version = RTL_GIGA_MAC_VER_48;
2264 }
2265}
2266
2267struct phy_reg {
2268 u16 reg;
2269 u16 val;
2270};
2271
2272static void __rtl_writephy_batch(struct rtl8169_private *tp,
2273 const struct phy_reg *regs, int len)
2274{
2275 while (len-- > 0) {
2276 rtl_writephy(tp, regs->reg, regs->val);
2277 regs++;
2278 }
2279}
2280
2281#define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2282
2283static void rtl_release_firmware(struct rtl8169_private *tp)
2284{
2285 if (tp->rtl_fw) {
2286 rtl_fw_release_firmware(tp->rtl_fw);
2287 kfree(tp->rtl_fw);
2288 tp->rtl_fw = NULL;
2289 }
2290}
2291
2292static void rtl_apply_firmware(struct rtl8169_private *tp)
2293{
2294 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2295 if (tp->rtl_fw)
2296 rtl_fw_write_firmware(tp, tp->rtl_fw);
2297}
2298
2299static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2300{
2301 if (rtl_readphy(tp, reg) != val)
2302 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2303 else
2304 rtl_apply_firmware(tp);
2305}
2306
2307static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2308{
2309 /* Adjust EEE LED frequency */
2310 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2311 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2312
2313 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2314}
2315
2316static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2317{
2318 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2319 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2320}
2321
2322static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2323{
2324 struct phy_device *phydev = tp->phydev;
2325
2326 phy_write(phydev, 0x1f, 0x0007);
2327 phy_write(phydev, 0x1e, 0x0020);
2328 phy_set_bits(phydev, 0x15, BIT(8));
2329
2330 phy_write(phydev, 0x1f, 0x0005);
2331 phy_write(phydev, 0x05, 0x8b85);
2332 phy_set_bits(phydev, 0x06, BIT(13));
2333
2334 phy_write(phydev, 0x1f, 0x0000);
2335}
2336
2337static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2338{
2339 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2340}
2341
2342static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2343{
2344 struct phy_device *phydev = tp->phydev;
2345
2346 rtl8168g_config_eee_phy(tp);
2347
2348 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2349 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2350}
2351
2352static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2353{
2354 struct phy_device *phydev = tp->phydev;
2355
2356 rtl8168h_config_eee_phy(tp);
2357
2358 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2359 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2360}
2361
2362static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2363{
2364 static const struct phy_reg phy_reg_init[] = {
2365 { 0x1f, 0x0001 },
2366 { 0x06, 0x006e },
2367 { 0x08, 0x0708 },
2368 { 0x15, 0x4000 },
2369 { 0x18, 0x65c7 },
2370
2371 { 0x1f, 0x0001 },
2372 { 0x03, 0x00a1 },
2373 { 0x02, 0x0008 },
2374 { 0x01, 0x0120 },
2375 { 0x00, 0x1000 },
2376 { 0x04, 0x0800 },
2377 { 0x04, 0x0000 },
2378
2379 { 0x03, 0xff41 },
2380 { 0x02, 0xdf60 },
2381 { 0x01, 0x0140 },
2382 { 0x00, 0x0077 },
2383 { 0x04, 0x7800 },
2384 { 0x04, 0x7000 },
2385
2386 { 0x03, 0x802f },
2387 { 0x02, 0x4f02 },
2388 { 0x01, 0x0409 },
2389 { 0x00, 0xf0f9 },
2390 { 0x04, 0x9800 },
2391 { 0x04, 0x9000 },
2392
2393 { 0x03, 0xdf01 },
2394 { 0x02, 0xdf20 },
2395 { 0x01, 0xff95 },
2396 { 0x00, 0xba00 },
2397 { 0x04, 0xa800 },
2398 { 0x04, 0xa000 },
2399
2400 { 0x03, 0xff41 },
2401 { 0x02, 0xdf20 },
2402 { 0x01, 0x0140 },
2403 { 0x00, 0x00bb },
2404 { 0x04, 0xb800 },
2405 { 0x04, 0xb000 },
2406
2407 { 0x03, 0xdf41 },
2408 { 0x02, 0xdc60 },
2409 { 0x01, 0x6340 },
2410 { 0x00, 0x007d },
2411 { 0x04, 0xd800 },
2412 { 0x04, 0xd000 },
2413
2414 { 0x03, 0xdf01 },
2415 { 0x02, 0xdf20 },
2416 { 0x01, 0x100a },
2417 { 0x00, 0xa0ff },
2418 { 0x04, 0xf800 },
2419 { 0x04, 0xf000 },
2420
2421 { 0x1f, 0x0000 },
2422 { 0x0b, 0x0000 },
2423 { 0x00, 0x9200 }
2424 };
2425
2426 rtl_writephy_batch(tp, phy_reg_init);
2427}
2428
2429static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2430{
2431 static const struct phy_reg phy_reg_init[] = {
2432 { 0x1f, 0x0002 },
2433 { 0x01, 0x90d0 },
2434 { 0x1f, 0x0000 }
2435 };
2436
2437 rtl_writephy_batch(tp, phy_reg_init);
2438}
2439
2440static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2441{
2442 struct pci_dev *pdev = tp->pci_dev;
2443
2444 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2445 (pdev->subsystem_device != 0xe000))
2446 return;
2447
2448 rtl_writephy(tp, 0x1f, 0x0001);
2449 rtl_writephy(tp, 0x10, 0xf01b);
2450 rtl_writephy(tp, 0x1f, 0x0000);
2451}
2452
2453static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2454{
2455 static const struct phy_reg phy_reg_init[] = {
2456 { 0x1f, 0x0001 },
2457 { 0x04, 0x0000 },
2458 { 0x03, 0x00a1 },
2459 { 0x02, 0x0008 },
2460 { 0x01, 0x0120 },
2461 { 0x00, 0x1000 },
2462 { 0x04, 0x0800 },
2463 { 0x04, 0x9000 },
2464 { 0x03, 0x802f },
2465 { 0x02, 0x4f02 },
2466 { 0x01, 0x0409 },
2467 { 0x00, 0xf099 },
2468 { 0x04, 0x9800 },
2469 { 0x04, 0xa000 },
2470 { 0x03, 0xdf01 },
2471 { 0x02, 0xdf20 },
2472 { 0x01, 0xff95 },
2473 { 0x00, 0xba00 },
2474 { 0x04, 0xa800 },
2475 { 0x04, 0xf000 },
2476 { 0x03, 0xdf01 },
2477 { 0x02, 0xdf20 },
2478 { 0x01, 0x101a },
2479 { 0x00, 0xa0ff },
2480 { 0x04, 0xf800 },
2481 { 0x04, 0x0000 },
2482 { 0x1f, 0x0000 },
2483
2484 { 0x1f, 0x0001 },
2485 { 0x10, 0xf41b },
2486 { 0x14, 0xfb54 },
2487 { 0x18, 0xf5c7 },
2488 { 0x1f, 0x0000 },
2489
2490 { 0x1f, 0x0001 },
2491 { 0x17, 0x0cc0 },
2492 { 0x1f, 0x0000 }
2493 };
2494
2495 rtl_writephy_batch(tp, phy_reg_init);
2496
2497 rtl8169scd_hw_phy_config_quirk(tp);
2498}
2499
2500static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2501{
2502 static const struct phy_reg phy_reg_init[] = {
2503 { 0x1f, 0x0001 },
2504 { 0x04, 0x0000 },
2505 { 0x03, 0x00a1 },
2506 { 0x02, 0x0008 },
2507 { 0x01, 0x0120 },
2508 { 0x00, 0x1000 },
2509 { 0x04, 0x0800 },
2510 { 0x04, 0x9000 },
2511 { 0x03, 0x802f },
2512 { 0x02, 0x4f02 },
2513 { 0x01, 0x0409 },
2514 { 0x00, 0xf099 },
2515 { 0x04, 0x9800 },
2516 { 0x04, 0xa000 },
2517 { 0x03, 0xdf01 },
2518 { 0x02, 0xdf20 },
2519 { 0x01, 0xff95 },
2520 { 0x00, 0xba00 },
2521 { 0x04, 0xa800 },
2522 { 0x04, 0xf000 },
2523 { 0x03, 0xdf01 },
2524 { 0x02, 0xdf20 },
2525 { 0x01, 0x101a },
2526 { 0x00, 0xa0ff },
2527 { 0x04, 0xf800 },
2528 { 0x04, 0x0000 },
2529 { 0x1f, 0x0000 },
2530
2531 { 0x1f, 0x0001 },
2532 { 0x0b, 0x8480 },
2533 { 0x1f, 0x0000 },
2534
2535 { 0x1f, 0x0001 },
2536 { 0x18, 0x67c7 },
2537 { 0x04, 0x2000 },
2538 { 0x03, 0x002f },
2539 { 0x02, 0x4360 },
2540 { 0x01, 0x0109 },
2541 { 0x00, 0x3022 },
2542 { 0x04, 0x2800 },
2543 { 0x1f, 0x0000 },
2544
2545 { 0x1f, 0x0001 },
2546 { 0x17, 0x0cc0 },
2547 { 0x1f, 0x0000 }
2548 };
2549
2550 rtl_writephy_batch(tp, phy_reg_init);
2551}
2552
2553static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2554{
2555 static const struct phy_reg phy_reg_init[] = {
2556 { 0x10, 0xf41b },
2557 { 0x1f, 0x0000 }
2558 };
2559
2560 rtl_writephy(tp, 0x1f, 0x0001);
2561 rtl_patchphy(tp, 0x16, 1 << 0);
2562
2563 rtl_writephy_batch(tp, phy_reg_init);
2564}
2565
2566static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2567{
2568 static const struct phy_reg phy_reg_init[] = {
2569 { 0x1f, 0x0001 },
2570 { 0x10, 0xf41b },
2571 { 0x1f, 0x0000 }
2572 };
2573
2574 rtl_writephy_batch(tp, phy_reg_init);
2575}
2576
2577static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2578{
2579 static const struct phy_reg phy_reg_init[] = {
2580 { 0x1f, 0x0000 },
2581 { 0x1d, 0x0f00 },
2582 { 0x1f, 0x0002 },
2583 { 0x0c, 0x1ec8 },
2584 { 0x1f, 0x0000 }
2585 };
2586
2587 rtl_writephy_batch(tp, phy_reg_init);
2588}
2589
2590static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2591{
2592 static const struct phy_reg phy_reg_init[] = {
2593 { 0x1f, 0x0001 },
2594 { 0x1d, 0x3d98 },
2595 { 0x1f, 0x0000 }
2596 };
2597
2598 rtl_writephy(tp, 0x1f, 0x0000);
2599 rtl_patchphy(tp, 0x14, 1 << 5);
2600 rtl_patchphy(tp, 0x0d, 1 << 5);
2601
2602 rtl_writephy_batch(tp, phy_reg_init);
2603}
2604
2605static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2606{
2607 static const struct phy_reg phy_reg_init[] = {
2608 { 0x1f, 0x0001 },
2609 { 0x12, 0x2300 },
2610 { 0x1f, 0x0002 },
2611 { 0x00, 0x88d4 },
2612 { 0x01, 0x82b1 },
2613 { 0x03, 0x7002 },
2614 { 0x08, 0x9e30 },
2615 { 0x09, 0x01f0 },
2616 { 0x0a, 0x5500 },
2617 { 0x0c, 0x00c8 },
2618 { 0x1f, 0x0003 },
2619 { 0x12, 0xc096 },
2620 { 0x16, 0x000a },
2621 { 0x1f, 0x0000 },
2622 { 0x1f, 0x0000 },
2623 { 0x09, 0x2000 },
2624 { 0x09, 0x0000 }
2625 };
2626
2627 rtl_writephy_batch(tp, phy_reg_init);
2628
2629 rtl_patchphy(tp, 0x14, 1 << 5);
2630 rtl_patchphy(tp, 0x0d, 1 << 5);
2631 rtl_writephy(tp, 0x1f, 0x0000);
2632}
2633
2634static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2635{
2636 static const struct phy_reg phy_reg_init[] = {
2637 { 0x1f, 0x0001 },
2638 { 0x12, 0x2300 },
2639 { 0x03, 0x802f },
2640 { 0x02, 0x4f02 },
2641 { 0x01, 0x0409 },
2642 { 0x00, 0xf099 },
2643 { 0x04, 0x9800 },
2644 { 0x04, 0x9000 },
2645 { 0x1d, 0x3d98 },
2646 { 0x1f, 0x0002 },
2647 { 0x0c, 0x7eb8 },
2648 { 0x06, 0x0761 },
2649 { 0x1f, 0x0003 },
2650 { 0x16, 0x0f0a },
2651 { 0x1f, 0x0000 }
2652 };
2653
2654 rtl_writephy_batch(tp, phy_reg_init);
2655
2656 rtl_patchphy(tp, 0x16, 1 << 0);
2657 rtl_patchphy(tp, 0x14, 1 << 5);
2658 rtl_patchphy(tp, 0x0d, 1 << 5);
2659 rtl_writephy(tp, 0x1f, 0x0000);
2660}
2661
2662static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2663{
2664 static const struct phy_reg phy_reg_init[] = {
2665 { 0x1f, 0x0001 },
2666 { 0x12, 0x2300 },
2667 { 0x1d, 0x3d98 },
2668 { 0x1f, 0x0002 },
2669 { 0x0c, 0x7eb8 },
2670 { 0x06, 0x5461 },
2671 { 0x1f, 0x0003 },
2672 { 0x16, 0x0f0a },
2673 { 0x1f, 0x0000 }
2674 };
2675
2676 rtl_writephy_batch(tp, phy_reg_init);
2677
2678 rtl_patchphy(tp, 0x16, 1 << 0);
2679 rtl_patchphy(tp, 0x14, 1 << 5);
2680 rtl_patchphy(tp, 0x0d, 1 << 5);
2681 rtl_writephy(tp, 0x1f, 0x0000);
2682}
2683
2684static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2685{
2686 rtl8168c_3_hw_phy_config(tp);
2687}
2688
2689static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2690 /* Channel Estimation */
2691 { 0x1f, 0x0001 },
2692 { 0x06, 0x4064 },
2693 { 0x07, 0x2863 },
2694 { 0x08, 0x059c },
2695 { 0x09, 0x26b4 },
2696 { 0x0a, 0x6a19 },
2697 { 0x0b, 0xdcc8 },
2698 { 0x10, 0xf06d },
2699 { 0x14, 0x7f68 },
2700 { 0x18, 0x7fd9 },
2701 { 0x1c, 0xf0ff },
2702 { 0x1d, 0x3d9c },
2703 { 0x1f, 0x0003 },
2704 { 0x12, 0xf49f },
2705 { 0x13, 0x070b },
2706 { 0x1a, 0x05ad },
2707 { 0x14, 0x94c0 },
2708
2709 /*
2710 * Tx Error Issue
2711 * Enhance line driver power
2712 */
2713 { 0x1f, 0x0002 },
2714 { 0x06, 0x5561 },
2715 { 0x1f, 0x0005 },
2716 { 0x05, 0x8332 },
2717 { 0x06, 0x5561 },
2718
2719 /*
2720 * Can not link to 1Gbps with bad cable
2721 * Decrease SNR threshold form 21.07dB to 19.04dB
2722 */
2723 { 0x1f, 0x0001 },
2724 { 0x17, 0x0cc0 },
2725
2726 { 0x1f, 0x0000 },
2727 { 0x0d, 0xf880 }
2728};
2729
2730static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2731 { 0x1f, 0x0002 },
2732 { 0x05, 0x669a },
2733 { 0x1f, 0x0005 },
2734 { 0x05, 0x8330 },
2735 { 0x06, 0x669a },
2736 { 0x1f, 0x0002 }
2737};
2738
2739static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2740{
2741 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2742
2743 /*
2744 * Rx Error Issue
2745 * Fine Tune Switching regulator parameter
2746 */
2747 rtl_writephy(tp, 0x1f, 0x0002);
2748 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2749 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2750
2751 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2752 int val;
2753
2754 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2755
2756 val = rtl_readphy(tp, 0x0d);
2757
2758 if ((val & 0x00ff) != 0x006c) {
2759 static const u32 set[] = {
2760 0x0065, 0x0066, 0x0067, 0x0068,
2761 0x0069, 0x006a, 0x006b, 0x006c
2762 };
2763 int i;
2764
2765 rtl_writephy(tp, 0x1f, 0x0002);
2766
2767 val &= 0xff00;
2768 for (i = 0; i < ARRAY_SIZE(set); i++)
2769 rtl_writephy(tp, 0x0d, val | set[i]);
2770 }
2771 } else {
2772 static const struct phy_reg phy_reg_init[] = {
2773 { 0x1f, 0x0002 },
2774 { 0x05, 0x6662 },
2775 { 0x1f, 0x0005 },
2776 { 0x05, 0x8330 },
2777 { 0x06, 0x6662 }
2778 };
2779
2780 rtl_writephy_batch(tp, phy_reg_init);
2781 }
2782
2783 /* RSET couple improve */
2784 rtl_writephy(tp, 0x1f, 0x0002);
2785 rtl_patchphy(tp, 0x0d, 0x0300);
2786 rtl_patchphy(tp, 0x0f, 0x0010);
2787
2788 /* Fine tune PLL performance */
2789 rtl_writephy(tp, 0x1f, 0x0002);
2790 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2791 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2792
2793 rtl_writephy(tp, 0x1f, 0x0005);
2794 rtl_writephy(tp, 0x05, 0x001b);
2795
2796 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2797
2798 rtl_writephy(tp, 0x1f, 0x0000);
2799}
2800
2801static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2802{
2803 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2804
2805 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2806 int val;
2807
2808 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2809
2810 val = rtl_readphy(tp, 0x0d);
2811 if ((val & 0x00ff) != 0x006c) {
2812 static const u32 set[] = {
2813 0x0065, 0x0066, 0x0067, 0x0068,
2814 0x0069, 0x006a, 0x006b, 0x006c
2815 };
2816 int i;
2817
2818 rtl_writephy(tp, 0x1f, 0x0002);
2819
2820 val &= 0xff00;
2821 for (i = 0; i < ARRAY_SIZE(set); i++)
2822 rtl_writephy(tp, 0x0d, val | set[i]);
2823 }
2824 } else {
2825 static const struct phy_reg phy_reg_init[] = {
2826 { 0x1f, 0x0002 },
2827 { 0x05, 0x2642 },
2828 { 0x1f, 0x0005 },
2829 { 0x05, 0x8330 },
2830 { 0x06, 0x2642 }
2831 };
2832
2833 rtl_writephy_batch(tp, phy_reg_init);
2834 }
2835
2836 /* Fine tune PLL performance */
2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2839 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2840
2841 /* Switching regulator Slew rate */
2842 rtl_writephy(tp, 0x1f, 0x0002);
2843 rtl_patchphy(tp, 0x0f, 0x0017);
2844
2845 rtl_writephy(tp, 0x1f, 0x0005);
2846 rtl_writephy(tp, 0x05, 0x001b);
2847
2848 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2849
2850 rtl_writephy(tp, 0x1f, 0x0000);
2851}
2852
2853static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2854{
2855 static const struct phy_reg phy_reg_init[] = {
2856 { 0x1f, 0x0002 },
2857 { 0x10, 0x0008 },
2858 { 0x0d, 0x006c },
2859
2860 { 0x1f, 0x0000 },
2861 { 0x0d, 0xf880 },
2862
2863 { 0x1f, 0x0001 },
2864 { 0x17, 0x0cc0 },
2865
2866 { 0x1f, 0x0001 },
2867 { 0x0b, 0xa4d8 },
2868 { 0x09, 0x281c },
2869 { 0x07, 0x2883 },
2870 { 0x0a, 0x6b35 },
2871 { 0x1d, 0x3da4 },
2872 { 0x1c, 0xeffd },
2873 { 0x14, 0x7f52 },
2874 { 0x18, 0x7fc6 },
2875 { 0x08, 0x0601 },
2876 { 0x06, 0x4063 },
2877 { 0x10, 0xf074 },
2878 { 0x1f, 0x0003 },
2879 { 0x13, 0x0789 },
2880 { 0x12, 0xf4bd },
2881 { 0x1a, 0x04fd },
2882 { 0x14, 0x84b0 },
2883 { 0x1f, 0x0000 },
2884 { 0x00, 0x9200 },
2885
2886 { 0x1f, 0x0005 },
2887 { 0x01, 0x0340 },
2888 { 0x1f, 0x0001 },
2889 { 0x04, 0x4000 },
2890 { 0x03, 0x1d21 },
2891 { 0x02, 0x0c32 },
2892 { 0x01, 0x0200 },
2893 { 0x00, 0x5554 },
2894 { 0x04, 0x4800 },
2895 { 0x04, 0x4000 },
2896 { 0x04, 0xf000 },
2897 { 0x03, 0xdf01 },
2898 { 0x02, 0xdf20 },
2899 { 0x01, 0x101a },
2900 { 0x00, 0xa0ff },
2901 { 0x04, 0xf800 },
2902 { 0x04, 0xf000 },
2903 { 0x1f, 0x0000 },
2904
2905 { 0x1f, 0x0007 },
2906 { 0x1e, 0x0023 },
2907 { 0x16, 0x0000 },
2908 { 0x1f, 0x0000 }
2909 };
2910
2911 rtl_writephy_batch(tp, phy_reg_init);
2912}
2913
2914static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2915{
2916 static const struct phy_reg phy_reg_init[] = {
2917 { 0x1f, 0x0001 },
2918 { 0x17, 0x0cc0 },
2919
2920 { 0x1f, 0x0007 },
2921 { 0x1e, 0x002d },
2922 { 0x18, 0x0040 },
2923 { 0x1f, 0x0000 }
2924 };
2925
2926 rtl_writephy_batch(tp, phy_reg_init);
2927 rtl_patchphy(tp, 0x0d, 1 << 5);
2928}
2929
2930static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2931{
2932 static const struct phy_reg phy_reg_init[] = {
2933 /* Enable Delay cap */
2934 { 0x1f, 0x0005 },
2935 { 0x05, 0x8b80 },
2936 { 0x06, 0xc896 },
2937 { 0x1f, 0x0000 },
2938
2939 /* Channel estimation fine tune */
2940 { 0x1f, 0x0001 },
2941 { 0x0b, 0x6c20 },
2942 { 0x07, 0x2872 },
2943 { 0x1c, 0xefff },
2944 { 0x1f, 0x0003 },
2945 { 0x14, 0x6420 },
2946 { 0x1f, 0x0000 },
2947
2948 /* Update PFM & 10M TX idle timer */
2949 { 0x1f, 0x0007 },
2950 { 0x1e, 0x002f },
2951 { 0x15, 0x1919 },
2952 { 0x1f, 0x0000 },
2953
2954 { 0x1f, 0x0007 },
2955 { 0x1e, 0x00ac },
2956 { 0x18, 0x0006 },
2957 { 0x1f, 0x0000 }
2958 };
2959
2960 rtl_apply_firmware(tp);
2961
2962 rtl_writephy_batch(tp, phy_reg_init);
2963
2964 /* DCO enable for 10M IDLE Power */
2965 rtl_writephy(tp, 0x1f, 0x0007);
2966 rtl_writephy(tp, 0x1e, 0x0023);
2967 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2968 rtl_writephy(tp, 0x1f, 0x0000);
2969
2970 /* For impedance matching */
2971 rtl_writephy(tp, 0x1f, 0x0002);
2972 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2973 rtl_writephy(tp, 0x1f, 0x0000);
2974
2975 /* PHY auto speed down */
2976 rtl_writephy(tp, 0x1f, 0x0007);
2977 rtl_writephy(tp, 0x1e, 0x002d);
2978 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2979 rtl_writephy(tp, 0x1f, 0x0000);
2980 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2981
2982 rtl_writephy(tp, 0x1f, 0x0005);
2983 rtl_writephy(tp, 0x05, 0x8b86);
2984 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2985 rtl_writephy(tp, 0x1f, 0x0000);
2986
2987 rtl_writephy(tp, 0x1f, 0x0005);
2988 rtl_writephy(tp, 0x05, 0x8b85);
2989 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2990 rtl_writephy(tp, 0x1f, 0x0007);
2991 rtl_writephy(tp, 0x1e, 0x0020);
2992 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2993 rtl_writephy(tp, 0x1f, 0x0006);
2994 rtl_writephy(tp, 0x00, 0x5a00);
2995 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_writephy(tp, 0x0d, 0x0007);
2997 rtl_writephy(tp, 0x0e, 0x003c);
2998 rtl_writephy(tp, 0x0d, 0x4007);
2999 rtl_writephy(tp, 0x0e, 0x0000);
3000 rtl_writephy(tp, 0x0d, 0x0000);
3001}
3002
3003static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3004{
3005 const u16 w[] = {
3006 addr[0] | (addr[1] << 8),
3007 addr[2] | (addr[3] << 8),
3008 addr[4] | (addr[5] << 8)
3009 };
3010
3011 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3012 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3013 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3014 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3015}
3016
3017static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3018{
3019 static const struct phy_reg phy_reg_init[] = {
3020 /* Enable Delay cap */
3021 { 0x1f, 0x0004 },
3022 { 0x1f, 0x0007 },
3023 { 0x1e, 0x00ac },
3024 { 0x18, 0x0006 },
3025 { 0x1f, 0x0002 },
3026 { 0x1f, 0x0000 },
3027 { 0x1f, 0x0000 },
3028
3029 /* Channel estimation fine tune */
3030 { 0x1f, 0x0003 },
3031 { 0x09, 0xa20f },
3032 { 0x1f, 0x0000 },
3033 { 0x1f, 0x0000 },
3034
3035 /* Green Setting */
3036 { 0x1f, 0x0005 },
3037 { 0x05, 0x8b5b },
3038 { 0x06, 0x9222 },
3039 { 0x05, 0x8b6d },
3040 { 0x06, 0x8000 },
3041 { 0x05, 0x8b76 },
3042 { 0x06, 0x8000 },
3043 { 0x1f, 0x0000 }
3044 };
3045
3046 rtl_apply_firmware(tp);
3047
3048 rtl_writephy_batch(tp, phy_reg_init);
3049
3050 /* For 4-corner performance improve */
3051 rtl_writephy(tp, 0x1f, 0x0005);
3052 rtl_writephy(tp, 0x05, 0x8b80);
3053 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3054 rtl_writephy(tp, 0x1f, 0x0000);
3055
3056 /* PHY auto speed down */
3057 rtl_writephy(tp, 0x1f, 0x0004);
3058 rtl_writephy(tp, 0x1f, 0x0007);
3059 rtl_writephy(tp, 0x1e, 0x002d);
3060 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3061 rtl_writephy(tp, 0x1f, 0x0002);
3062 rtl_writephy(tp, 0x1f, 0x0000);
3063 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3064
3065 /* improve 10M EEE waveform */
3066 rtl_writephy(tp, 0x1f, 0x0005);
3067 rtl_writephy(tp, 0x05, 0x8b86);
3068 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3070
3071 /* Improve 2-pair detection performance */
3072 rtl_writephy(tp, 0x1f, 0x0005);
3073 rtl_writephy(tp, 0x05, 0x8b85);
3074 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3075 rtl_writephy(tp, 0x1f, 0x0000);
3076
3077 rtl8168f_config_eee_phy(tp);
3078 rtl_enable_eee(tp);
3079
3080 /* Green feature */
3081 rtl_writephy(tp, 0x1f, 0x0003);
3082 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3083 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3084 rtl_writephy(tp, 0x1f, 0x0000);
3085 rtl_writephy(tp, 0x1f, 0x0005);
3086 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3087 rtl_writephy(tp, 0x1f, 0x0000);
3088
3089 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3090 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3091}
3092
3093static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3094{
3095 /* For 4-corner performance improve */
3096 rtl_writephy(tp, 0x1f, 0x0005);
3097 rtl_writephy(tp, 0x05, 0x8b80);
3098 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100
3101 /* PHY auto speed down */
3102 rtl_writephy(tp, 0x1f, 0x0007);
3103 rtl_writephy(tp, 0x1e, 0x002d);
3104 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3107
3108 /* Improve 10M EEE waveform */
3109 rtl_writephy(tp, 0x1f, 0x0005);
3110 rtl_writephy(tp, 0x05, 0x8b86);
3111 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3112 rtl_writephy(tp, 0x1f, 0x0000);
3113
3114 rtl8168f_config_eee_phy(tp);
3115 rtl_enable_eee(tp);
3116}
3117
3118static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3119{
3120 static const struct phy_reg phy_reg_init[] = {
3121 /* Channel estimation fine tune */
3122 { 0x1f, 0x0003 },
3123 { 0x09, 0xa20f },
3124 { 0x1f, 0x0000 },
3125
3126 /* Modify green table for giga & fnet */
3127 { 0x1f, 0x0005 },
3128 { 0x05, 0x8b55 },
3129 { 0x06, 0x0000 },
3130 { 0x05, 0x8b5e },
3131 { 0x06, 0x0000 },
3132 { 0x05, 0x8b67 },
3133 { 0x06, 0x0000 },
3134 { 0x05, 0x8b70 },
3135 { 0x06, 0x0000 },
3136 { 0x1f, 0x0000 },
3137 { 0x1f, 0x0007 },
3138 { 0x1e, 0x0078 },
3139 { 0x17, 0x0000 },
3140 { 0x19, 0x00fb },
3141 { 0x1f, 0x0000 },
3142
3143 /* Modify green table for 10M */
3144 { 0x1f, 0x0005 },
3145 { 0x05, 0x8b79 },
3146 { 0x06, 0xaa00 },
3147 { 0x1f, 0x0000 },
3148
3149 /* Disable hiimpedance detection (RTCT) */
3150 { 0x1f, 0x0003 },
3151 { 0x01, 0x328a },
3152 { 0x1f, 0x0000 }
3153 };
3154
3155 rtl_apply_firmware(tp);
3156
3157 rtl_writephy_batch(tp, phy_reg_init);
3158
3159 rtl8168f_hw_phy_config(tp);
3160
3161 /* Improve 2-pair detection performance */
3162 rtl_writephy(tp, 0x1f, 0x0005);
3163 rtl_writephy(tp, 0x05, 0x8b85);
3164 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3165 rtl_writephy(tp, 0x1f, 0x0000);
3166}
3167
3168static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3169{
3170 rtl_apply_firmware(tp);
3171
3172 rtl8168f_hw_phy_config(tp);
3173}
3174
3175static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3176{
3177 static const struct phy_reg phy_reg_init[] = {
3178 /* Channel estimation fine tune */
3179 { 0x1f, 0x0003 },
3180 { 0x09, 0xa20f },
3181 { 0x1f, 0x0000 },
3182
3183 /* Modify green table for giga & fnet */
3184 { 0x1f, 0x0005 },
3185 { 0x05, 0x8b55 },
3186 { 0x06, 0x0000 },
3187 { 0x05, 0x8b5e },
3188 { 0x06, 0x0000 },
3189 { 0x05, 0x8b67 },
3190 { 0x06, 0x0000 },
3191 { 0x05, 0x8b70 },
3192 { 0x06, 0x0000 },
3193 { 0x1f, 0x0000 },
3194 { 0x1f, 0x0007 },
3195 { 0x1e, 0x0078 },
3196 { 0x17, 0x0000 },
3197 { 0x19, 0x00aa },
3198 { 0x1f, 0x0000 },
3199
3200 /* Modify green table for 10M */
3201 { 0x1f, 0x0005 },
3202 { 0x05, 0x8b79 },
3203 { 0x06, 0xaa00 },
3204 { 0x1f, 0x0000 },
3205
3206 /* Disable hiimpedance detection (RTCT) */
3207 { 0x1f, 0x0003 },
3208 { 0x01, 0x328a },
3209 { 0x1f, 0x0000 }
3210 };
3211
3212
3213 rtl_apply_firmware(tp);
3214
3215 rtl8168f_hw_phy_config(tp);
3216
3217 /* Improve 2-pair detection performance */
3218 rtl_writephy(tp, 0x1f, 0x0005);
3219 rtl_writephy(tp, 0x05, 0x8b85);
3220 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3221 rtl_writephy(tp, 0x1f, 0x0000);
3222
3223 rtl_writephy_batch(tp, phy_reg_init);
3224
3225 /* Modify green table for giga */
3226 rtl_writephy(tp, 0x1f, 0x0005);
3227 rtl_writephy(tp, 0x05, 0x8b54);
3228 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3229 rtl_writephy(tp, 0x05, 0x8b5d);
3230 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3231 rtl_writephy(tp, 0x05, 0x8a7c);
3232 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3233 rtl_writephy(tp, 0x05, 0x8a7f);
3234 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3235 rtl_writephy(tp, 0x05, 0x8a82);
3236 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3237 rtl_writephy(tp, 0x05, 0x8a85);
3238 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3239 rtl_writephy(tp, 0x05, 0x8a88);
3240 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3241 rtl_writephy(tp, 0x1f, 0x0000);
3242
3243 /* uc same-seed solution */
3244 rtl_writephy(tp, 0x1f, 0x0005);
3245 rtl_writephy(tp, 0x05, 0x8b85);
3246 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0000);
3248
3249 /* Green feature */
3250 rtl_writephy(tp, 0x1f, 0x0003);
3251 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3252 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3253 rtl_writephy(tp, 0x1f, 0x0000);
3254}
3255
3256static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3257{
3258 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3259}
3260
3261static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3262{
3263 struct phy_device *phydev = tp->phydev;
3264
3265 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3266 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3267 phy_write(phydev, 0x1f, 0x0a43);
3268 phy_write(phydev, 0x13, 0x8084);
3269 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3270 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3271
3272 phy_write(phydev, 0x1f, 0x0000);
3273}
3274
3275static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3276{
3277 int ret;
3278
3279 rtl_apply_firmware(tp);
3280
3281 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3282 if (ret & BIT(8))
3283 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3284 else
3285 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3286
3287 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3288 if (ret & BIT(8))
3289 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3290 else
3291 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3292
3293 /* Enable PHY auto speed down */
3294 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3295
3296 rtl8168g_phy_adjust_10m_aldps(tp);
3297
3298 /* EEE auto-fallback function */
3299 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3300
3301 /* Enable UC LPF tune function */
3302 rtl_writephy(tp, 0x1f, 0x0a43);
3303 rtl_writephy(tp, 0x13, 0x8012);
3304 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3305
3306 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3307
3308 /* Improve SWR Efficiency */
3309 rtl_writephy(tp, 0x1f, 0x0bcd);
3310 rtl_writephy(tp, 0x14, 0x5065);
3311 rtl_writephy(tp, 0x14, 0xd065);
3312 rtl_writephy(tp, 0x1f, 0x0bc8);
3313 rtl_writephy(tp, 0x11, 0x5655);
3314 rtl_writephy(tp, 0x1f, 0x0bcd);
3315 rtl_writephy(tp, 0x14, 0x1065);
3316 rtl_writephy(tp, 0x14, 0x9065);
3317 rtl_writephy(tp, 0x14, 0x1065);
3318 rtl_writephy(tp, 0x1f, 0x0000);
3319
3320 rtl8168g_disable_aldps(tp);
3321 rtl8168g_config_eee_phy(tp);
3322 rtl_enable_eee(tp);
3323}
3324
3325static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3326{
3327 rtl_apply_firmware(tp);
3328 rtl8168g_config_eee_phy(tp);
3329 rtl_enable_eee(tp);
3330}
3331
3332static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3333{
3334 u16 dout_tapbin;
3335 u32 data;
3336
3337 rtl_apply_firmware(tp);
3338
3339 /* CHN EST parameters adjust - giga master */
3340 rtl_writephy(tp, 0x1f, 0x0a43);
3341 rtl_writephy(tp, 0x13, 0x809b);
3342 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3343 rtl_writephy(tp, 0x13, 0x80a2);
3344 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3345 rtl_writephy(tp, 0x13, 0x80a4);
3346 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3347 rtl_writephy(tp, 0x13, 0x809c);
3348 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3349 rtl_writephy(tp, 0x1f, 0x0000);
3350
3351 /* CHN EST parameters adjust - giga slave */
3352 rtl_writephy(tp, 0x1f, 0x0a43);
3353 rtl_writephy(tp, 0x13, 0x80ad);
3354 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3355 rtl_writephy(tp, 0x13, 0x80b4);
3356 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3357 rtl_writephy(tp, 0x13, 0x80ac);
3358 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360
3361 /* CHN EST parameters adjust - fnet */
3362 rtl_writephy(tp, 0x1f, 0x0a43);
3363 rtl_writephy(tp, 0x13, 0x808e);
3364 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3365 rtl_writephy(tp, 0x13, 0x8090);
3366 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3367 rtl_writephy(tp, 0x13, 0x8092);
3368 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3369 rtl_writephy(tp, 0x1f, 0x0000);
3370
3371 /* enable R-tune & PGA-retune function */
3372 dout_tapbin = 0;
3373 rtl_writephy(tp, 0x1f, 0x0a46);
3374 data = rtl_readphy(tp, 0x13);
3375 data &= 3;
3376 data <<= 2;
3377 dout_tapbin |= data;
3378 data = rtl_readphy(tp, 0x12);
3379 data &= 0xc000;
3380 data >>= 14;
3381 dout_tapbin |= data;
3382 dout_tapbin = ~(dout_tapbin^0x08);
3383 dout_tapbin <<= 12;
3384 dout_tapbin &= 0xf000;
3385 rtl_writephy(tp, 0x1f, 0x0a43);
3386 rtl_writephy(tp, 0x13, 0x827a);
3387 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3388 rtl_writephy(tp, 0x13, 0x827b);
3389 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3390 rtl_writephy(tp, 0x13, 0x827c);
3391 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3392 rtl_writephy(tp, 0x13, 0x827d);
3393 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3394
3395 rtl_writephy(tp, 0x1f, 0x0a43);
3396 rtl_writephy(tp, 0x13, 0x0811);
3397 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3398 rtl_writephy(tp, 0x1f, 0x0a42);
3399 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3400 rtl_writephy(tp, 0x1f, 0x0000);
3401
3402 /* enable GPHY 10M */
3403 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3404
3405 /* SAR ADC performance */
3406 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3407
3408 rtl_writephy(tp, 0x1f, 0x0a43);
3409 rtl_writephy(tp, 0x13, 0x803f);
3410 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3411 rtl_writephy(tp, 0x13, 0x8047);
3412 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3413 rtl_writephy(tp, 0x13, 0x804f);
3414 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3415 rtl_writephy(tp, 0x13, 0x8057);
3416 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3417 rtl_writephy(tp, 0x13, 0x805f);
3418 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3419 rtl_writephy(tp, 0x13, 0x8067);
3420 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3421 rtl_writephy(tp, 0x13, 0x806f);
3422 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3423 rtl_writephy(tp, 0x1f, 0x0000);
3424
3425 /* disable phy pfm mode */
3426 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3427
3428 rtl8168g_disable_aldps(tp);
3429 rtl8168h_config_eee_phy(tp);
3430 rtl_enable_eee(tp);
3431}
3432
3433static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3434{
3435 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3436 u16 rlen;
3437 u32 data;
3438
3439 rtl_apply_firmware(tp);
3440
3441 /* CHIN EST parameter update */
3442 rtl_writephy(tp, 0x1f, 0x0a43);
3443 rtl_writephy(tp, 0x13, 0x808a);
3444 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3445 rtl_writephy(tp, 0x1f, 0x0000);
3446
3447 /* enable R-tune & PGA-retune function */
3448 rtl_writephy(tp, 0x1f, 0x0a43);
3449 rtl_writephy(tp, 0x13, 0x0811);
3450 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3451 rtl_writephy(tp, 0x1f, 0x0a42);
3452 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3453 rtl_writephy(tp, 0x1f, 0x0000);
3454
3455 /* enable GPHY 10M */
3456 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3457
3458 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3459 data = r8168_mac_ocp_read(tp, 0xdd02);
3460 ioffset_p3 = ((data & 0x80)>>7);
3461 ioffset_p3 <<= 3;
3462
3463 data = r8168_mac_ocp_read(tp, 0xdd00);
3464 ioffset_p3 |= ((data & (0xe000))>>13);
3465 ioffset_p2 = ((data & (0x1e00))>>9);
3466 ioffset_p1 = ((data & (0x01e0))>>5);
3467 ioffset_p0 = ((data & 0x0010)>>4);
3468 ioffset_p0 <<= 3;
3469 ioffset_p0 |= (data & (0x07));
3470 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3471
3472 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3473 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3474 rtl_writephy(tp, 0x1f, 0x0bcf);
3475 rtl_writephy(tp, 0x16, data);
3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 }
3478
3479 /* Modify rlen (TX LPF corner frequency) level */
3480 rtl_writephy(tp, 0x1f, 0x0bcd);
3481 data = rtl_readphy(tp, 0x16);
3482 data &= 0x000f;
3483 rlen = 0;
3484 if (data > 3)
3485 rlen = data - 3;
3486 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3487 rtl_writephy(tp, 0x17, data);
3488 rtl_writephy(tp, 0x1f, 0x0bcd);
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490
3491 /* disable phy pfm mode */
3492 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3493
3494 rtl8168g_disable_aldps(tp);
3495 rtl8168g_config_eee_phy(tp);
3496 rtl_enable_eee(tp);
3497}
3498
3499static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3500{
3501 /* Enable PHY auto speed down */
3502 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3503
3504 rtl8168g_phy_adjust_10m_aldps(tp);
3505
3506 /* Enable EEE auto-fallback function */
3507 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3508
3509 /* Enable UC LPF tune function */
3510 rtl_writephy(tp, 0x1f, 0x0a43);
3511 rtl_writephy(tp, 0x13, 0x8012);
3512 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3513 rtl_writephy(tp, 0x1f, 0x0000);
3514
3515 /* set rg_sel_sdm_rate */
3516 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3517
3518 rtl8168g_disable_aldps(tp);
3519 rtl8168g_config_eee_phy(tp);
3520 rtl_enable_eee(tp);
3521}
3522
3523static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3524{
3525 rtl8168g_phy_adjust_10m_aldps(tp);
3526
3527 /* Enable UC LPF tune function */
3528 rtl_writephy(tp, 0x1f, 0x0a43);
3529 rtl_writephy(tp, 0x13, 0x8012);
3530 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3531 rtl_writephy(tp, 0x1f, 0x0000);
3532
3533 /* Set rg_sel_sdm_rate */
3534 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3535
3536 /* Channel estimation parameters */
3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x80f3);
3539 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3540 rtl_writephy(tp, 0x13, 0x80f0);
3541 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3542 rtl_writephy(tp, 0x13, 0x80ef);
3543 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3544 rtl_writephy(tp, 0x13, 0x80f6);
3545 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3546 rtl_writephy(tp, 0x13, 0x80ec);
3547 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3548 rtl_writephy(tp, 0x13, 0x80ed);
3549 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3550 rtl_writephy(tp, 0x13, 0x80f2);
3551 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3552 rtl_writephy(tp, 0x13, 0x80f4);
3553 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3554 rtl_writephy(tp, 0x1f, 0x0a43);
3555 rtl_writephy(tp, 0x13, 0x8110);
3556 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3557 rtl_writephy(tp, 0x13, 0x810f);
3558 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3559 rtl_writephy(tp, 0x13, 0x8111);
3560 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3561 rtl_writephy(tp, 0x13, 0x8113);
3562 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3563 rtl_writephy(tp, 0x13, 0x8115);
3564 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3565 rtl_writephy(tp, 0x13, 0x810e);
3566 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3567 rtl_writephy(tp, 0x13, 0x810c);
3568 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3569 rtl_writephy(tp, 0x13, 0x810b);
3570 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3571 rtl_writephy(tp, 0x1f, 0x0a43);
3572 rtl_writephy(tp, 0x13, 0x80d1);
3573 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3574 rtl_writephy(tp, 0x13, 0x80cd);
3575 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3576 rtl_writephy(tp, 0x13, 0x80d3);
3577 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3578 rtl_writephy(tp, 0x13, 0x80d5);
3579 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3580 rtl_writephy(tp, 0x13, 0x80d7);
3581 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3582
3583 /* Force PWM-mode */
3584 rtl_writephy(tp, 0x1f, 0x0bcd);
3585 rtl_writephy(tp, 0x14, 0x5065);
3586 rtl_writephy(tp, 0x14, 0xd065);
3587 rtl_writephy(tp, 0x1f, 0x0bc8);
3588 rtl_writephy(tp, 0x12, 0x00ed);
3589 rtl_writephy(tp, 0x1f, 0x0bcd);
3590 rtl_writephy(tp, 0x14, 0x1065);
3591 rtl_writephy(tp, 0x14, 0x9065);
3592 rtl_writephy(tp, 0x14, 0x1065);
3593 rtl_writephy(tp, 0x1f, 0x0000);
3594
3595 rtl8168g_disable_aldps(tp);
3596 rtl8168g_config_eee_phy(tp);
3597 rtl_enable_eee(tp);
3598}
3599
3600static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3601{
3602 static const struct phy_reg phy_reg_init[] = {
3603 { 0x1f, 0x0003 },
3604 { 0x08, 0x441d },
3605 { 0x01, 0x9100 },
3606 { 0x1f, 0x0000 }
3607 };
3608
3609 rtl_writephy(tp, 0x1f, 0x0000);
3610 rtl_patchphy(tp, 0x11, 1 << 12);
3611 rtl_patchphy(tp, 0x19, 1 << 13);
3612 rtl_patchphy(tp, 0x10, 1 << 15);
3613
3614 rtl_writephy_batch(tp, phy_reg_init);
3615}
3616
3617static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3618{
3619 static const struct phy_reg phy_reg_init[] = {
3620 { 0x1f, 0x0005 },
3621 { 0x1a, 0x0000 },
3622 { 0x1f, 0x0000 },
3623
3624 { 0x1f, 0x0004 },
3625 { 0x1c, 0x0000 },
3626 { 0x1f, 0x0000 },
3627
3628 { 0x1f, 0x0001 },
3629 { 0x15, 0x7701 },
3630 { 0x1f, 0x0000 }
3631 };
3632
3633 /* Disable ALDPS before ram code */
3634 rtl_writephy(tp, 0x1f, 0x0000);
3635 rtl_writephy(tp, 0x18, 0x0310);
3636 msleep(100);
3637
3638 rtl_apply_firmware(tp);
3639
3640 rtl_writephy_batch(tp, phy_reg_init);
3641}
3642
3643static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3644{
3645 /* Disable ALDPS before setting firmware */
3646 rtl_writephy(tp, 0x1f, 0x0000);
3647 rtl_writephy(tp, 0x18, 0x0310);
3648 msleep(20);
3649
3650 rtl_apply_firmware(tp);
3651
3652 /* EEE setting */
3653 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3654 rtl_writephy(tp, 0x1f, 0x0004);
3655 rtl_writephy(tp, 0x10, 0x401f);
3656 rtl_writephy(tp, 0x19, 0x7030);
3657 rtl_writephy(tp, 0x1f, 0x0000);
3658}
3659
3660static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3661{
3662 static const struct phy_reg phy_reg_init[] = {
3663 { 0x1f, 0x0004 },
3664 { 0x10, 0xc07f },
3665 { 0x19, 0x7030 },
3666 { 0x1f, 0x0000 }
3667 };
3668
3669 /* Disable ALDPS before ram code */
3670 rtl_writephy(tp, 0x1f, 0x0000);
3671 rtl_writephy(tp, 0x18, 0x0310);
3672 msleep(100);
3673
3674 rtl_apply_firmware(tp);
3675
3676 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3677 rtl_writephy_batch(tp, phy_reg_init);
3678
3679 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3680}
3681
3682static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3683{
3684 struct phy_device *phydev = tp->phydev;
3685
3686 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3687 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3688 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3689 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3690 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3691 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3692 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3693 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3694 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3695
3696 phy_write(phydev, 0x1f, 0x0a43);
3697 phy_write(phydev, 0x13, 0x80ea);
3698 phy_modify(phydev, 0x14, 0xff00, 0xc400);
3699 phy_write(phydev, 0x13, 0x80eb);
3700 phy_modify(phydev, 0x14, 0x0700, 0x0300);
3701 phy_write(phydev, 0x13, 0x80f8);
3702 phy_modify(phydev, 0x14, 0xff00, 0x1c00);
3703 phy_write(phydev, 0x13, 0x80f1);
3704 phy_modify(phydev, 0x14, 0xff00, 0x3000);
3705 phy_write(phydev, 0x13, 0x80fe);
3706 phy_modify(phydev, 0x14, 0xff00, 0xa500);
3707 phy_write(phydev, 0x13, 0x8102);
3708 phy_modify(phydev, 0x14, 0xff00, 0x5000);
3709 phy_write(phydev, 0x13, 0x8105);
3710 phy_modify(phydev, 0x14, 0xff00, 0x3300);
3711 phy_write(phydev, 0x13, 0x8100);
3712 phy_modify(phydev, 0x14, 0xff00, 0x7000);
3713 phy_write(phydev, 0x13, 0x8104);
3714 phy_modify(phydev, 0x14, 0xff00, 0xf000);
3715 phy_write(phydev, 0x13, 0x8106);
3716 phy_modify(phydev, 0x14, 0xff00, 0x6500);
3717 phy_write(phydev, 0x13, 0x80dc);
3718 phy_modify(phydev, 0x14, 0xff00, 0xed00);
3719 phy_write(phydev, 0x13, 0x80df);
3720 phy_set_bits(phydev, 0x14, BIT(8));
3721 phy_write(phydev, 0x13, 0x80e1);
3722 phy_clear_bits(phydev, 0x14, BIT(8));
3723 phy_write(phydev, 0x1f, 0x0000);
3724
3725 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
3726 phy_write_paged(phydev, 0xa43, 0x13, 0x819f);
3727 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6);
3728
3729 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3730 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3731 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3732 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3733
3734 rtl8125_config_eee_phy(tp);
3735 rtl_enable_eee(tp);
3736}
3737
3738static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3739{
3740 struct phy_device *phydev = tp->phydev;
3741 int i;
3742
3743 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3744 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3745 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3746 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3747 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3748 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3749 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3750 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3751 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3752 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3753 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3754 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3755
3756 phy_write(phydev, 0x1f, 0x0b87);
3757 phy_write(phydev, 0x16, 0x80a2);
3758 phy_write(phydev, 0x17, 0x0153);
3759 phy_write(phydev, 0x16, 0x809c);
3760 phy_write(phydev, 0x17, 0x0153);
3761 phy_write(phydev, 0x1f, 0x0000);
3762
3763 phy_write(phydev, 0x1f, 0x0a43);
3764 phy_write(phydev, 0x13, 0x81B3);
3765 phy_write(phydev, 0x14, 0x0043);
3766 phy_write(phydev, 0x14, 0x00A7);
3767 phy_write(phydev, 0x14, 0x00D6);
3768 phy_write(phydev, 0x14, 0x00EC);
3769 phy_write(phydev, 0x14, 0x00F6);
3770 phy_write(phydev, 0x14, 0x00FB);
3771 phy_write(phydev, 0x14, 0x00FD);
3772 phy_write(phydev, 0x14, 0x00FF);
3773 phy_write(phydev, 0x14, 0x00BB);
3774 phy_write(phydev, 0x14, 0x0058);
3775 phy_write(phydev, 0x14, 0x0029);
3776 phy_write(phydev, 0x14, 0x0013);
3777 phy_write(phydev, 0x14, 0x0009);
3778 phy_write(phydev, 0x14, 0x0004);
3779 phy_write(phydev, 0x14, 0x0002);
3780 for (i = 0; i < 25; i++)
3781 phy_write(phydev, 0x14, 0x0000);
3782
3783 phy_write(phydev, 0x13, 0x8257);
3784 phy_write(phydev, 0x14, 0x020F);
3785
3786 phy_write(phydev, 0x13, 0x80EA);
3787 phy_write(phydev, 0x14, 0x7843);
3788 phy_write(phydev, 0x1f, 0x0000);
3789
3790 rtl_apply_firmware(tp);
3791
3792 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3793
3794 phy_write(phydev, 0x1f, 0x0a43);
3795 phy_write(phydev, 0x13, 0x81a2);
3796 phy_set_bits(phydev, 0x14, BIT(8));
3797 phy_write(phydev, 0x1f, 0x0000);
3798
3799 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3800 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3801 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3802 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3803 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3804 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3805
3806 rtl8125_config_eee_phy(tp);
3807 rtl_enable_eee(tp);
3808}
3809
3810static void rtl_hw_phy_config(struct net_device *dev)
3811{
3812 static const rtl_generic_fct phy_configs[] = {
3813 /* PCI devices. */
3814 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3815 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3816 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3817 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3818 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3819 /* PCI-E devices. */
3820 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3821 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3822 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3823 [RTL_GIGA_MAC_VER_10] = NULL,
3824 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3825 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3826 [RTL_GIGA_MAC_VER_13] = NULL,
3827 [RTL_GIGA_MAC_VER_14] = NULL,
3828 [RTL_GIGA_MAC_VER_15] = NULL,
3829 [RTL_GIGA_MAC_VER_16] = NULL,
3830 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3831 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3832 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3833 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3834 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3835 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3836 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3837 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3838 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3839 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3840 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3841 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3842 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3843 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3844 [RTL_GIGA_MAC_VER_31] = NULL,
3845 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3846 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3847 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3848 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3849 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3850 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3851 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3852 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3853 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3854 [RTL_GIGA_MAC_VER_41] = NULL,
3855 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3856 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3857 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3858 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3859 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3860 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3861 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3862 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3863 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3864 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3865 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3866 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
3867 };
3868 struct rtl8169_private *tp = netdev_priv(dev);
3869
3870 if (phy_configs[tp->mac_version])
3871 phy_configs[tp->mac_version](tp);
3872}
3873
3874static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3875{
3876 if (!test_and_set_bit(flag, tp->wk.flags))
3877 schedule_work(&tp->wk.work);
3878}
3879
3880static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3881{
3882 rtl_hw_phy_config(dev);
3883
3884 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3885 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3886 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3887 netif_dbg(tp, drv, dev,
3888 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3889 RTL_W8(tp, 0x82, 0x01);
3890 }
3891
3892 /* We may have called phy_speed_down before */
3893 phy_speed_up(tp->phydev);
3894
3895 genphy_soft_reset(tp->phydev);
3896}
3897
3898static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3899{
3900 rtl_lock_work(tp);
3901
3902 rtl_unlock_config_regs(tp);
3903
3904 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3905 RTL_R32(tp, MAC4);
3906
3907 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3908 RTL_R32(tp, MAC0);
3909
3910 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3911 rtl_rar_exgmac_set(tp, addr);
3912
3913 rtl_lock_config_regs(tp);
3914
3915 rtl_unlock_work(tp);
3916}
3917
3918static int rtl_set_mac_address(struct net_device *dev, void *p)
3919{
3920 struct rtl8169_private *tp = netdev_priv(dev);
3921 struct device *d = tp_to_dev(tp);
3922 int ret;
3923
3924 ret = eth_mac_addr(dev, p);
3925 if (ret)
3926 return ret;
3927
3928 pm_runtime_get_noresume(d);
3929
3930 if (pm_runtime_active(d))
3931 rtl_rar_set(tp, dev->dev_addr);
3932
3933 pm_runtime_put_noidle(d);
3934
3935 return 0;
3936}
3937
3938static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3939{
3940 struct rtl8169_private *tp = netdev_priv(dev);
3941
3942 if (!netif_running(dev))
3943 return -ENODEV;
3944
3945 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3946}
3947
3948static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3949{
3950 switch (tp->mac_version) {
3951 case RTL_GIGA_MAC_VER_25:
3952 case RTL_GIGA_MAC_VER_26:
3953 case RTL_GIGA_MAC_VER_29:
3954 case RTL_GIGA_MAC_VER_30:
3955 case RTL_GIGA_MAC_VER_32:
3956 case RTL_GIGA_MAC_VER_33:
3957 case RTL_GIGA_MAC_VER_34:
3958 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
3959 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3960 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3961 break;
3962 default:
3963 break;
3964 }
3965}
3966
3967static void rtl_pll_power_down(struct rtl8169_private *tp)
3968{
3969 if (r8168_check_dash(tp))
3970 return;
3971
3972 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3973 tp->mac_version == RTL_GIGA_MAC_VER_33)
3974 rtl_ephy_write(tp, 0x19, 0xff64);
3975
3976 if (device_may_wakeup(tp_to_dev(tp))) {
3977 phy_speed_down(tp->phydev, false);
3978 rtl_wol_suspend_quirk(tp);
3979 return;
3980 }
3981
3982 switch (tp->mac_version) {
3983 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
3984 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
3985 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
3986 case RTL_GIGA_MAC_VER_37:
3987 case RTL_GIGA_MAC_VER_39:
3988 case RTL_GIGA_MAC_VER_43:
3989 case RTL_GIGA_MAC_VER_44:
3990 case RTL_GIGA_MAC_VER_45:
3991 case RTL_GIGA_MAC_VER_46:
3992 case RTL_GIGA_MAC_VER_47:
3993 case RTL_GIGA_MAC_VER_48:
3994 case RTL_GIGA_MAC_VER_50:
3995 case RTL_GIGA_MAC_VER_51:
3996 case RTL_GIGA_MAC_VER_60:
3997 case RTL_GIGA_MAC_VER_61:
3998 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3999 break;
4000 case RTL_GIGA_MAC_VER_40:
4001 case RTL_GIGA_MAC_VER_41:
4002 case RTL_GIGA_MAC_VER_49:
4003 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4004 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4005 break;
4006 default:
4007 break;
4008 }
4009}
4010
4011static void rtl_pll_power_up(struct rtl8169_private *tp)
4012{
4013 switch (tp->mac_version) {
4014 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
4015 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
4016 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
4017 case RTL_GIGA_MAC_VER_37:
4018 case RTL_GIGA_MAC_VER_39:
4019 case RTL_GIGA_MAC_VER_43:
4020 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4021 break;
4022 case RTL_GIGA_MAC_VER_44:
4023 case RTL_GIGA_MAC_VER_45:
4024 case RTL_GIGA_MAC_VER_46:
4025 case RTL_GIGA_MAC_VER_47:
4026 case RTL_GIGA_MAC_VER_48:
4027 case RTL_GIGA_MAC_VER_50:
4028 case RTL_GIGA_MAC_VER_51:
4029 case RTL_GIGA_MAC_VER_60:
4030 case RTL_GIGA_MAC_VER_61:
4031 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4032 break;
4033 case RTL_GIGA_MAC_VER_40:
4034 case RTL_GIGA_MAC_VER_41:
4035 case RTL_GIGA_MAC_VER_49:
4036 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4037 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4038 break;
4039 default:
4040 break;
4041 }
4042
4043 phy_resume(tp->phydev);
4044 /* give MAC/PHY some time to resume */
4045 msleep(20);
4046}
4047
4048static void rtl_init_rxcfg(struct rtl8169_private *tp)
4049{
4050 switch (tp->mac_version) {
4051 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4052 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4053 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4054 break;
4055 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4056 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4057 case RTL_GIGA_MAC_VER_38:
4058 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4059 break;
4060 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4061 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4062 break;
4063 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4064 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4065 RX_DMA_BURST);
4066 break;
4067 default:
4068 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4069 break;
4070 }
4071}
4072
4073static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4074{
4075 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4076}
4077
4078static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4079{
4080 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4081 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4082}
4083
4084static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4085{
4086 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4087 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4088}
4089
4090static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4091{
4092 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4093}
4094
4095static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4096{
4097 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4098}
4099
4100static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4101{
4102 RTL_W8(tp, MaxTxPacketSize, 0x24);
4103 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4104 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4105}
4106
4107static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4108{
4109 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4110 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4111 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4112}
4113
4114static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4115{
4116 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4117}
4118
4119static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4120{
4121 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4122}
4123
4124static void rtl_jumbo_config(struct rtl8169_private *tp)
4125{
4126 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
4127 int readrq = 4096;
4128
4129 rtl_unlock_config_regs(tp);
4130 switch (tp->mac_version) {
4131 case RTL_GIGA_MAC_VER_12:
4132 case RTL_GIGA_MAC_VER_17:
4133 if (jumbo) {
4134 readrq = 512;
4135 r8168b_1_hw_jumbo_enable(tp);
4136 } else {
4137 r8168b_1_hw_jumbo_disable(tp);
4138 }
4139 break;
4140 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4141 if (jumbo) {
4142 readrq = 512;
4143 r8168c_hw_jumbo_enable(tp);
4144 } else {
4145 r8168c_hw_jumbo_disable(tp);
4146 }
4147 break;
4148 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4149 if (jumbo)
4150 r8168dp_hw_jumbo_enable(tp);
4151 else
4152 r8168dp_hw_jumbo_disable(tp);
4153 break;
4154 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
4155 if (jumbo) {
4156 pcie_set_readrq(tp->pci_dev, 512);
4157 r8168e_hw_jumbo_enable(tp);
4158 } else {
4159 r8168e_hw_jumbo_disable(tp);
4160 }
4161 break;
4162 default:
4163 break;
4164 }
4165 rtl_lock_config_regs(tp);
4166
4167 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
4168 pcie_set_readrq(tp->pci_dev, readrq);
4169
4170 /* Chip doesn't support pause in jumbo mode */
4171 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
4172 tp->phydev->advertising, !jumbo);
4173 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
4174 tp->phydev->advertising, !jumbo);
4175 phy_start_aneg(tp->phydev);
4176}
4177
4178DECLARE_RTL_COND(rtl_chipcmd_cond)
4179{
4180 return RTL_R8(tp, ChipCmd) & CmdReset;
4181}
4182
4183static void rtl_hw_reset(struct rtl8169_private *tp)
4184{
4185 RTL_W8(tp, ChipCmd, CmdReset);
4186
4187 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4188}
4189
4190static void rtl_request_firmware(struct rtl8169_private *tp)
4191{
4192 struct rtl_fw *rtl_fw;
4193
4194 /* firmware loaded already or no firmware available */
4195 if (tp->rtl_fw || !tp->fw_name)
4196 return;
4197
4198 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4199 if (!rtl_fw) {
4200 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4201 return;
4202 }
4203
4204 rtl_fw->phy_write = rtl_writephy;
4205 rtl_fw->phy_read = rtl_readphy;
4206 rtl_fw->mac_mcu_write = mac_mcu_write;
4207 rtl_fw->mac_mcu_read = mac_mcu_read;
4208 rtl_fw->fw_name = tp->fw_name;
4209 rtl_fw->dev = tp_to_dev(tp);
4210
4211 if (rtl_fw_request_firmware(rtl_fw))
4212 kfree(rtl_fw);
4213 else
4214 tp->rtl_fw = rtl_fw;
4215}
4216
4217static void rtl_rx_close(struct rtl8169_private *tp)
4218{
4219 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4220}
4221
4222DECLARE_RTL_COND(rtl_npq_cond)
4223{
4224 return RTL_R8(tp, TxPoll) & NPQ;
4225}
4226
4227DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4228{
4229 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4230}
4231
4232static void rtl8169_hw_reset(struct rtl8169_private *tp)
4233{
4234 /* Disable interrupts */
4235 rtl8169_irq_mask_and_ack(tp);
4236
4237 rtl_rx_close(tp);
4238
4239 switch (tp->mac_version) {
4240 case RTL_GIGA_MAC_VER_27:
4241 case RTL_GIGA_MAC_VER_28:
4242 case RTL_GIGA_MAC_VER_31:
4243 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4244 break;
4245 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4246 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4247 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4248 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4249 break;
4250 default:
4251 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4252 udelay(100);
4253 break;
4254 }
4255
4256 rtl_hw_reset(tp);
4257}
4258
4259static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4260{
4261 u32 val = TX_DMA_BURST << TxDMAShift |
4262 InterFrameGap << TxInterFrameGapShift;
4263
4264 if (rtl_is_8168evl_up(tp))
4265 val |= TXCFG_AUTO_FIFO;
4266
4267 RTL_W32(tp, TxConfig, val);
4268}
4269
4270static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4271{
4272 /* Low hurts. Let's disable the filtering. */
4273 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4274}
4275
4276static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4277{
4278 /*
4279 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4280 * register to be written before TxDescAddrLow to work.
4281 * Switching from MMIO to I/O access fixes the issue as well.
4282 */
4283 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4284 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4285 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4286 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4287}
4288
4289static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4290{
4291 u32 val;
4292
4293 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4294 val = 0x000fff00;
4295 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4296 val = 0x00ffff00;
4297 else
4298 return;
4299
4300 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4301 val |= 0xff;
4302
4303 RTL_W32(tp, 0x7c, val);
4304}
4305
4306static void rtl_set_rx_mode(struct net_device *dev)
4307{
4308 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4309 /* Multicast hash filter */
4310 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4311 struct rtl8169_private *tp = netdev_priv(dev);
4312 u32 tmp;
4313
4314 if (dev->flags & IFF_PROMISC) {
4315 /* Unconditionally log net taps. */
4316 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4317 rx_mode |= AcceptAllPhys;
4318 } else if (!(dev->flags & IFF_MULTICAST)) {
4319 rx_mode &= ~AcceptMulticast;
4320 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4321 dev->flags & IFF_ALLMULTI ||
4322 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4323 /* accept all multicasts */
4324 } else if (netdev_mc_empty(dev)) {
4325 rx_mode &= ~AcceptMulticast;
4326 } else {
4327 struct netdev_hw_addr *ha;
4328
4329 mc_filter[1] = mc_filter[0] = 0;
4330 netdev_for_each_mc_addr(ha, dev) {
4331 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4332 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4333 }
4334
4335 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4336 tmp = mc_filter[0];
4337 mc_filter[0] = swab32(mc_filter[1]);
4338 mc_filter[1] = swab32(tmp);
4339 }
4340 }
4341
4342 if (dev->features & NETIF_F_RXALL)
4343 rx_mode |= (AcceptErr | AcceptRunt);
4344
4345 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4346 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4347
4348 tmp = RTL_R32(tp, RxConfig);
4349 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4350}
4351
4352DECLARE_RTL_COND(rtl_csiar_cond)
4353{
4354 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4355}
4356
4357static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4358{
4359 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4360
4361 RTL_W32(tp, CSIDR, value);
4362 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4363 CSIAR_BYTE_ENABLE | func << 16);
4364
4365 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4366}
4367
4368static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4369{
4370 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4371
4372 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4373 CSIAR_BYTE_ENABLE);
4374
4375 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4376 RTL_R32(tp, CSIDR) : ~0;
4377}
4378
4379static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4380{
4381 struct pci_dev *pdev = tp->pci_dev;
4382 u32 csi;
4383
4384 /* According to Realtek the value at config space address 0x070f
4385 * controls the L0s/L1 entrance latency. We try standard ECAM access
4386 * first and if it fails fall back to CSI.
4387 */
4388 if (pdev->cfg_size > 0x070f &&
4389 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4390 return;
4391
4392 netdev_notice_once(tp->dev,
4393 "No native access to PCI extended config space, falling back to CSI\n");
4394 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4395 rtl_csi_write(tp, 0x070c, csi | val << 24);
4396}
4397
4398static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4399{
4400 rtl_csi_access_enable(tp, 0x27);
4401}
4402
4403struct ephy_info {
4404 unsigned int offset;
4405 u16 mask;
4406 u16 bits;
4407};
4408
4409static void __rtl_ephy_init(struct rtl8169_private *tp,
4410 const struct ephy_info *e, int len)
4411{
4412 u16 w;
4413
4414 while (len-- > 0) {
4415 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4416 rtl_ephy_write(tp, e->offset, w);
4417 e++;
4418 }
4419}
4420
4421#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4422
4423static void rtl_disable_clock_request(struct rtl8169_private *tp)
4424{
4425 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4426 PCI_EXP_LNKCTL_CLKREQ_EN);
4427}
4428
4429static void rtl_enable_clock_request(struct rtl8169_private *tp)
4430{
4431 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4432 PCI_EXP_LNKCTL_CLKREQ_EN);
4433}
4434
4435static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4436{
4437 /* work around an issue when PCI reset occurs during L2/L3 state */
4438 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4439}
4440
4441static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4442{
4443 /* Don't enable ASPM in the chip if OS can't control ASPM */
4444 if (enable && tp->aspm_manageable) {
4445 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4446 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4447 } else {
4448 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4449 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4450 }
4451
4452 udelay(10);
4453}
4454
4455static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4456 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4457{
4458 /* Usage of dynamic vs. static FIFO is controlled by bit
4459 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4460 */
4461 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4462 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4463}
4464
4465static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4466 u8 low, u8 high)
4467{
4468 /* FIFO thresholds for pause flow control */
4469 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4470 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4471}
4472
4473static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4474{
4475 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4476}
4477
4478static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4479{
4480 rtl_hw_start_8168bb(tp);
4481
4482 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4483}
4484
4485static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4486{
4487 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4488
4489 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4490
4491 rtl_disable_clock_request(tp);
4492}
4493
4494static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4495{
4496 static const struct ephy_info e_info_8168cp[] = {
4497 { 0x01, 0, 0x0001 },
4498 { 0x02, 0x0800, 0x1000 },
4499 { 0x03, 0, 0x0042 },
4500 { 0x06, 0x0080, 0x0000 },
4501 { 0x07, 0, 0x2000 }
4502 };
4503
4504 rtl_set_def_aspm_entry_latency(tp);
4505
4506 rtl_ephy_init(tp, e_info_8168cp);
4507
4508 __rtl_hw_start_8168cp(tp);
4509}
4510
4511static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4512{
4513 rtl_set_def_aspm_entry_latency(tp);
4514
4515 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4516}
4517
4518static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4519{
4520 rtl_set_def_aspm_entry_latency(tp);
4521
4522 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4523
4524 /* Magic. */
4525 RTL_W8(tp, DBG_REG, 0x20);
4526}
4527
4528static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4529{
4530 static const struct ephy_info e_info_8168c_1[] = {
4531 { 0x02, 0x0800, 0x1000 },
4532 { 0x03, 0, 0x0002 },
4533 { 0x06, 0x0080, 0x0000 }
4534 };
4535
4536 rtl_set_def_aspm_entry_latency(tp);
4537
4538 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4539
4540 rtl_ephy_init(tp, e_info_8168c_1);
4541
4542 __rtl_hw_start_8168cp(tp);
4543}
4544
4545static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4546{
4547 static const struct ephy_info e_info_8168c_2[] = {
4548 { 0x01, 0, 0x0001 },
4549 { 0x03, 0x0400, 0x0020 }
4550 };
4551
4552 rtl_set_def_aspm_entry_latency(tp);
4553
4554 rtl_ephy_init(tp, e_info_8168c_2);
4555
4556 __rtl_hw_start_8168cp(tp);
4557}
4558
4559static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4560{
4561 rtl_hw_start_8168c_2(tp);
4562}
4563
4564static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4565{
4566 rtl_set_def_aspm_entry_latency(tp);
4567
4568 __rtl_hw_start_8168cp(tp);
4569}
4570
4571static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4572{
4573 rtl_set_def_aspm_entry_latency(tp);
4574
4575 rtl_disable_clock_request(tp);
4576}
4577
4578static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4579{
4580 rtl_set_def_aspm_entry_latency(tp);
4581
4582 rtl_disable_clock_request(tp);
4583}
4584
4585static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4586{
4587 static const struct ephy_info e_info_8168d_4[] = {
4588 { 0x0b, 0x0000, 0x0048 },
4589 { 0x19, 0x0020, 0x0050 },
4590 { 0x0c, 0x0100, 0x0020 },
4591 { 0x10, 0x0004, 0x0000 },
4592 };
4593
4594 rtl_set_def_aspm_entry_latency(tp);
4595
4596 rtl_ephy_init(tp, e_info_8168d_4);
4597
4598 rtl_enable_clock_request(tp);
4599}
4600
4601static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4602{
4603 static const struct ephy_info e_info_8168e_1[] = {
4604 { 0x00, 0x0200, 0x0100 },
4605 { 0x00, 0x0000, 0x0004 },
4606 { 0x06, 0x0002, 0x0001 },
4607 { 0x06, 0x0000, 0x0030 },
4608 { 0x07, 0x0000, 0x2000 },
4609 { 0x00, 0x0000, 0x0020 },
4610 { 0x03, 0x5800, 0x2000 },
4611 { 0x03, 0x0000, 0x0001 },
4612 { 0x01, 0x0800, 0x1000 },
4613 { 0x07, 0x0000, 0x4000 },
4614 { 0x1e, 0x0000, 0x2000 },
4615 { 0x19, 0xffff, 0xfe6c },
4616 { 0x0a, 0x0000, 0x0040 }
4617 };
4618
4619 rtl_set_def_aspm_entry_latency(tp);
4620
4621 rtl_ephy_init(tp, e_info_8168e_1);
4622
4623 rtl_disable_clock_request(tp);
4624
4625 /* Reset tx FIFO pointer */
4626 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4627 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4628
4629 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4630}
4631
4632static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4633{
4634 static const struct ephy_info e_info_8168e_2[] = {
4635 { 0x09, 0x0000, 0x0080 },
4636 { 0x19, 0x0000, 0x0224 },
4637 { 0x00, 0x0000, 0x0004 },
4638 { 0x0c, 0x3df0, 0x0200 },
4639 };
4640
4641 rtl_set_def_aspm_entry_latency(tp);
4642
4643 rtl_ephy_init(tp, e_info_8168e_2);
4644
4645 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4646 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4647 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4648 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4649 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4650 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4651 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4652
4653 rtl_disable_clock_request(tp);
4654
4655 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4656
4657 rtl8168_config_eee_mac(tp);
4658
4659 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4660 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4661 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4662
4663 rtl_hw_aspm_clkreq_enable(tp, true);
4664}
4665
4666static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4667{
4668 rtl_set_def_aspm_entry_latency(tp);
4669
4670 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4671 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4672 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4673 rtl_reset_packet_filter(tp);
4674 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4675 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4676 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4677 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4678
4679 rtl_disable_clock_request(tp);
4680
4681 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4682 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4683 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4684 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4685
4686 rtl8168_config_eee_mac(tp);
4687}
4688
4689static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4690{
4691 static const struct ephy_info e_info_8168f_1[] = {
4692 { 0x06, 0x00c0, 0x0020 },
4693 { 0x08, 0x0001, 0x0002 },
4694 { 0x09, 0x0000, 0x0080 },
4695 { 0x19, 0x0000, 0x0224 },
4696 { 0x00, 0x0000, 0x0008 },
4697 { 0x0c, 0x3df0, 0x0200 },
4698 };
4699
4700 rtl_hw_start_8168f(tp);
4701
4702 rtl_ephy_init(tp, e_info_8168f_1);
4703
4704 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4705}
4706
4707static void rtl_hw_start_8411(struct rtl8169_private *tp)
4708{
4709 static const struct ephy_info e_info_8168f_1[] = {
4710 { 0x06, 0x00c0, 0x0020 },
4711 { 0x0f, 0xffff, 0x5200 },
4712 { 0x19, 0x0000, 0x0224 },
4713 { 0x00, 0x0000, 0x0008 },
4714 { 0x0c, 0x3df0, 0x0200 },
4715 };
4716
4717 rtl_hw_start_8168f(tp);
4718 rtl_pcie_state_l2l3_disable(tp);
4719
4720 rtl_ephy_init(tp, e_info_8168f_1);
4721
4722 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4723}
4724
4725static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4726{
4727 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4728 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4729
4730 rtl_set_def_aspm_entry_latency(tp);
4731
4732 rtl_reset_packet_filter(tp);
4733 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4734
4735 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4736
4737 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4738 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4739
4740 rtl8168_config_eee_mac(tp);
4741
4742 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4743 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4744
4745 rtl_pcie_state_l2l3_disable(tp);
4746 rtl_hw_aspm_clkreq_enable(tp, true);
4747}
4748
4749static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4750{
4751 static const struct ephy_info e_info_8168g_1[] = {
4752 { 0x00, 0x0008, 0x0000 },
4753 { 0x0c, 0x3ff0, 0x0820 },
4754 { 0x1e, 0x0000, 0x0001 },
4755 { 0x19, 0x8000, 0x0000 }
4756 };
4757
4758 rtl_hw_start_8168g(tp);
4759
4760 /* disable aspm and clock request before access ephy */
4761 rtl_hw_aspm_clkreq_enable(tp, false);
4762 rtl_ephy_init(tp, e_info_8168g_1);
4763 rtl_hw_aspm_clkreq_enable(tp, true);
4764}
4765
4766static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4767{
4768 static const struct ephy_info e_info_8168g_2[] = {
4769 { 0x00, 0x0008, 0x0000 },
4770 { 0x0c, 0x3ff0, 0x0820 },
4771 { 0x19, 0xffff, 0x7c00 },
4772 { 0x1e, 0xffff, 0x20eb },
4773 { 0x0d, 0xffff, 0x1666 },
4774 { 0x00, 0xffff, 0x10a3 },
4775 { 0x06, 0xffff, 0xf050 },
4776 { 0x04, 0x0000, 0x0010 },
4777 { 0x1d, 0x4000, 0x0000 },
4778 };
4779
4780 rtl_hw_start_8168g(tp);
4781
4782 /* disable aspm and clock request before access ephy */
4783 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4784 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4785 rtl_ephy_init(tp, e_info_8168g_2);
4786}
4787
4788static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4789{
4790 static const struct ephy_info e_info_8411_2[] = {
4791 { 0x00, 0x0008, 0x0000 },
4792 { 0x0c, 0x37d0, 0x0820 },
4793 { 0x1e, 0x0000, 0x0001 },
4794 { 0x19, 0x8021, 0x0000 },
4795 { 0x1e, 0x0000, 0x2000 },
4796 { 0x0d, 0x0100, 0x0200 },
4797 { 0x00, 0x0000, 0x0080 },
4798 { 0x06, 0x0000, 0x0010 },
4799 { 0x04, 0x0000, 0x0010 },
4800 { 0x1d, 0x0000, 0x4000 },
4801 };
4802
4803 rtl_hw_start_8168g(tp);
4804
4805 /* disable aspm and clock request before access ephy */
4806 rtl_hw_aspm_clkreq_enable(tp, false);
4807 rtl_ephy_init(tp, e_info_8411_2);
4808
4809 /* The following Realtek-provided magic fixes an issue with the RX unit
4810 * getting confused after the PHY having been powered-down.
4811 */
4812 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4813 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4814 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4815 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4816 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4817 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4818 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4819 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4820 mdelay(3);
4821 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4822
4823 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4824 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4825 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4826 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4827 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4828 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4829 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4830 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4831 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4832 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4833 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4834 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4835 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4836 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4837 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4838 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4839 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4840 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4841 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4842 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4843 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4844 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4845 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4846 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4847 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4848 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4849 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4850 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4851 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4852 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4853 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4854 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4855 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4856 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4857 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4858 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4859 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4860 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4861 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4862 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4863 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4864 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4865 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4866 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4867 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4868 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4869 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4870 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4871 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4872 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4873 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4874 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4875 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4876 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4877 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4878 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4879 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4880 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4881 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4882 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4883 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4884 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4885 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4886 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4887 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4888 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4889 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4890 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4891 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4892 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4893 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4894 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4895 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4896 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4897 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4898 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4899 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4900 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4901 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4902 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4903 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4904 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4905 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4906 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4907 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4908 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4909 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4910 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4911 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4912 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4913 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4914 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4915 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4916 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4917 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4918 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4919 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4920 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4921 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4922 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4923 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4924 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4925 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4926 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4927 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4928 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4929 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4930 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4931 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4932 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4933 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4934
4935 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4936
4937 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4938 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4939 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4940 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4941 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4942 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4943 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4944
4945 rtl_hw_aspm_clkreq_enable(tp, true);
4946}
4947
4948static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4949{
4950 static const struct ephy_info e_info_8168h_1[] = {
4951 { 0x1e, 0x0800, 0x0001 },
4952 { 0x1d, 0x0000, 0x0800 },
4953 { 0x05, 0xffff, 0x2089 },
4954 { 0x06, 0xffff, 0x5881 },
4955 { 0x04, 0xffff, 0x854a },
4956 { 0x01, 0xffff, 0x068b }
4957 };
4958 int rg_saw_cnt;
4959
4960 /* disable aspm and clock request before access ephy */
4961 rtl_hw_aspm_clkreq_enable(tp, false);
4962 rtl_ephy_init(tp, e_info_8168h_1);
4963
4964 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4965 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4966
4967 rtl_set_def_aspm_entry_latency(tp);
4968
4969 rtl_reset_packet_filter(tp);
4970
4971 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4972
4973 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4974
4975 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4976
4977 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4978
4979 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4980 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4981
4982 rtl8168_config_eee_mac(tp);
4983
4984 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4985 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4986
4987 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4988
4989 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4990
4991 rtl_pcie_state_l2l3_disable(tp);
4992
4993 rtl_writephy(tp, 0x1f, 0x0c42);
4994 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4995 rtl_writephy(tp, 0x1f, 0x0000);
4996 if (rg_saw_cnt > 0) {
4997 u16 sw_cnt_1ms_ini;
4998
4999 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5000 sw_cnt_1ms_ini &= 0x0fff;
5001 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
5002 }
5003
5004 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5005 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
5006 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
5007 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5008
5009 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5010 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5011 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5012 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5013
5014 rtl_hw_aspm_clkreq_enable(tp, true);
5015}
5016
5017static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5018{
5019 rtl8168ep_stop_cmac(tp);
5020
5021 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5022 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5023
5024 rtl_set_def_aspm_entry_latency(tp);
5025
5026 rtl_reset_packet_filter(tp);
5027
5028 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5029
5030 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5031
5032 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5033
5034 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5035 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5036
5037 rtl8168_config_eee_mac(tp);
5038
5039 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5040
5041 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5042
5043 rtl_pcie_state_l2l3_disable(tp);
5044}
5045
5046static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5047{
5048 static const struct ephy_info e_info_8168ep_1[] = {
5049 { 0x00, 0xffff, 0x10ab },
5050 { 0x06, 0xffff, 0xf030 },
5051 { 0x08, 0xffff, 0x2006 },
5052 { 0x0d, 0xffff, 0x1666 },
5053 { 0x0c, 0x3ff0, 0x0000 }
5054 };
5055
5056 /* disable aspm and clock request before access ephy */
5057 rtl_hw_aspm_clkreq_enable(tp, false);
5058 rtl_ephy_init(tp, e_info_8168ep_1);
5059
5060 rtl_hw_start_8168ep(tp);
5061
5062 rtl_hw_aspm_clkreq_enable(tp, true);
5063}
5064
5065static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5066{
5067 static const struct ephy_info e_info_8168ep_2[] = {
5068 { 0x00, 0xffff, 0x10a3 },
5069 { 0x19, 0xffff, 0xfc00 },
5070 { 0x1e, 0xffff, 0x20ea }
5071 };
5072
5073 /* disable aspm and clock request before access ephy */
5074 rtl_hw_aspm_clkreq_enable(tp, false);
5075 rtl_ephy_init(tp, e_info_8168ep_2);
5076
5077 rtl_hw_start_8168ep(tp);
5078
5079 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5080 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5081
5082 rtl_hw_aspm_clkreq_enable(tp, true);
5083}
5084
5085static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5086{
5087 static const struct ephy_info e_info_8168ep_3[] = {
5088 { 0x00, 0x0000, 0x0080 },
5089 { 0x0d, 0x0100, 0x0200 },
5090 { 0x19, 0x8021, 0x0000 },
5091 { 0x1e, 0x0000, 0x2000 },
5092 };
5093
5094 /* disable aspm and clock request before access ephy */
5095 rtl_hw_aspm_clkreq_enable(tp, false);
5096 rtl_ephy_init(tp, e_info_8168ep_3);
5097
5098 rtl_hw_start_8168ep(tp);
5099
5100 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5101 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5102
5103 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5104 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5105 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5106
5107 rtl_hw_aspm_clkreq_enable(tp, true);
5108}
5109
5110static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5111{
5112 static const struct ephy_info e_info_8102e_1[] = {
5113 { 0x01, 0, 0x6e65 },
5114 { 0x02, 0, 0x091f },
5115 { 0x03, 0, 0xc2f9 },
5116 { 0x06, 0, 0xafb5 },
5117 { 0x07, 0, 0x0e00 },
5118 { 0x19, 0, 0xec80 },
5119 { 0x01, 0, 0x2e65 },
5120 { 0x01, 0, 0x6e65 }
5121 };
5122 u8 cfg1;
5123
5124 rtl_set_def_aspm_entry_latency(tp);
5125
5126 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5127
5128 RTL_W8(tp, Config1,
5129 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5130 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5131
5132 cfg1 = RTL_R8(tp, Config1);
5133 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5134 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5135
5136 rtl_ephy_init(tp, e_info_8102e_1);
5137}
5138
5139static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5140{
5141 rtl_set_def_aspm_entry_latency(tp);
5142
5143 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5144 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5145}
5146
5147static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5148{
5149 rtl_hw_start_8102e_2(tp);
5150
5151 rtl_ephy_write(tp, 0x03, 0xc2f9);
5152}
5153
5154static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5155{
5156 static const struct ephy_info e_info_8105e_1[] = {
5157 { 0x07, 0, 0x4000 },
5158 { 0x19, 0, 0x0200 },
5159 { 0x19, 0, 0x0020 },
5160 { 0x1e, 0, 0x2000 },
5161 { 0x03, 0, 0x0001 },
5162 { 0x19, 0, 0x0100 },
5163 { 0x19, 0, 0x0004 },
5164 { 0x0a, 0, 0x0020 }
5165 };
5166
5167 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5168 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5169
5170 /* Disable Early Tally Counter */
5171 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5172
5173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5174 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5175
5176 rtl_ephy_init(tp, e_info_8105e_1);
5177
5178 rtl_pcie_state_l2l3_disable(tp);
5179}
5180
5181static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5182{
5183 rtl_hw_start_8105e_1(tp);
5184 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5185}
5186
5187static void rtl_hw_start_8402(struct rtl8169_private *tp)
5188{
5189 static const struct ephy_info e_info_8402[] = {
5190 { 0x19, 0xffff, 0xff64 },
5191 { 0x1e, 0, 0x4000 }
5192 };
5193
5194 rtl_set_def_aspm_entry_latency(tp);
5195
5196 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5197 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5198
5199 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5200
5201 rtl_ephy_init(tp, e_info_8402);
5202
5203 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5204 rtl_reset_packet_filter(tp);
5205 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5206 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5207 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5208
5209 rtl_pcie_state_l2l3_disable(tp);
5210}
5211
5212static void rtl_hw_start_8106(struct rtl8169_private *tp)
5213{
5214 rtl_hw_aspm_clkreq_enable(tp, false);
5215
5216 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5217 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5218
5219 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5220 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5221 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5222
5223 rtl_pcie_state_l2l3_disable(tp);
5224}
5225
5226DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5227{
5228 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5229}
5230
5231static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5232{
5233 rtl_pcie_state_l2l3_disable(tp);
5234
5235 RTL_W16(tp, 0x382, 0x221b);
5236 RTL_W8(tp, 0x4500, 0);
5237 RTL_W16(tp, 0x4800, 0);
5238
5239 /* disable UPS */
5240 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5241
5242 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5243
5244 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5245 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5246
5247 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5248 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5249 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5250
5251 /* disable new tx descriptor format */
5252 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5253
5254 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5255 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5256 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5257 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5258 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5259 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5260 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5261 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5262 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5263 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5264 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5265 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5266 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5267 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5268 udelay(1);
5269 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5270 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5271
5272 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5273
5274 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5275
5276 rtl8125_config_eee_mac(tp);
5277
5278 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5279 udelay(10);
5280}
5281
5282static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5283{
5284 static const struct ephy_info e_info_8125_1[] = {
5285 { 0x01, 0xffff, 0xa812 },
5286 { 0x09, 0xffff, 0x520c },
5287 { 0x04, 0xffff, 0xd000 },
5288 { 0x0d, 0xffff, 0xf702 },
5289 { 0x0a, 0xffff, 0x8653 },
5290 { 0x06, 0xffff, 0x001e },
5291 { 0x08, 0xffff, 0x3595 },
5292 { 0x20, 0xffff, 0x9455 },
5293 { 0x21, 0xffff, 0x99ff },
5294 { 0x02, 0xffff, 0x6046 },
5295 { 0x29, 0xffff, 0xfe00 },
5296 { 0x23, 0xffff, 0xab62 },
5297
5298 { 0x41, 0xffff, 0xa80c },
5299 { 0x49, 0xffff, 0x520c },
5300 { 0x44, 0xffff, 0xd000 },
5301 { 0x4d, 0xffff, 0xf702 },
5302 { 0x4a, 0xffff, 0x8653 },
5303 { 0x46, 0xffff, 0x001e },
5304 { 0x48, 0xffff, 0x3595 },
5305 { 0x60, 0xffff, 0x9455 },
5306 { 0x61, 0xffff, 0x99ff },
5307 { 0x42, 0xffff, 0x6046 },
5308 { 0x69, 0xffff, 0xfe00 },
5309 { 0x63, 0xffff, 0xab62 },
5310 };
5311
5312 rtl_set_def_aspm_entry_latency(tp);
5313
5314 /* disable aspm and clock request before access ephy */
5315 rtl_hw_aspm_clkreq_enable(tp, false);
5316 rtl_ephy_init(tp, e_info_8125_1);
5317
5318 rtl_hw_start_8125_common(tp);
5319}
5320
5321static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5322{
5323 static const struct ephy_info e_info_8125_2[] = {
5324 { 0x04, 0xffff, 0xd000 },
5325 { 0x0a, 0xffff, 0x8653 },
5326 { 0x23, 0xffff, 0xab66 },
5327 { 0x20, 0xffff, 0x9455 },
5328 { 0x21, 0xffff, 0x99ff },
5329 { 0x29, 0xffff, 0xfe04 },
5330
5331 { 0x44, 0xffff, 0xd000 },
5332 { 0x4a, 0xffff, 0x8653 },
5333 { 0x63, 0xffff, 0xab66 },
5334 { 0x60, 0xffff, 0x9455 },
5335 { 0x61, 0xffff, 0x99ff },
5336 { 0x69, 0xffff, 0xfe04 },
5337 };
5338
5339 rtl_set_def_aspm_entry_latency(tp);
5340
5341 /* disable aspm and clock request before access ephy */
5342 rtl_hw_aspm_clkreq_enable(tp, false);
5343 rtl_ephy_init(tp, e_info_8125_2);
5344
5345 rtl_hw_start_8125_common(tp);
5346}
5347
5348static void rtl_hw_config(struct rtl8169_private *tp)
5349{
5350 static const rtl_generic_fct hw_configs[] = {
5351 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5352 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5353 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5354 [RTL_GIGA_MAC_VER_10] = NULL,
5355 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5356 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5357 [RTL_GIGA_MAC_VER_13] = NULL,
5358 [RTL_GIGA_MAC_VER_14] = NULL,
5359 [RTL_GIGA_MAC_VER_15] = NULL,
5360 [RTL_GIGA_MAC_VER_16] = NULL,
5361 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5362 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5363 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5364 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5365 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5366 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5367 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5368 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5369 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5370 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5371 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5372 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5373 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5374 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5375 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5376 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5377 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5378 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5379 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5380 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5381 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5382 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5383 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5384 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5385 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5386 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5387 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5388 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5389 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5390 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5391 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5392 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5393 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5394 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5395 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5396 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5397 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
5398 };
5399
5400 if (hw_configs[tp->mac_version])
5401 hw_configs[tp->mac_version](tp);
5402}
5403
5404static void rtl_hw_start_8125(struct rtl8169_private *tp)
5405{
5406 int i;
5407
5408 /* disable interrupt coalescing */
5409 for (i = 0xa00; i < 0xb00; i += 4)
5410 RTL_W32(tp, i, 0);
5411
5412 rtl_hw_config(tp);
5413}
5414
5415static void rtl_hw_start_8168(struct rtl8169_private *tp)
5416{
5417 switch (tp->mac_version) {
5418 case RTL_GIGA_MAC_VER_11:
5419 case RTL_GIGA_MAC_VER_12:
5420 case RTL_GIGA_MAC_VER_13:
5421 case RTL_GIGA_MAC_VER_16:
5422 case RTL_GIGA_MAC_VER_17:
5423 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5424 PCI_EXP_DEVCTL_NOSNOOP_EN);
5425 break;
5426 default:
5427 break;
5428 }
5429
5430 if (rtl_is_8168evl_up(tp))
5431 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5432 else
5433 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5434
5435 rtl_hw_config(tp);
5436
5437 /* disable interrupt coalescing */
5438 RTL_W16(tp, IntrMitigate, 0x0000);
5439}
5440
5441static void rtl_hw_start_8169(struct rtl8169_private *tp)
5442{
5443 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5444 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5445
5446 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5447
5448 tp->cp_cmd |= PCIMulRW;
5449
5450 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5451 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5452 netif_dbg(tp, drv, tp->dev,
5453 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5454 tp->cp_cmd |= (1 << 14);
5455 }
5456
5457 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5458
5459 rtl8169_set_magic_reg(tp, tp->mac_version);
5460
5461 RTL_W32(tp, RxMissed, 0);
5462
5463 /* disable interrupt coalescing */
5464 RTL_W16(tp, IntrMitigate, 0x0000);
5465}
5466
5467static void rtl_hw_start(struct rtl8169_private *tp)
5468{
5469 rtl_unlock_config_regs(tp);
5470
5471 tp->cp_cmd &= CPCMD_MASK;
5472 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5473
5474 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5475 rtl_hw_start_8169(tp);
5476 else if (rtl_is_8125(tp))
5477 rtl_hw_start_8125(tp);
5478 else
5479 rtl_hw_start_8168(tp);
5480
5481 rtl_set_rx_max_size(tp);
5482 rtl_set_rx_tx_desc_registers(tp);
5483 rtl_lock_config_regs(tp);
5484
5485 rtl_jumbo_config(tp);
5486
5487 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5488 RTL_R16(tp, CPlusCmd);
5489 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5490 rtl_init_rxcfg(tp);
5491 rtl_set_tx_config_registers(tp);
5492 rtl_set_rx_mode(tp->dev);
5493 rtl_irq_enable(tp);
5494}
5495
5496static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5497{
5498 struct rtl8169_private *tp = netdev_priv(dev);
5499
5500 dev->mtu = new_mtu;
5501 netdev_update_features(dev);
5502 rtl_jumbo_config(tp);
5503
5504 /* Reportedly at least Asus X453MA truncates packets otherwise */
5505 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
5506 rtl_init_rxcfg(tp);
5507
5508 return 0;
5509}
5510
5511static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5512{
5513 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5514 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5515}
5516
5517static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5518{
5519 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5520
5521 /* Force memory writes to complete before releasing descriptor */
5522 dma_wmb();
5523
5524 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5525}
5526
5527static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5528 struct RxDesc *desc)
5529{
5530 struct device *d = tp_to_dev(tp);
5531 int node = dev_to_node(d);
5532 dma_addr_t mapping;
5533 struct page *data;
5534
5535 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5536 if (!data)
5537 return NULL;
5538
5539 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5540 if (unlikely(dma_mapping_error(d, mapping))) {
5541 if (net_ratelimit())
5542 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5543 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5544 return NULL;
5545 }
5546
5547 desc->addr = cpu_to_le64(mapping);
5548 rtl8169_mark_to_asic(desc);
5549
5550 return data;
5551}
5552
5553static void rtl8169_rx_clear(struct rtl8169_private *tp)
5554{
5555 unsigned int i;
5556
5557 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5558 dma_unmap_page(tp_to_dev(tp),
5559 le64_to_cpu(tp->RxDescArray[i].addr),
5560 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5561 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5562 tp->Rx_databuff[i] = NULL;
5563 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5564 }
5565}
5566
5567static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5568{
5569 desc->opts1 |= cpu_to_le32(RingEnd);
5570}
5571
5572static int rtl8169_rx_fill(struct rtl8169_private *tp)
5573{
5574 unsigned int i;
5575
5576 for (i = 0; i < NUM_RX_DESC; i++) {
5577 struct page *data;
5578
5579 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5580 if (!data) {
5581 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5582 goto err_out;
5583 }
5584 tp->Rx_databuff[i] = data;
5585 }
5586
5587 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5588 return 0;
5589
5590err_out:
5591 rtl8169_rx_clear(tp);
5592 return -ENOMEM;
5593}
5594
5595static int rtl8169_init_ring(struct rtl8169_private *tp)
5596{
5597 rtl8169_init_ring_indexes(tp);
5598
5599 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5600 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5601
5602 return rtl8169_rx_fill(tp);
5603}
5604
5605static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5606 struct TxDesc *desc)
5607{
5608 unsigned int len = tx_skb->len;
5609
5610 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5611
5612 desc->opts1 = 0x00;
5613 desc->opts2 = 0x00;
5614 desc->addr = 0x00;
5615 tx_skb->len = 0;
5616}
5617
5618static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5619 unsigned int n)
5620{
5621 unsigned int i;
5622
5623 for (i = 0; i < n; i++) {
5624 unsigned int entry = (start + i) % NUM_TX_DESC;
5625 struct ring_info *tx_skb = tp->tx_skb + entry;
5626 unsigned int len = tx_skb->len;
5627
5628 if (len) {
5629 struct sk_buff *skb = tx_skb->skb;
5630
5631 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5632 tp->TxDescArray + entry);
5633 if (skb) {
5634 dev_consume_skb_any(skb);
5635 tx_skb->skb = NULL;
5636 }
5637 }
5638 }
5639}
5640
5641static void rtl8169_tx_clear(struct rtl8169_private *tp)
5642{
5643 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5644 tp->cur_tx = tp->dirty_tx = 0;
5645 netdev_reset_queue(tp->dev);
5646}
5647
5648static void rtl_reset_work(struct rtl8169_private *tp)
5649{
5650 struct net_device *dev = tp->dev;
5651 int i;
5652
5653 napi_disable(&tp->napi);
5654 netif_stop_queue(dev);
5655 synchronize_rcu();
5656
5657 rtl8169_hw_reset(tp);
5658
5659 for (i = 0; i < NUM_RX_DESC; i++)
5660 rtl8169_mark_to_asic(tp->RxDescArray + i);
5661
5662 rtl8169_tx_clear(tp);
5663 rtl8169_init_ring_indexes(tp);
5664
5665 napi_enable(&tp->napi);
5666 rtl_hw_start(tp);
5667 netif_wake_queue(dev);
5668}
5669
5670static void rtl8169_tx_timeout(struct net_device *dev)
5671{
5672 struct rtl8169_private *tp = netdev_priv(dev);
5673
5674 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5675}
5676
5677static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5678{
5679 u32 status = opts0 | len;
5680
5681 if (entry == NUM_TX_DESC - 1)
5682 status |= RingEnd;
5683
5684 return cpu_to_le32(status);
5685}
5686
5687static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5688 u32 *opts)
5689{
5690 struct skb_shared_info *info = skb_shinfo(skb);
5691 unsigned int cur_frag, entry;
5692 struct TxDesc *uninitialized_var(txd);
5693 struct device *d = tp_to_dev(tp);
5694
5695 entry = tp->cur_tx;
5696 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5697 const skb_frag_t *frag = info->frags + cur_frag;
5698 dma_addr_t mapping;
5699 u32 len;
5700 void *addr;
5701
5702 entry = (entry + 1) % NUM_TX_DESC;
5703
5704 txd = tp->TxDescArray + entry;
5705 len = skb_frag_size(frag);
5706 addr = skb_frag_address(frag);
5707 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5708 if (unlikely(dma_mapping_error(d, mapping))) {
5709 if (net_ratelimit())
5710 netif_err(tp, drv, tp->dev,
5711 "Failed to map TX fragments DMA!\n");
5712 goto err_out;
5713 }
5714
5715 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5716 txd->opts2 = cpu_to_le32(opts[1]);
5717 txd->addr = cpu_to_le64(mapping);
5718
5719 tp->tx_skb[entry].len = len;
5720 }
5721
5722 if (cur_frag) {
5723 tp->tx_skb[entry].skb = skb;
5724 txd->opts1 |= cpu_to_le32(LastFrag);
5725 }
5726
5727 return cur_frag;
5728
5729err_out:
5730 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5731 return -EIO;
5732}
5733
5734static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5735{
5736 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5737}
5738
5739/* msdn_giant_send_check()
5740 * According to the document of microsoft, the TCP Pseudo Header excludes the
5741 * packet length for IPv6 TCP large packets.
5742 */
5743static int msdn_giant_send_check(struct sk_buff *skb)
5744{
5745 const struct ipv6hdr *ipv6h;
5746 struct tcphdr *th;
5747 int ret;
5748
5749 ret = skb_cow_head(skb, 0);
5750 if (ret)
5751 return ret;
5752
5753 ipv6h = ipv6_hdr(skb);
5754 th = tcp_hdr(skb);
5755
5756 th->check = 0;
5757 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5758
5759 return ret;
5760}
5761
5762static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5763{
5764 u32 mss = skb_shinfo(skb)->gso_size;
5765
5766 if (mss) {
5767 opts[0] |= TD_LSO;
5768 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5769 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5770 const struct iphdr *ip = ip_hdr(skb);
5771
5772 if (ip->protocol == IPPROTO_TCP)
5773 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5774 else if (ip->protocol == IPPROTO_UDP)
5775 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5776 else
5777 WARN_ON_ONCE(1);
5778 }
5779}
5780
5781static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5782 struct sk_buff *skb, u32 *opts)
5783{
5784 u32 transport_offset = (u32)skb_transport_offset(skb);
5785 u32 mss = skb_shinfo(skb)->gso_size;
5786
5787 if (mss) {
5788 switch (vlan_get_protocol(skb)) {
5789 case htons(ETH_P_IP):
5790 opts[0] |= TD1_GTSENV4;
5791 break;
5792
5793 case htons(ETH_P_IPV6):
5794 if (msdn_giant_send_check(skb))
5795 return false;
5796
5797 opts[0] |= TD1_GTSENV6;
5798 break;
5799
5800 default:
5801 WARN_ON_ONCE(1);
5802 break;
5803 }
5804
5805 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5806 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5807 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5808 u8 ip_protocol;
5809
5810 switch (vlan_get_protocol(skb)) {
5811 case htons(ETH_P_IP):
5812 opts[1] |= TD1_IPv4_CS;
5813 ip_protocol = ip_hdr(skb)->protocol;
5814 break;
5815
5816 case htons(ETH_P_IPV6):
5817 opts[1] |= TD1_IPv6_CS;
5818 ip_protocol = ipv6_hdr(skb)->nexthdr;
5819 break;
5820
5821 default:
5822 ip_protocol = IPPROTO_RAW;
5823 break;
5824 }
5825
5826 if (ip_protocol == IPPROTO_TCP)
5827 opts[1] |= TD1_TCP_CS;
5828 else if (ip_protocol == IPPROTO_UDP)
5829 opts[1] |= TD1_UDP_CS;
5830 else
5831 WARN_ON_ONCE(1);
5832
5833 opts[1] |= transport_offset << TCPHO_SHIFT;
5834 } else {
5835 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5836 /* eth_skb_pad would free the skb on error */
5837 return !__skb_put_padto(skb, ETH_ZLEN, false);
5838 }
5839
5840 return true;
5841}
5842
5843static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5844 unsigned int nr_frags)
5845{
5846 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5847
5848 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5849 return slots_avail > nr_frags;
5850}
5851
5852/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5853static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5854{
5855 switch (tp->mac_version) {
5856 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5857 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5858 return false;
5859 default:
5860 return true;
5861 }
5862}
5863
5864static void rtl8169_doorbell(struct rtl8169_private *tp)
5865{
5866 if (rtl_is_8125(tp))
5867 RTL_W16(tp, TxPoll_8125, BIT(0));
5868 else
5869 RTL_W8(tp, TxPoll, NPQ);
5870}
5871
5872static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5873 struct net_device *dev)
5874{
5875 struct rtl8169_private *tp = netdev_priv(dev);
5876 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5877 struct TxDesc *txd = tp->TxDescArray + entry;
5878 struct device *d = tp_to_dev(tp);
5879 dma_addr_t mapping;
5880 u32 opts[2], len;
5881 bool stop_queue;
5882 bool door_bell;
5883 int frags;
5884
5885 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5886 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5887 goto err_stop_0;
5888 }
5889
5890 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5891 goto err_stop_0;
5892
5893 opts[1] = rtl8169_tx_vlan_tag(skb);
5894 opts[0] = DescOwn;
5895
5896 if (rtl_chip_supports_csum_v2(tp)) {
5897 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5898 goto err_dma_0;
5899 } else {
5900 rtl8169_tso_csum_v1(skb, opts);
5901 }
5902
5903 len = skb_headlen(skb);
5904 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5905 if (unlikely(dma_mapping_error(d, mapping))) {
5906 if (net_ratelimit())
5907 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5908 goto err_dma_0;
5909 }
5910
5911 tp->tx_skb[entry].len = len;
5912 txd->addr = cpu_to_le64(mapping);
5913
5914 frags = rtl8169_xmit_frags(tp, skb, opts);
5915 if (frags < 0)
5916 goto err_dma_1;
5917 else if (frags)
5918 opts[0] |= FirstFrag;
5919 else {
5920 opts[0] |= FirstFrag | LastFrag;
5921 tp->tx_skb[entry].skb = skb;
5922 }
5923
5924 txd->opts2 = cpu_to_le32(opts[1]);
5925
5926 skb_tx_timestamp(skb);
5927
5928 /* Force memory writes to complete before releasing descriptor */
5929 dma_wmb();
5930
5931 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5932
5933 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5934
5935 /* Force all memory writes to complete before notifying device */
5936 wmb();
5937
5938 tp->cur_tx += frags + 1;
5939
5940 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5941 if (unlikely(stop_queue)) {
5942 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5943 * not miss a ring update when it notices a stopped queue.
5944 */
5945 smp_wmb();
5946 netif_stop_queue(dev);
5947 door_bell = true;
5948 }
5949
5950 if (door_bell)
5951 rtl8169_doorbell(tp);
5952
5953 if (unlikely(stop_queue)) {
5954 /* Sync with rtl_tx:
5955 * - publish queue status and cur_tx ring index (write barrier)
5956 * - refresh dirty_tx ring index (read barrier).
5957 * May the current thread have a pessimistic view of the ring
5958 * status and forget to wake up queue, a racing rtl_tx thread
5959 * can't.
5960 */
5961 smp_mb();
5962 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5963 netif_start_queue(dev);
5964 }
5965
5966 return NETDEV_TX_OK;
5967
5968err_dma_1:
5969 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5970err_dma_0:
5971 dev_kfree_skb_any(skb);
5972 dev->stats.tx_dropped++;
5973 return NETDEV_TX_OK;
5974
5975err_stop_0:
5976 netif_stop_queue(dev);
5977 dev->stats.tx_dropped++;
5978 return NETDEV_TX_BUSY;
5979}
5980
5981static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5982 struct net_device *dev,
5983 netdev_features_t features)
5984{
5985 int transport_offset = skb_transport_offset(skb);
5986 struct rtl8169_private *tp = netdev_priv(dev);
5987
5988 if (skb_is_gso(skb)) {
5989 if (transport_offset > GTTCPHO_MAX &&
5990 rtl_chip_supports_csum_v2(tp))
5991 features &= ~NETIF_F_ALL_TSO;
5992 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5993 if (skb->len < ETH_ZLEN) {
5994 switch (tp->mac_version) {
5995 case RTL_GIGA_MAC_VER_11:
5996 case RTL_GIGA_MAC_VER_12:
5997 case RTL_GIGA_MAC_VER_17:
5998 case RTL_GIGA_MAC_VER_34:
5999 features &= ~NETIF_F_CSUM_MASK;
6000 break;
6001 default:
6002 break;
6003 }
6004 }
6005
6006 if (transport_offset > TCPHO_MAX &&
6007 rtl_chip_supports_csum_v2(tp))
6008 features &= ~NETIF_F_CSUM_MASK;
6009 }
6010
6011 return vlan_features_check(skb, features);
6012}
6013
6014static void rtl8169_pcierr_interrupt(struct net_device *dev)
6015{
6016 struct rtl8169_private *tp = netdev_priv(dev);
6017 struct pci_dev *pdev = tp->pci_dev;
6018 u16 pci_status, pci_cmd;
6019
6020 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6021 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6022
6023 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6024 pci_cmd, pci_status);
6025
6026 /*
6027 * The recovery sequence below admits a very elaborated explanation:
6028 * - it seems to work;
6029 * - I did not see what else could be done;
6030 * - it makes iop3xx happy.
6031 *
6032 * Feel free to adjust to your needs.
6033 */
6034 if (pdev->broken_parity_status)
6035 pci_cmd &= ~PCI_COMMAND_PARITY;
6036 else
6037 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6038
6039 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6040
6041 pci_write_config_word(pdev, PCI_STATUS,
6042 pci_status & (PCI_STATUS_DETECTED_PARITY |
6043 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6044 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6045
6046 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6047}
6048
6049static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6050 int budget)
6051{
6052 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6053
6054 dirty_tx = tp->dirty_tx;
6055 smp_rmb();
6056 tx_left = tp->cur_tx - dirty_tx;
6057
6058 while (tx_left > 0) {
6059 unsigned int entry = dirty_tx % NUM_TX_DESC;
6060 struct ring_info *tx_skb = tp->tx_skb + entry;
6061 u32 status;
6062
6063 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
6064 if (status & DescOwn)
6065 break;
6066
6067 /* This barrier is needed to keep us from reading
6068 * any other fields out of the Tx descriptor until
6069 * we know the status of DescOwn
6070 */
6071 dma_rmb();
6072
6073 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6074 tp->TxDescArray + entry);
6075 if (tx_skb->skb) {
6076 pkts_compl++;
6077 bytes_compl += tx_skb->skb->len;
6078 napi_consume_skb(tx_skb->skb, budget);
6079 tx_skb->skb = NULL;
6080 }
6081 dirty_tx++;
6082 tx_left--;
6083 }
6084
6085 if (tp->dirty_tx != dirty_tx) {
6086 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6087
6088 u64_stats_update_begin(&tp->tx_stats.syncp);
6089 tp->tx_stats.packets += pkts_compl;
6090 tp->tx_stats.bytes += bytes_compl;
6091 u64_stats_update_end(&tp->tx_stats.syncp);
6092
6093 tp->dirty_tx = dirty_tx;
6094 /* Sync with rtl8169_start_xmit:
6095 * - publish dirty_tx ring index (write barrier)
6096 * - refresh cur_tx ring index and queue status (read barrier)
6097 * May the current thread miss the stopped queue condition,
6098 * a racing xmit thread can only have a right view of the
6099 * ring status.
6100 */
6101 smp_mb();
6102 if (netif_queue_stopped(dev) &&
6103 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6104 netif_wake_queue(dev);
6105 }
6106 /*
6107 * 8168 hack: TxPoll requests are lost when the Tx packets are
6108 * too close. Let's kick an extra TxPoll request when a burst
6109 * of start_xmit activity is detected (if it is not detected,
6110 * it is slow enough). -- FR
6111 */
6112 if (tp->cur_tx != dirty_tx)
6113 rtl8169_doorbell(tp);
6114 }
6115}
6116
6117static inline int rtl8169_fragmented_frame(u32 status)
6118{
6119 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6120}
6121
6122static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6123{
6124 u32 status = opts1 & RxProtoMask;
6125
6126 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6127 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6128 skb->ip_summed = CHECKSUM_UNNECESSARY;
6129 else
6130 skb_checksum_none_assert(skb);
6131}
6132
6133static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6134{
6135 unsigned int cur_rx, rx_left;
6136 unsigned int count;
6137
6138 cur_rx = tp->cur_rx;
6139
6140 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6141 unsigned int entry = cur_rx % NUM_RX_DESC;
6142 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
6143 struct RxDesc *desc = tp->RxDescArray + entry;
6144 u32 status;
6145
6146 status = le32_to_cpu(READ_ONCE(desc->opts1));
6147 if (status & DescOwn)
6148 break;
6149
6150 /* This barrier is needed to keep us from reading
6151 * any other fields out of the Rx descriptor until
6152 * we know the status of DescOwn
6153 */
6154 dma_rmb();
6155
6156 if (unlikely(status & RxRES)) {
6157 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6158 status);
6159 dev->stats.rx_errors++;
6160 if (status & (RxRWT | RxRUNT))
6161 dev->stats.rx_length_errors++;
6162 if (status & RxCRC)
6163 dev->stats.rx_crc_errors++;
6164 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6165 dev->features & NETIF_F_RXALL) {
6166 goto process_pkt;
6167 }
6168 } else {
6169 unsigned int pkt_size;
6170 struct sk_buff *skb;
6171
6172process_pkt:
6173 pkt_size = status & GENMASK(13, 0);
6174 if (likely(!(dev->features & NETIF_F_RXFCS)))
6175 pkt_size -= ETH_FCS_LEN;
6176 /*
6177 * The driver does not support incoming fragmented
6178 * frames. They are seen as a symptom of over-mtu
6179 * sized frames.
6180 */
6181 if (unlikely(rtl8169_fragmented_frame(status))) {
6182 dev->stats.rx_dropped++;
6183 dev->stats.rx_length_errors++;
6184 goto release_descriptor;
6185 }
6186
6187 skb = napi_alloc_skb(&tp->napi, pkt_size);
6188 if (unlikely(!skb)) {
6189 dev->stats.rx_dropped++;
6190 goto release_descriptor;
6191 }
6192
6193 dma_sync_single_for_cpu(tp_to_dev(tp),
6194 le64_to_cpu(desc->addr),
6195 pkt_size, DMA_FROM_DEVICE);
6196 prefetch(rx_buf);
6197 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
6198 skb->tail += pkt_size;
6199 skb->len = pkt_size;
6200
6201 dma_sync_single_for_device(tp_to_dev(tp),
6202 le64_to_cpu(desc->addr),
6203 pkt_size, DMA_FROM_DEVICE);
6204
6205 rtl8169_rx_csum(skb, status);
6206 skb->protocol = eth_type_trans(skb, dev);
6207
6208 rtl8169_rx_vlan_tag(desc, skb);
6209
6210 if (skb->pkt_type == PACKET_MULTICAST)
6211 dev->stats.multicast++;
6212
6213 napi_gro_receive(&tp->napi, skb);
6214
6215 u64_stats_update_begin(&tp->rx_stats.syncp);
6216 tp->rx_stats.packets++;
6217 tp->rx_stats.bytes += pkt_size;
6218 u64_stats_update_end(&tp->rx_stats.syncp);
6219 }
6220release_descriptor:
6221 desc->opts2 = 0;
6222 rtl8169_mark_to_asic(desc);
6223 }
6224
6225 count = cur_rx - tp->cur_rx;
6226 tp->cur_rx = cur_rx;
6227
6228 return count;
6229}
6230
6231static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6232{
6233 struct rtl8169_private *tp = dev_instance;
6234 u32 status = rtl_get_events(tp);
6235
6236 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6237 !(status & tp->irq_mask))
6238 return IRQ_NONE;
6239
6240 /* At least RTL8168fp may unexpectedly set the SYSErr bit */
6241 if (unlikely(status & SYSErr &&
6242 tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
6243 rtl8169_pcierr_interrupt(tp->dev);
6244 goto out;
6245 }
6246
6247 if (status & LinkChg)
6248 phy_mac_interrupt(tp->phydev);
6249
6250 if (unlikely(status & RxFIFOOver &&
6251 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6252 netif_stop_queue(tp->dev);
6253 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6254 }
6255
6256 rtl_irq_disable(tp);
6257 napi_schedule(&tp->napi);
6258out:
6259 rtl_ack_events(tp, status);
6260
6261 return IRQ_HANDLED;
6262}
6263
6264static void rtl_task(struct work_struct *work)
6265{
6266 static const struct {
6267 int bitnr;
6268 void (*action)(struct rtl8169_private *);
6269 } rtl_work[] = {
6270 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6271 };
6272 struct rtl8169_private *tp =
6273 container_of(work, struct rtl8169_private, wk.work);
6274 struct net_device *dev = tp->dev;
6275 int i;
6276
6277 rtl_lock_work(tp);
6278
6279 if (!netif_running(dev) ||
6280 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6281 goto out_unlock;
6282
6283 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6284 bool pending;
6285
6286 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6287 if (pending)
6288 rtl_work[i].action(tp);
6289 }
6290
6291out_unlock:
6292 rtl_unlock_work(tp);
6293}
6294
6295static int rtl8169_poll(struct napi_struct *napi, int budget)
6296{
6297 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6298 struct net_device *dev = tp->dev;
6299 int work_done;
6300
6301 work_done = rtl_rx(dev, tp, (u32) budget);
6302
6303 rtl_tx(dev, tp, budget);
6304
6305 if (work_done < budget) {
6306 napi_complete_done(napi, work_done);
6307 rtl_irq_enable(tp);
6308 }
6309
6310 return work_done;
6311}
6312
6313static void rtl8169_rx_missed(struct net_device *dev)
6314{
6315 struct rtl8169_private *tp = netdev_priv(dev);
6316
6317 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6318 return;
6319
6320 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6321 RTL_W32(tp, RxMissed, 0);
6322}
6323
6324static void r8169_phylink_handler(struct net_device *ndev)
6325{
6326 struct rtl8169_private *tp = netdev_priv(ndev);
6327 struct device *d = tp_to_dev(tp);
6328
6329 if (netif_carrier_ok(ndev)) {
6330 rtl_link_chg_patch(tp);
6331 pm_request_resume(d);
6332 netif_wake_queue(tp->dev);
6333 } else {
6334 /* In few cases rx is broken after link-down otherwise */
6335 if (rtl_is_8125(tp))
6336 rtl_reset_work(tp);
6337 pm_runtime_idle(d);
6338 }
6339
6340 if (net_ratelimit())
6341 phy_print_status(tp->phydev);
6342}
6343
6344static int r8169_phy_connect(struct rtl8169_private *tp)
6345{
6346 struct phy_device *phydev = tp->phydev;
6347 phy_interface_t phy_mode;
6348 int ret;
6349
6350 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6351 PHY_INTERFACE_MODE_MII;
6352
6353 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6354 phy_mode);
6355 if (ret)
6356 return ret;
6357
6358 if (!tp->supports_gmii)
6359 phy_set_max_speed(phydev, SPEED_100);
6360
6361 phy_attached_info(phydev);
6362
6363 return 0;
6364}
6365
6366static void rtl8169_down(struct net_device *dev)
6367{
6368 struct rtl8169_private *tp = netdev_priv(dev);
6369
6370 phy_stop(tp->phydev);
6371
6372 napi_disable(&tp->napi);
6373 netif_stop_queue(dev);
6374
6375 rtl8169_hw_reset(tp);
6376 /*
6377 * At this point device interrupts can not be enabled in any function,
6378 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6379 * and napi is disabled (rtl8169_poll).
6380 */
6381 rtl8169_rx_missed(dev);
6382
6383 /* Give a racing hard_start_xmit a few cycles to complete. */
6384 synchronize_rcu();
6385
6386 rtl8169_tx_clear(tp);
6387
6388 rtl8169_rx_clear(tp);
6389
6390 rtl_pll_power_down(tp);
6391}
6392
6393static int rtl8169_close(struct net_device *dev)
6394{
6395 struct rtl8169_private *tp = netdev_priv(dev);
6396 struct pci_dev *pdev = tp->pci_dev;
6397
6398 pm_runtime_get_sync(&pdev->dev);
6399
6400 /* Update counters before going down */
6401 rtl8169_update_counters(tp);
6402
6403 rtl_lock_work(tp);
6404 /* Clear all task flags */
6405 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6406
6407 rtl8169_down(dev);
6408 rtl_unlock_work(tp);
6409
6410 cancel_work_sync(&tp->wk.work);
6411
6412 free_irq(pci_irq_vector(pdev, 0), tp);
6413
6414 phy_disconnect(tp->phydev);
6415
6416 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6417 tp->RxPhyAddr);
6418 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6419 tp->TxPhyAddr);
6420 tp->TxDescArray = NULL;
6421 tp->RxDescArray = NULL;
6422
6423 pm_runtime_put_sync(&pdev->dev);
6424
6425 return 0;
6426}
6427
6428#ifdef CONFIG_NET_POLL_CONTROLLER
6429static void rtl8169_netpoll(struct net_device *dev)
6430{
6431 struct rtl8169_private *tp = netdev_priv(dev);
6432
6433 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6434}
6435#endif
6436
6437static int rtl_open(struct net_device *dev)
6438{
6439 struct rtl8169_private *tp = netdev_priv(dev);
6440 struct pci_dev *pdev = tp->pci_dev;
6441 int retval = -ENOMEM;
6442
6443 pm_runtime_get_sync(&pdev->dev);
6444
6445 /*
6446 * Rx and Tx descriptors needs 256 bytes alignment.
6447 * dma_alloc_coherent provides more.
6448 */
6449 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6450 &tp->TxPhyAddr, GFP_KERNEL);
6451 if (!tp->TxDescArray)
6452 goto err_pm_runtime_put;
6453
6454 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6455 &tp->RxPhyAddr, GFP_KERNEL);
6456 if (!tp->RxDescArray)
6457 goto err_free_tx_0;
6458
6459 retval = rtl8169_init_ring(tp);
6460 if (retval < 0)
6461 goto err_free_rx_1;
6462
6463 rtl_request_firmware(tp);
6464
6465 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
6466 IRQF_SHARED, dev->name, tp);
6467 if (retval < 0)
6468 goto err_release_fw_2;
6469
6470 retval = r8169_phy_connect(tp);
6471 if (retval)
6472 goto err_free_irq;
6473
6474 rtl_lock_work(tp);
6475
6476 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6477
6478 napi_enable(&tp->napi);
6479
6480 rtl8169_init_phy(dev, tp);
6481
6482 rtl_pll_power_up(tp);
6483
6484 rtl_hw_start(tp);
6485
6486 if (!rtl8169_init_counter_offsets(tp))
6487 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6488
6489 phy_start(tp->phydev);
6490 netif_start_queue(dev);
6491
6492 rtl_unlock_work(tp);
6493
6494 pm_runtime_put_sync(&pdev->dev);
6495out:
6496 return retval;
6497
6498err_free_irq:
6499 free_irq(pci_irq_vector(pdev, 0), tp);
6500err_release_fw_2:
6501 rtl_release_firmware(tp);
6502 rtl8169_rx_clear(tp);
6503err_free_rx_1:
6504 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6505 tp->RxPhyAddr);
6506 tp->RxDescArray = NULL;
6507err_free_tx_0:
6508 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6509 tp->TxPhyAddr);
6510 tp->TxDescArray = NULL;
6511err_pm_runtime_put:
6512 pm_runtime_put_noidle(&pdev->dev);
6513 goto out;
6514}
6515
6516static void
6517rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6518{
6519 struct rtl8169_private *tp = netdev_priv(dev);
6520 struct pci_dev *pdev = tp->pci_dev;
6521 struct rtl8169_counters *counters = tp->counters;
6522 unsigned int start;
6523
6524 pm_runtime_get_noresume(&pdev->dev);
6525
6526 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6527 rtl8169_rx_missed(dev);
6528
6529 do {
6530 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6531 stats->rx_packets = tp->rx_stats.packets;
6532 stats->rx_bytes = tp->rx_stats.bytes;
6533 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6534
6535 do {
6536 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6537 stats->tx_packets = tp->tx_stats.packets;
6538 stats->tx_bytes = tp->tx_stats.bytes;
6539 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6540
6541 stats->rx_dropped = dev->stats.rx_dropped;
6542 stats->tx_dropped = dev->stats.tx_dropped;
6543 stats->rx_length_errors = dev->stats.rx_length_errors;
6544 stats->rx_errors = dev->stats.rx_errors;
6545 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6546 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6547 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6548 stats->multicast = dev->stats.multicast;
6549
6550 /*
6551 * Fetch additional counter values missing in stats collected by driver
6552 * from tally counters.
6553 */
6554 if (pm_runtime_active(&pdev->dev))
6555 rtl8169_update_counters(tp);
6556
6557 /*
6558 * Subtract values fetched during initalization.
6559 * See rtl8169_init_counter_offsets for a description why we do that.
6560 */
6561 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6562 le64_to_cpu(tp->tc_offset.tx_errors);
6563 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6564 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6565 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6566 le16_to_cpu(tp->tc_offset.tx_aborted);
6567
6568 pm_runtime_put_noidle(&pdev->dev);
6569}
6570
6571static void rtl8169_net_suspend(struct net_device *dev)
6572{
6573 struct rtl8169_private *tp = netdev_priv(dev);
6574
6575 if (!netif_running(dev))
6576 return;
6577
6578 phy_stop(tp->phydev);
6579 netif_device_detach(dev);
6580
6581 rtl_lock_work(tp);
6582 napi_disable(&tp->napi);
6583 /* Clear all task flags */
6584 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6585
6586 rtl_unlock_work(tp);
6587
6588 rtl_pll_power_down(tp);
6589}
6590
6591#ifdef CONFIG_PM
6592
6593static int rtl8169_suspend(struct device *device)
6594{
6595 struct net_device *dev = dev_get_drvdata(device);
6596 struct rtl8169_private *tp = netdev_priv(dev);
6597
6598 rtl8169_net_suspend(dev);
6599 clk_disable_unprepare(tp->clk);
6600
6601 return 0;
6602}
6603
6604static void __rtl8169_resume(struct net_device *dev)
6605{
6606 struct rtl8169_private *tp = netdev_priv(dev);
6607
6608 netif_device_attach(dev);
6609
6610 rtl_pll_power_up(tp);
6611 rtl8169_init_phy(dev, tp);
6612
6613 phy_start(tp->phydev);
6614
6615 rtl_lock_work(tp);
6616 napi_enable(&tp->napi);
6617 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6618 rtl_reset_work(tp);
6619 rtl_unlock_work(tp);
6620}
6621
6622static int rtl8169_resume(struct device *device)
6623{
6624 struct net_device *dev = dev_get_drvdata(device);
6625 struct rtl8169_private *tp = netdev_priv(dev);
6626
6627 rtl_rar_set(tp, dev->dev_addr);
6628
6629 clk_prepare_enable(tp->clk);
6630
6631 if (netif_running(dev))
6632 __rtl8169_resume(dev);
6633
6634 return 0;
6635}
6636
6637static int rtl8169_runtime_suspend(struct device *device)
6638{
6639 struct net_device *dev = dev_get_drvdata(device);
6640 struct rtl8169_private *tp = netdev_priv(dev);
6641
6642 if (!tp->TxDescArray)
6643 return 0;
6644
6645 rtl_lock_work(tp);
6646 __rtl8169_set_wol(tp, WAKE_ANY);
6647 rtl_unlock_work(tp);
6648
6649 rtl8169_net_suspend(dev);
6650
6651 /* Update counters before going runtime suspend */
6652 rtl8169_rx_missed(dev);
6653 rtl8169_update_counters(tp);
6654
6655 return 0;
6656}
6657
6658static int rtl8169_runtime_resume(struct device *device)
6659{
6660 struct net_device *dev = dev_get_drvdata(device);
6661 struct rtl8169_private *tp = netdev_priv(dev);
6662
6663 rtl_rar_set(tp, dev->dev_addr);
6664
6665 if (!tp->TxDescArray)
6666 return 0;
6667
6668 rtl_lock_work(tp);
6669 __rtl8169_set_wol(tp, tp->saved_wolopts);
6670 rtl_unlock_work(tp);
6671
6672 __rtl8169_resume(dev);
6673
6674 return 0;
6675}
6676
6677static int rtl8169_runtime_idle(struct device *device)
6678{
6679 struct net_device *dev = dev_get_drvdata(device);
6680
6681 if (!netif_running(dev) || !netif_carrier_ok(dev))
6682 pm_schedule_suspend(device, 10000);
6683
6684 return -EBUSY;
6685}
6686
6687static const struct dev_pm_ops rtl8169_pm_ops = {
6688 .suspend = rtl8169_suspend,
6689 .resume = rtl8169_resume,
6690 .freeze = rtl8169_suspend,
6691 .thaw = rtl8169_resume,
6692 .poweroff = rtl8169_suspend,
6693 .restore = rtl8169_resume,
6694 .runtime_suspend = rtl8169_runtime_suspend,
6695 .runtime_resume = rtl8169_runtime_resume,
6696 .runtime_idle = rtl8169_runtime_idle,
6697};
6698
6699#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6700
6701#else /* !CONFIG_PM */
6702
6703#define RTL8169_PM_OPS NULL
6704
6705#endif /* !CONFIG_PM */
6706
6707static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6708{
6709 /* WoL fails with 8168b when the receiver is disabled. */
6710 switch (tp->mac_version) {
6711 case RTL_GIGA_MAC_VER_11:
6712 case RTL_GIGA_MAC_VER_12:
6713 case RTL_GIGA_MAC_VER_17:
6714 pci_clear_master(tp->pci_dev);
6715
6716 RTL_W8(tp, ChipCmd, CmdRxEnb);
6717 /* PCI commit */
6718 RTL_R8(tp, ChipCmd);
6719 break;
6720 default:
6721 break;
6722 }
6723}
6724
6725static void rtl_shutdown(struct pci_dev *pdev)
6726{
6727 struct net_device *dev = pci_get_drvdata(pdev);
6728 struct rtl8169_private *tp = netdev_priv(dev);
6729
6730 rtl8169_net_suspend(dev);
6731
6732 /* Restore original MAC address */
6733 rtl_rar_set(tp, dev->perm_addr);
6734
6735 rtl8169_hw_reset(tp);
6736
6737 if (system_state == SYSTEM_POWER_OFF) {
6738 if (tp->saved_wolopts) {
6739 rtl_wol_suspend_quirk(tp);
6740 rtl_wol_shutdown_quirk(tp);
6741 }
6742
6743 pci_wake_from_d3(pdev, true);
6744 pci_set_power_state(pdev, PCI_D3hot);
6745 }
6746}
6747
6748static void rtl_remove_one(struct pci_dev *pdev)
6749{
6750 struct net_device *dev = pci_get_drvdata(pdev);
6751 struct rtl8169_private *tp = netdev_priv(dev);
6752
6753 if (r8168_check_dash(tp))
6754 rtl8168_driver_stop(tp);
6755
6756 netif_napi_del(&tp->napi);
6757
6758 unregister_netdev(dev);
6759 mdiobus_unregister(tp->phydev->mdio.bus);
6760
6761 rtl_release_firmware(tp);
6762
6763 if (pci_dev_run_wake(pdev))
6764 pm_runtime_get_noresume(&pdev->dev);
6765
6766 /* restore original MAC address */
6767 rtl_rar_set(tp, dev->perm_addr);
6768}
6769
6770static const struct net_device_ops rtl_netdev_ops = {
6771 .ndo_open = rtl_open,
6772 .ndo_stop = rtl8169_close,
6773 .ndo_get_stats64 = rtl8169_get_stats64,
6774 .ndo_start_xmit = rtl8169_start_xmit,
6775 .ndo_features_check = rtl8169_features_check,
6776 .ndo_tx_timeout = rtl8169_tx_timeout,
6777 .ndo_validate_addr = eth_validate_addr,
6778 .ndo_change_mtu = rtl8169_change_mtu,
6779 .ndo_fix_features = rtl8169_fix_features,
6780 .ndo_set_features = rtl8169_set_features,
6781 .ndo_set_mac_address = rtl_set_mac_address,
6782 .ndo_do_ioctl = rtl8169_ioctl,
6783 .ndo_set_rx_mode = rtl_set_rx_mode,
6784#ifdef CONFIG_NET_POLL_CONTROLLER
6785 .ndo_poll_controller = rtl8169_netpoll,
6786#endif
6787
6788};
6789
6790static void rtl_set_irq_mask(struct rtl8169_private *tp)
6791{
6792 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6793
6794 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6795 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6796 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6797 /* special workaround needed */
6798 tp->irq_mask |= RxFIFOOver;
6799 else
6800 tp->irq_mask |= RxOverflow;
6801}
6802
6803static int rtl_alloc_irq(struct rtl8169_private *tp)
6804{
6805 unsigned int flags;
6806
6807 switch (tp->mac_version) {
6808 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6809 rtl_unlock_config_regs(tp);
6810 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6811 rtl_lock_config_regs(tp);
6812 /* fall through */
6813 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
6814 flags = PCI_IRQ_LEGACY;
6815 break;
6816 default:
6817 flags = PCI_IRQ_ALL_TYPES;
6818 break;
6819 }
6820
6821 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6822}
6823
6824static void rtl_read_mac_address(struct rtl8169_private *tp,
6825 u8 mac_addr[ETH_ALEN])
6826{
6827 /* Get MAC address */
6828 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6829 u32 value = rtl_eri_read(tp, 0xe0);
6830
6831 mac_addr[0] = (value >> 0) & 0xff;
6832 mac_addr[1] = (value >> 8) & 0xff;
6833 mac_addr[2] = (value >> 16) & 0xff;
6834 mac_addr[3] = (value >> 24) & 0xff;
6835
6836 value = rtl_eri_read(tp, 0xe4);
6837 mac_addr[4] = (value >> 0) & 0xff;
6838 mac_addr[5] = (value >> 8) & 0xff;
6839 } else if (rtl_is_8125(tp)) {
6840 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
6841 }
6842}
6843
6844DECLARE_RTL_COND(rtl_link_list_ready_cond)
6845{
6846 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6847}
6848
6849DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6850{
6851 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6852}
6853
6854static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6855{
6856 struct rtl8169_private *tp = mii_bus->priv;
6857
6858 if (phyaddr > 0)
6859 return -ENODEV;
6860
6861 return rtl_readphy(tp, phyreg);
6862}
6863
6864static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6865 int phyreg, u16 val)
6866{
6867 struct rtl8169_private *tp = mii_bus->priv;
6868
6869 if (phyaddr > 0)
6870 return -ENODEV;
6871
6872 rtl_writephy(tp, phyreg, val);
6873
6874 return 0;
6875}
6876
6877static int r8169_mdio_register(struct rtl8169_private *tp)
6878{
6879 struct pci_dev *pdev = tp->pci_dev;
6880 struct mii_bus *new_bus;
6881 int ret;
6882
6883 /* On some boards with this chip version the BIOS is buggy and misses
6884 * to reset the PHY page selector. This results in the PHY ID read
6885 * accessing registers on a different page, returning a more or
6886 * less random value. Fix this by resetting the page selector first.
6887 */
6888 if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
6889 tp->mac_version == RTL_GIGA_MAC_VER_26)
6890 r8169_mdio_write(tp, 0x1f, 0);
6891
6892 new_bus = devm_mdiobus_alloc(&pdev->dev);
6893 if (!new_bus)
6894 return -ENOMEM;
6895
6896 new_bus->name = "r8169";
6897 new_bus->priv = tp;
6898 new_bus->parent = &pdev->dev;
6899 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6900 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
6901 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
6902
6903 new_bus->read = r8169_mdio_read_reg;
6904 new_bus->write = r8169_mdio_write_reg;
6905
6906 ret = mdiobus_register(new_bus);
6907 if (ret)
6908 return ret;
6909
6910 tp->phydev = mdiobus_get_phy(new_bus, 0);
6911 if (!tp->phydev) {
6912 mdiobus_unregister(new_bus);
6913 return -ENODEV;
6914 } else if (!tp->phydev->drv) {
6915 /* Most chip versions fail with the genphy driver.
6916 * Therefore ensure that the dedicated PHY driver is loaded.
6917 */
6918 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
6919 mdiobus_unregister(new_bus);
6920 return -EUNATCH;
6921 }
6922
6923 /* PHY will be woken up in rtl_open() */
6924 phy_suspend(tp->phydev);
6925
6926 return 0;
6927}
6928
6929static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6930{
6931 tp->ocp_base = OCP_STD_PHY_BASE;
6932
6933 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6934
6935 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6936 return;
6937
6938 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6939 return;
6940
6941 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6942 msleep(1);
6943 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6944
6945 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6946
6947 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6948 return;
6949
6950 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6951
6952 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6953}
6954
6955static void rtl_hw_init_8125(struct rtl8169_private *tp)
6956{
6957 tp->ocp_base = OCP_STD_PHY_BASE;
6958
6959 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6960
6961 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6962 return;
6963
6964 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6965 msleep(1);
6966 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6967
6968 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6969
6970 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6971 return;
6972
6973 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6974 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6975 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6976
6977 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6978}
6979
6980static void rtl_hw_initialize(struct rtl8169_private *tp)
6981{
6982 switch (tp->mac_version) {
6983 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6984 rtl8168ep_stop_cmac(tp);
6985 /* fall through */
6986 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6987 rtl_hw_init_8168g(tp);
6988 break;
6989 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6990 rtl_hw_init_8125(tp);
6991 break;
6992 default:
6993 break;
6994 }
6995}
6996
6997static int rtl_jumbo_max(struct rtl8169_private *tp)
6998{
6999 /* Non-GBit versions don't support jumbo frames */
7000 if (!tp->supports_gmii)
7001 return JUMBO_1K;
7002
7003 switch (tp->mac_version) {
7004 /* RTL8169 */
7005 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7006 return JUMBO_7K;
7007 /* RTL8168b */
7008 case RTL_GIGA_MAC_VER_11:
7009 case RTL_GIGA_MAC_VER_12:
7010 case RTL_GIGA_MAC_VER_17:
7011 return JUMBO_4K;
7012 /* RTL8168c */
7013 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7014 return JUMBO_6K;
7015 default:
7016 return JUMBO_9K;
7017 }
7018}
7019
7020static void rtl_disable_clk(void *data)
7021{
7022 clk_disable_unprepare(data);
7023}
7024
7025static int rtl_get_ether_clk(struct rtl8169_private *tp)
7026{
7027 struct device *d = tp_to_dev(tp);
7028 struct clk *clk;
7029 int rc;
7030
7031 clk = devm_clk_get(d, "ether_clk");
7032 if (IS_ERR(clk)) {
7033 rc = PTR_ERR(clk);
7034 if (rc == -ENOENT)
7035 /* clk-core allows NULL (for suspend / resume) */
7036 rc = 0;
7037 else if (rc != -EPROBE_DEFER)
7038 dev_err(d, "failed to get clk: %d\n", rc);
7039 } else {
7040 tp->clk = clk;
7041 rc = clk_prepare_enable(clk);
7042 if (rc)
7043 dev_err(d, "failed to enable clk: %d\n", rc);
7044 else
7045 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7046 }
7047
7048 return rc;
7049}
7050
7051static void rtl_init_mac_address(struct rtl8169_private *tp)
7052{
7053 struct net_device *dev = tp->dev;
7054 u8 *mac_addr = dev->dev_addr;
7055 int rc;
7056
7057 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
7058 if (!rc)
7059 goto done;
7060
7061 rtl_read_mac_address(tp, mac_addr);
7062 if (is_valid_ether_addr(mac_addr))
7063 goto done;
7064
7065 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
7066 if (is_valid_ether_addr(mac_addr))
7067 goto done;
7068
7069 eth_hw_addr_random(dev);
7070 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
7071done:
7072 rtl_rar_set(tp, mac_addr);
7073}
7074
7075static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7076{
7077 struct rtl8169_private *tp;
7078 struct net_device *dev;
7079 int chipset, region;
7080 int jumbo_max, rc;
7081
7082 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7083 if (!dev)
7084 return -ENOMEM;
7085
7086 SET_NETDEV_DEV(dev, &pdev->dev);
7087 dev->netdev_ops = &rtl_netdev_ops;
7088 tp = netdev_priv(dev);
7089 tp->dev = dev;
7090 tp->pci_dev = pdev;
7091 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7092 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
7093 tp->eee_adv = -1;
7094
7095 /* Get the *optional* external "ether_clk" used on some boards */
7096 rc = rtl_get_ether_clk(tp);
7097 if (rc)
7098 return rc;
7099
7100 /* Disable ASPM completely as that cause random device stop working
7101 * problems as well as full system hangs for some PCIe devices users.
7102 */
7103 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
7104 PCIE_LINK_STATE_L1);
7105 tp->aspm_manageable = !rc;
7106
7107 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7108 rc = pcim_enable_device(pdev);
7109 if (rc < 0) {
7110 dev_err(&pdev->dev, "enable failure\n");
7111 return rc;
7112 }
7113
7114 if (pcim_set_mwi(pdev) < 0)
7115 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7116
7117 /* use first MMIO region */
7118 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7119 if (region < 0) {
7120 dev_err(&pdev->dev, "no MMIO resource found\n");
7121 return -ENODEV;
7122 }
7123
7124 /* check for weird/broken PCI region reporting */
7125 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7126 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7127 return -ENODEV;
7128 }
7129
7130 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7131 if (rc < 0) {
7132 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7133 return rc;
7134 }
7135
7136 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7137
7138 /* Identify chip attached to board */
7139 rtl8169_get_mac_version(tp);
7140 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7141 return -ENODEV;
7142
7143 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7144
7145 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7146 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
7147 dev->features |= NETIF_F_HIGHDMA;
7148
7149 rtl_init_rxcfg(tp);
7150
7151 rtl8169_irq_mask_and_ack(tp);
7152
7153 rtl_hw_initialize(tp);
7154
7155 rtl_hw_reset(tp);
7156
7157 pci_set_master(pdev);
7158
7159 chipset = tp->mac_version;
7160
7161 rc = rtl_alloc_irq(tp);
7162 if (rc < 0) {
7163 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7164 return rc;
7165 }
7166
7167 mutex_init(&tp->wk.mutex);
7168 INIT_WORK(&tp->wk.work, rtl_task);
7169 u64_stats_init(&tp->rx_stats.syncp);
7170 u64_stats_init(&tp->tx_stats.syncp);
7171
7172 rtl_init_mac_address(tp);
7173
7174 dev->ethtool_ops = &rtl8169_ethtool_ops;
7175
7176 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7177
7178 dev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7179 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7180 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7181 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7182 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7183 NETIF_F_HIGHDMA;
7184 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7185
7186 tp->cp_cmd |= RxChkSum;
7187 /* RTL8125 uses register RxConfig for VLAN offloading config */
7188 if (!rtl_is_8125(tp))
7189 tp->cp_cmd |= RxVlan;
7190 /*
7191 * Pretend we are using VLANs; This bypasses a nasty bug where
7192 * Interrupts stop flowing on high load on 8110SCd controllers.
7193 */
7194 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7195 /* Disallow toggling */
7196 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7197
7198 if (rtl_chip_supports_csum_v2(tp)) {
7199 dev->hw_features |= NETIF_F_IPV6_CSUM;
7200 dev->features |= NETIF_F_IPV6_CSUM;
7201 }
7202
7203 /* There has been a number of reports that using SG/TSO results in
7204 * tx timeouts. However for a lot of people SG/TSO works fine.
7205 * Therefore disable both features by default, but allow users to
7206 * enable them. Use at own risk!
7207 */
7208 if (rtl_chip_supports_csum_v2(tp)) {
7209 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
7210 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7211 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7212 } else {
7213 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
7214 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7215 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7216 }
7217
7218 dev->hw_features |= NETIF_F_RXALL;
7219 dev->hw_features |= NETIF_F_RXFCS;
7220
7221 /* MTU range: 60 - hw-specific max */
7222 dev->min_mtu = ETH_ZLEN;
7223 jumbo_max = rtl_jumbo_max(tp);
7224 dev->max_mtu = jumbo_max;
7225
7226 rtl_set_irq_mask(tp);
7227
7228 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7229
7230 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7231 &tp->counters_phys_addr,
7232 GFP_KERNEL);
7233 if (!tp->counters)
7234 return -ENOMEM;
7235
7236 pci_set_drvdata(pdev, dev);
7237
7238 rc = r8169_mdio_register(tp);
7239 if (rc)
7240 return rc;
7241
7242 /* chip gets powered up in rtl_open() */
7243 rtl_pll_power_down(tp);
7244
7245 rc = register_netdev(dev);
7246 if (rc)
7247 goto err_mdio_unregister;
7248
7249 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7250 rtl_chip_infos[chipset].name, dev->dev_addr,
7251 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7252 pci_irq_vector(pdev, 0));
7253
7254 if (jumbo_max > JUMBO_1K)
7255 netif_info(tp, probe, dev,
7256 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7257 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7258 "ok" : "ko");
7259
7260 if (r8168_check_dash(tp))
7261 rtl8168_driver_start(tp);
7262
7263 if (pci_dev_run_wake(pdev))
7264 pm_runtime_put_sync(&pdev->dev);
7265
7266 return 0;
7267
7268err_mdio_unregister:
7269 mdiobus_unregister(tp->phydev->mdio.bus);
7270 return rc;
7271}
7272
7273static struct pci_driver rtl8169_pci_driver = {
7274 .name = MODULENAME,
7275 .id_table = rtl8169_pci_tbl,
7276 .probe = rtl_init_one,
7277 .remove = rtl_remove_one,
7278 .shutdown = rtl_shutdown,
7279 .driver.pm = RTL8169_PM_OPS,
7280};
7281
7282module_pci_driver(rtl8169_pci_driver);