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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / net / ethernet / renesas / sh_eth.c
blob: 50d85d0372302b75d7a38567544f6a75550c735b [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/* SuperH Ethernet device driver
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/dma-mapping.h>
16#include <linux/etherdevice.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/mdio-bitbang.h>
20#include <linux/netdevice.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/of_net.h>
25#include <linux/phy.h>
26#include <linux/cache.h>
27#include <linux/io.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/ethtool.h>
31#include <linux/if_vlan.h>
32#include <linux/sh_eth.h>
33#include <linux/of_mdio.h>
34
35#include "sh_eth.h"
36
37#define SH_ETH_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR| \
41 NETIF_MSG_TX_ERR)
42
43#define SH_ETH_OFFSET_INVALID ((u16)~0)
44
45#define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
47
48static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
49 SH_ETH_OFFSET_DEFAULTS,
50
51 [EDSR] = 0x0000,
52 [EDMR] = 0x0400,
53 [EDTRR] = 0x0408,
54 [EDRRR] = 0x0410,
55 [EESR] = 0x0428,
56 [EESIPR] = 0x0430,
57 [TDLAR] = 0x0010,
58 [TDFAR] = 0x0014,
59 [TDFXR] = 0x0018,
60 [TDFFR] = 0x001c,
61 [RDLAR] = 0x0030,
62 [RDFAR] = 0x0034,
63 [RDFXR] = 0x0038,
64 [RDFFR] = 0x003c,
65 [TRSCER] = 0x0438,
66 [RMFCR] = 0x0440,
67 [TFTR] = 0x0448,
68 [FDR] = 0x0450,
69 [RMCR] = 0x0458,
70 [RPADIR] = 0x0460,
71 [FCFTR] = 0x0468,
72 [CSMR] = 0x04E4,
73
74 [ECMR] = 0x0500,
75 [ECSR] = 0x0510,
76 [ECSIPR] = 0x0518,
77 [PIR] = 0x0520,
78 [PSR] = 0x0528,
79 [PIPR] = 0x052c,
80 [RFLR] = 0x0508,
81 [APR] = 0x0554,
82 [MPR] = 0x0558,
83 [PFTCR] = 0x055c,
84 [PFRCR] = 0x0560,
85 [TPAUSER] = 0x0564,
86 [GECMR] = 0x05b0,
87 [BCULR] = 0x05b4,
88 [MAHR] = 0x05c0,
89 [MALR] = 0x05c8,
90 [TROCR] = 0x0700,
91 [CDCR] = 0x0708,
92 [LCCR] = 0x0710,
93 [CEFCR] = 0x0740,
94 [FRECR] = 0x0748,
95 [TSFRCR] = 0x0750,
96 [TLFRCR] = 0x0758,
97 [RFCR] = 0x0760,
98 [CERCR] = 0x0768,
99 [CEECR] = 0x0770,
100 [MAFCR] = 0x0778,
101 [RMII_MII] = 0x0790,
102
103 [ARSTR] = 0x0000,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
107 [TSU_FCM] = 0x0018,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
117 [TSU_FWSR] = 0x0050,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
124 [TSU_TEN] = 0x0064,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
130
131 [TXNLCR0] = 0x0080,
132 [TXALCR0] = 0x0084,
133 [RXNLCR0] = 0x0088,
134 [RXALCR0] = 0x008c,
135 [FWNLCR0] = 0x0090,
136 [FWALCR0] = 0x0094,
137 [TXNLCR1] = 0x00a0,
138 [TXALCR1] = 0x00a4,
139 [RXNLCR1] = 0x00a8,
140 [RXALCR1] = 0x00ac,
141 [FWNLCR1] = 0x00b0,
142 [FWALCR1] = 0x00b4,
143};
144
145static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
146 SH_ETH_OFFSET_DEFAULTS,
147
148 [EDSR] = 0x0000,
149 [EDMR] = 0x0400,
150 [EDTRR] = 0x0408,
151 [EDRRR] = 0x0410,
152 [EESR] = 0x0428,
153 [EESIPR] = 0x0430,
154 [TDLAR] = 0x0010,
155 [TDFAR] = 0x0014,
156 [TDFXR] = 0x0018,
157 [TDFFR] = 0x001c,
158 [RDLAR] = 0x0030,
159 [RDFAR] = 0x0034,
160 [RDFXR] = 0x0038,
161 [RDFFR] = 0x003c,
162 [TRSCER] = 0x0438,
163 [RMFCR] = 0x0440,
164 [TFTR] = 0x0448,
165 [FDR] = 0x0450,
166 [RMCR] = 0x0458,
167 [RPADIR] = 0x0460,
168 [FCFTR] = 0x0468,
169 [CSMR] = 0x04E4,
170
171 [ECMR] = 0x0500,
172 [RFLR] = 0x0508,
173 [ECSR] = 0x0510,
174 [ECSIPR] = 0x0518,
175 [PIR] = 0x0520,
176 [APR] = 0x0554,
177 [MPR] = 0x0558,
178 [PFTCR] = 0x055c,
179 [PFRCR] = 0x0560,
180 [TPAUSER] = 0x0564,
181 [MAHR] = 0x05c0,
182 [MALR] = 0x05c8,
183 [CEFCR] = 0x0740,
184 [FRECR] = 0x0748,
185 [TSFRCR] = 0x0750,
186 [TLFRCR] = 0x0758,
187 [RFCR] = 0x0760,
188 [MAFCR] = 0x0778,
189
190 [ARSTR] = 0x0000,
191 [TSU_CTRST] = 0x0004,
192 [TSU_FWSLC] = 0x0038,
193 [TSU_VTAG0] = 0x0058,
194 [TSU_ADSBSY] = 0x0060,
195 [TSU_TEN] = 0x0064,
196 [TSU_POST1] = 0x0070,
197 [TSU_POST2] = 0x0074,
198 [TSU_POST3] = 0x0078,
199 [TSU_POST4] = 0x007c,
200 [TSU_ADRH0] = 0x0100,
201
202 [TXNLCR0] = 0x0080,
203 [TXALCR0] = 0x0084,
204 [RXNLCR0] = 0x0088,
205 [RXALCR0] = 0x008C,
206};
207
208static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
209 SH_ETH_OFFSET_DEFAULTS,
210
211 [ECMR] = 0x0300,
212 [RFLR] = 0x0308,
213 [ECSR] = 0x0310,
214 [ECSIPR] = 0x0318,
215 [PIR] = 0x0320,
216 [PSR] = 0x0328,
217 [RDMLR] = 0x0340,
218 [IPGR] = 0x0350,
219 [APR] = 0x0354,
220 [MPR] = 0x0358,
221 [RFCF] = 0x0360,
222 [TPAUSER] = 0x0364,
223 [TPAUSECR] = 0x0368,
224 [MAHR] = 0x03c0,
225 [MALR] = 0x03c8,
226 [TROCR] = 0x03d0,
227 [CDCR] = 0x03d4,
228 [LCCR] = 0x03d8,
229 [CNDCR] = 0x03dc,
230 [CEFCR] = 0x03e4,
231 [FRECR] = 0x03e8,
232 [TSFRCR] = 0x03ec,
233 [TLFRCR] = 0x03f0,
234 [RFCR] = 0x03f4,
235 [MAFCR] = 0x03f8,
236
237 [EDMR] = 0x0200,
238 [EDTRR] = 0x0208,
239 [EDRRR] = 0x0210,
240 [TDLAR] = 0x0218,
241 [RDLAR] = 0x0220,
242 [EESR] = 0x0228,
243 [EESIPR] = 0x0230,
244 [TRSCER] = 0x0238,
245 [RMFCR] = 0x0240,
246 [TFTR] = 0x0248,
247 [FDR] = 0x0250,
248 [RMCR] = 0x0258,
249 [TFUCR] = 0x0264,
250 [RFOCR] = 0x0268,
251 [RMIIMODE] = 0x026c,
252 [FCFTR] = 0x0270,
253 [TRIMD] = 0x027c,
254};
255
256static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
258
259 [ECMR] = 0x0100,
260 [RFLR] = 0x0108,
261 [ECSR] = 0x0110,
262 [ECSIPR] = 0x0118,
263 [PIR] = 0x0120,
264 [PSR] = 0x0128,
265 [RDMLR] = 0x0140,
266 [IPGR] = 0x0150,
267 [APR] = 0x0154,
268 [MPR] = 0x0158,
269 [TPAUSER] = 0x0164,
270 [RFCF] = 0x0160,
271 [TPAUSECR] = 0x0168,
272 [BCFRR] = 0x016c,
273 [MAHR] = 0x01c0,
274 [MALR] = 0x01c8,
275 [TROCR] = 0x01d0,
276 [CDCR] = 0x01d4,
277 [LCCR] = 0x01d8,
278 [CNDCR] = 0x01dc,
279 [CEFCR] = 0x01e4,
280 [FRECR] = 0x01e8,
281 [TSFRCR] = 0x01ec,
282 [TLFRCR] = 0x01f0,
283 [RFCR] = 0x01f4,
284 [MAFCR] = 0x01f8,
285 [RTRATE] = 0x01fc,
286
287 [EDMR] = 0x0000,
288 [EDTRR] = 0x0008,
289 [EDRRR] = 0x0010,
290 [TDLAR] = 0x0018,
291 [RDLAR] = 0x0020,
292 [EESR] = 0x0028,
293 [EESIPR] = 0x0030,
294 [TRSCER] = 0x0038,
295 [RMFCR] = 0x0040,
296 [TFTR] = 0x0048,
297 [FDR] = 0x0050,
298 [RMCR] = 0x0058,
299 [TFUCR] = 0x0064,
300 [RFOCR] = 0x0068,
301 [FCFTR] = 0x0070,
302 [RPADIR] = 0x0078,
303 [TRIMD] = 0x007c,
304 [RBWAR] = 0x00c8,
305 [RDFAR] = 0x00cc,
306 [TBRAR] = 0x00d4,
307 [TDFAR] = 0x00d8,
308};
309
310static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
311 SH_ETH_OFFSET_DEFAULTS,
312
313 [EDMR] = 0x0000,
314 [EDTRR] = 0x0004,
315 [EDRRR] = 0x0008,
316 [TDLAR] = 0x000c,
317 [RDLAR] = 0x0010,
318 [EESR] = 0x0014,
319 [EESIPR] = 0x0018,
320 [TRSCER] = 0x001c,
321 [RMFCR] = 0x0020,
322 [TFTR] = 0x0024,
323 [FDR] = 0x0028,
324 [RMCR] = 0x002c,
325 [EDOCR] = 0x0030,
326 [FCFTR] = 0x0034,
327 [RPADIR] = 0x0038,
328 [TRIMD] = 0x003c,
329 [RBWAR] = 0x0040,
330 [RDFAR] = 0x0044,
331 [TBRAR] = 0x004c,
332 [TDFAR] = 0x0050,
333
334 [ECMR] = 0x0160,
335 [ECSR] = 0x0164,
336 [ECSIPR] = 0x0168,
337 [PIR] = 0x016c,
338 [MAHR] = 0x0170,
339 [MALR] = 0x0174,
340 [RFLR] = 0x0178,
341 [PSR] = 0x017c,
342 [TROCR] = 0x0180,
343 [CDCR] = 0x0184,
344 [LCCR] = 0x0188,
345 [CNDCR] = 0x018c,
346 [CEFCR] = 0x0194,
347 [FRECR] = 0x0198,
348 [TSFRCR] = 0x019c,
349 [TLFRCR] = 0x01a0,
350 [RFCR] = 0x01a4,
351 [MAFCR] = 0x01a8,
352 [IPGR] = 0x01b4,
353 [APR] = 0x01b8,
354 [MPR] = 0x01bc,
355 [TPAUSER] = 0x01c4,
356 [BCFR] = 0x01cc,
357
358 [ARSTR] = 0x0000,
359 [TSU_CTRST] = 0x0004,
360 [TSU_FWEN0] = 0x0010,
361 [TSU_FWEN1] = 0x0014,
362 [TSU_FCM] = 0x0018,
363 [TSU_BSYSL0] = 0x0020,
364 [TSU_BSYSL1] = 0x0024,
365 [TSU_PRISL0] = 0x0028,
366 [TSU_PRISL1] = 0x002c,
367 [TSU_FWSL0] = 0x0030,
368 [TSU_FWSL1] = 0x0034,
369 [TSU_FWSLC] = 0x0038,
370 [TSU_QTAGM0] = 0x0040,
371 [TSU_QTAGM1] = 0x0044,
372 [TSU_ADQT0] = 0x0048,
373 [TSU_ADQT1] = 0x004c,
374 [TSU_FWSR] = 0x0050,
375 [TSU_FWINMK] = 0x0054,
376 [TSU_ADSBSY] = 0x0060,
377 [TSU_TEN] = 0x0064,
378 [TSU_POST1] = 0x0070,
379 [TSU_POST2] = 0x0074,
380 [TSU_POST3] = 0x0078,
381 [TSU_POST4] = 0x007c,
382
383 [TXNLCR0] = 0x0080,
384 [TXALCR0] = 0x0084,
385 [RXNLCR0] = 0x0088,
386 [RXALCR0] = 0x008c,
387 [FWNLCR0] = 0x0090,
388 [FWALCR0] = 0x0094,
389 [TXNLCR1] = 0x00a0,
390 [TXALCR1] = 0x00a4,
391 [RXNLCR1] = 0x00a8,
392 [RXALCR1] = 0x00ac,
393 [FWNLCR1] = 0x00b0,
394 [FWALCR1] = 0x00b4,
395
396 [TSU_ADRH0] = 0x0100,
397};
398
399static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
401
402static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
403{
404 struct sh_eth_private *mdp = netdev_priv(ndev);
405 u16 offset = mdp->reg_offset[enum_index];
406
407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
408 return;
409
410 iowrite32(data, mdp->addr + offset);
411}
412
413static u32 sh_eth_read(struct net_device *ndev, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return ~0U;
420
421 return ioread32(mdp->addr + offset);
422}
423
424static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
425 u32 set)
426{
427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
428 enum_index);
429}
430
431static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
432{
433 return mdp->reg_offset[enum_index];
434}
435
436static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
437 int enum_index)
438{
439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
440
441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
442 return;
443
444 iowrite32(data, mdp->tsu_addr + offset);
445}
446
447static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
448{
449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
450
451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
452 return ~0U;
453
454 return ioread32(mdp->tsu_addr + offset);
455}
456
457static void sh_eth_soft_swap(char *src, int len)
458{
459#ifdef __LITTLE_ENDIAN
460 u32 *p = (u32 *)src;
461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
462
463 for (; p < maxp; p++)
464 *p = swab32(*p);
465#endif
466}
467
468static void sh_eth_select_mii(struct net_device *ndev)
469{
470 struct sh_eth_private *mdp = netdev_priv(ndev);
471 u32 value;
472
473 switch (mdp->phy_interface) {
474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
475 value = 0x3;
476 break;
477 case PHY_INTERFACE_MODE_GMII:
478 value = 0x2;
479 break;
480 case PHY_INTERFACE_MODE_MII:
481 value = 0x1;
482 break;
483 case PHY_INTERFACE_MODE_RMII:
484 value = 0x0;
485 break;
486 default:
487 netdev_warn(ndev,
488 "PHY interface mode was not setup. Set to MII.\n");
489 value = 0x1;
490 break;
491 }
492
493 sh_eth_write(ndev, value, RMII_MII);
494}
495
496static void sh_eth_set_duplex(struct net_device *ndev)
497{
498 struct sh_eth_private *mdp = netdev_priv(ndev);
499
500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
501}
502
503static void sh_eth_chip_reset(struct net_device *ndev)
504{
505 struct sh_eth_private *mdp = netdev_priv(ndev);
506
507 /* reset device */
508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
509 mdelay(1);
510}
511
512static int sh_eth_soft_reset(struct net_device *ndev)
513{
514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
515 mdelay(3);
516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
517
518 return 0;
519}
520
521static int sh_eth_check_soft_reset(struct net_device *ndev)
522{
523 int cnt;
524
525 for (cnt = 100; cnt > 0; cnt--) {
526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
527 return 0;
528 mdelay(1);
529 }
530
531 netdev_err(ndev, "Device reset failed\n");
532 return -ETIMEDOUT;
533}
534
535static int sh_eth_soft_reset_gether(struct net_device *ndev)
536{
537 struct sh_eth_private *mdp = netdev_priv(ndev);
538 int ret;
539
540 sh_eth_write(ndev, EDSR_ENALL, EDSR);
541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
542
543 ret = sh_eth_check_soft_reset(ndev);
544 if (ret)
545 return ret;
546
547 /* Table Init */
548 sh_eth_write(ndev, 0, TDLAR);
549 sh_eth_write(ndev, 0, TDFAR);
550 sh_eth_write(ndev, 0, TDFXR);
551 sh_eth_write(ndev, 0, TDFFR);
552 sh_eth_write(ndev, 0, RDLAR);
553 sh_eth_write(ndev, 0, RDFAR);
554 sh_eth_write(ndev, 0, RDFXR);
555 sh_eth_write(ndev, 0, RDFFR);
556
557 /* Reset HW CRC register */
558 if (mdp->cd->csmr)
559 sh_eth_write(ndev, 0, CSMR);
560
561 /* Select MII mode */
562 if (mdp->cd->select_mii)
563 sh_eth_select_mii(ndev);
564
565 return ret;
566}
567
568static void sh_eth_set_rate_gether(struct net_device *ndev)
569{
570 struct sh_eth_private *mdp = netdev_priv(ndev);
571
572 switch (mdp->speed) {
573 case 10: /* 10BASE */
574 sh_eth_write(ndev, GECMR_10, GECMR);
575 break;
576 case 100:/* 100BASE */
577 sh_eth_write(ndev, GECMR_100, GECMR);
578 break;
579 case 1000: /* 1000BASE */
580 sh_eth_write(ndev, GECMR_1000, GECMR);
581 break;
582 }
583}
584
585#ifdef CONFIG_OF
586/* R7S72100 */
587static struct sh_eth_cpu_data r7s72100_data = {
588 .soft_reset = sh_eth_soft_reset_gether,
589
590 .chip_reset = sh_eth_chip_reset,
591 .set_duplex = sh_eth_set_duplex,
592
593 .register_type = SH_ETH_REG_FAST_RZ,
594
595 .edtrr_trns = EDTRR_TRNS_GETHER,
596 .ecsr_value = ECSR_ICD,
597 .ecsipr_value = ECSIPR_ICDIP,
598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
600 EESIPR_ECIIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 EESIPR_RMAFIP | EESIPR_RRFIP |
604 EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
606
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
610 EESR_TDE,
611 .fdr_value = 0x0000070f,
612
613 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
614
615 .no_psr = 1,
616 .apr = 1,
617 .mpr = 1,
618 .tpauser = 1,
619 .hw_swap = 1,
620 .rpadir = 1,
621 .no_trimd = 1,
622 .no_ade = 1,
623 .xdfar_rw = 1,
624 .csmr = 1,
625 .rx_csum = 1,
626 .tsu = 1,
627 .no_tx_cntrs = 1,
628};
629
630static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
631{
632 sh_eth_chip_reset(ndev);
633
634 sh_eth_select_mii(ndev);
635}
636
637/* R8A7740 */
638static struct sh_eth_cpu_data r8a7740_data = {
639 .soft_reset = sh_eth_soft_reset_gether,
640
641 .chip_reset = sh_eth_chip_reset_r8a7740,
642 .set_duplex = sh_eth_set_duplex,
643 .set_rate = sh_eth_set_rate_gether,
644
645 .register_type = SH_ETH_REG_GIGABIT,
646
647 .edtrr_trns = EDTRR_TRNS_GETHER,
648 .ecsr_value = ECSR_ICD | ECSR_MPD,
649 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
650 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
651 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
652 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
653 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
654 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
655 EESIPR_CEEFIP | EESIPR_CELFIP |
656 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
657 EESIPR_PREIP | EESIPR_CERFIP,
658
659 .tx_check = EESR_TC1 | EESR_FTC,
660 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
661 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
662 EESR_TDE,
663 .fdr_value = 0x0000070f,
664
665 .apr = 1,
666 .mpr = 1,
667 .tpauser = 1,
668 .bculr = 1,
669 .hw_swap = 1,
670 .rpadir = 1,
671 .no_trimd = 1,
672 .no_ade = 1,
673 .xdfar_rw = 1,
674 .csmr = 1,
675 .rx_csum = 1,
676 .tsu = 1,
677 .select_mii = 1,
678 .magic = 1,
679 .cexcr = 1,
680};
681
682/* There is CPU dependent code */
683static void sh_eth_set_rate_rcar(struct net_device *ndev)
684{
685 struct sh_eth_private *mdp = netdev_priv(ndev);
686
687 switch (mdp->speed) {
688 case 10: /* 10BASE */
689 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
690 break;
691 case 100:/* 100BASE */
692 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
693 break;
694 }
695}
696
697/* R-Car Gen1 */
698static struct sh_eth_cpu_data rcar_gen1_data = {
699 .soft_reset = sh_eth_soft_reset,
700
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_rcar,
703
704 .register_type = SH_ETH_REG_FAST_RCAR,
705
706 .edtrr_trns = EDTRR_TRNS_ETHER,
707 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
708 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
709 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
710 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
711 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
712 EESIPR_RMAFIP | EESIPR_RRFIP |
713 EESIPR_RTLFIP | EESIPR_RTSFIP |
714 EESIPR_PREIP | EESIPR_CERFIP,
715
716 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
717 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
718 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
719 .fdr_value = 0x00000f0f,
720
721 .apr = 1,
722 .mpr = 1,
723 .tpauser = 1,
724 .hw_swap = 1,
725 .no_xdfar = 1,
726};
727
728/* R-Car Gen2 and RZ/G1 */
729static struct sh_eth_cpu_data rcar_gen2_data = {
730 .soft_reset = sh_eth_soft_reset,
731
732 .set_duplex = sh_eth_set_duplex,
733 .set_rate = sh_eth_set_rate_rcar,
734
735 .register_type = SH_ETH_REG_FAST_RCAR,
736
737 .edtrr_trns = EDTRR_TRNS_ETHER,
738 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
739 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
740 ECSIPR_MPDIP,
741 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
742 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
743 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
744 EESIPR_RMAFIP | EESIPR_RRFIP |
745 EESIPR_RTLFIP | EESIPR_RTSFIP |
746 EESIPR_PREIP | EESIPR_CERFIP,
747
748 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
749 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
750 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
751 .fdr_value = 0x00000f0f,
752
753 .trscer_err_mask = DESC_I_RINT8,
754
755 .apr = 1,
756 .mpr = 1,
757 .tpauser = 1,
758 .hw_swap = 1,
759 .no_xdfar = 1,
760 .rmiimode = 1,
761 .magic = 1,
762};
763
764/* R8A77980 */
765static struct sh_eth_cpu_data r8a77980_data = {
766 .soft_reset = sh_eth_soft_reset_gether,
767
768 .set_duplex = sh_eth_set_duplex,
769 .set_rate = sh_eth_set_rate_gether,
770
771 .register_type = SH_ETH_REG_GIGABIT,
772
773 .edtrr_trns = EDTRR_TRNS_GETHER,
774 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
775 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
776 ECSIPR_MPDIP,
777 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
778 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
779 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
780 EESIPR_RMAFIP | EESIPR_RRFIP |
781 EESIPR_RTLFIP | EESIPR_RTSFIP |
782 EESIPR_PREIP | EESIPR_CERFIP,
783
784 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
785 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
786 EESR_RFE | EESR_RDE | EESR_RFRMER |
787 EESR_TFE | EESR_TDE | EESR_ECI,
788 .fdr_value = 0x0000070f,
789
790 .apr = 1,
791 .mpr = 1,
792 .tpauser = 1,
793 .bculr = 1,
794 .hw_swap = 1,
795 .nbst = 1,
796 .rpadir = 1,
797 .no_trimd = 1,
798 .no_ade = 1,
799 .xdfar_rw = 1,
800 .csmr = 1,
801 .rx_csum = 1,
802 .select_mii = 1,
803 .magic = 1,
804 .cexcr = 1,
805};
806
807/* R7S9210 */
808static struct sh_eth_cpu_data r7s9210_data = {
809 .soft_reset = sh_eth_soft_reset,
810
811 .set_duplex = sh_eth_set_duplex,
812 .set_rate = sh_eth_set_rate_rcar,
813
814 .register_type = SH_ETH_REG_FAST_SH4,
815
816 .edtrr_trns = EDTRR_TRNS_ETHER,
817 .ecsr_value = ECSR_ICD,
818 .ecsipr_value = ECSIPR_ICDIP,
819 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
820 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
821 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
822 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
823 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
824 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
825 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
826
827 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
828 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
829 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
830
831 .fdr_value = 0x0000070f,
832
833 .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
834
835 .apr = 1,
836 .mpr = 1,
837 .tpauser = 1,
838 .hw_swap = 1,
839 .rpadir = 1,
840 .no_ade = 1,
841 .xdfar_rw = 1,
842};
843#endif /* CONFIG_OF */
844
845static void sh_eth_set_rate_sh7724(struct net_device *ndev)
846{
847 struct sh_eth_private *mdp = netdev_priv(ndev);
848
849 switch (mdp->speed) {
850 case 10: /* 10BASE */
851 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
852 break;
853 case 100:/* 100BASE */
854 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
855 break;
856 }
857}
858
859/* SH7724 */
860static struct sh_eth_cpu_data sh7724_data = {
861 .soft_reset = sh_eth_soft_reset,
862
863 .set_duplex = sh_eth_set_duplex,
864 .set_rate = sh_eth_set_rate_sh7724,
865
866 .register_type = SH_ETH_REG_FAST_SH4,
867
868 .edtrr_trns = EDTRR_TRNS_ETHER,
869 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
870 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
871 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
872 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
873 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
874 EESIPR_RMAFIP | EESIPR_RRFIP |
875 EESIPR_RTLFIP | EESIPR_RTSFIP |
876 EESIPR_PREIP | EESIPR_CERFIP,
877
878 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
879 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
880 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
881
882 .apr = 1,
883 .mpr = 1,
884 .tpauser = 1,
885 .hw_swap = 1,
886 .rpadir = 1,
887};
888
889static void sh_eth_set_rate_sh7757(struct net_device *ndev)
890{
891 struct sh_eth_private *mdp = netdev_priv(ndev);
892
893 switch (mdp->speed) {
894 case 10: /* 10BASE */
895 sh_eth_write(ndev, 0, RTRATE);
896 break;
897 case 100:/* 100BASE */
898 sh_eth_write(ndev, 1, RTRATE);
899 break;
900 }
901}
902
903/* SH7757 */
904static struct sh_eth_cpu_data sh7757_data = {
905 .soft_reset = sh_eth_soft_reset,
906
907 .set_duplex = sh_eth_set_duplex,
908 .set_rate = sh_eth_set_rate_sh7757,
909
910 .register_type = SH_ETH_REG_FAST_SH4,
911
912 .edtrr_trns = EDTRR_TRNS_ETHER,
913 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
914 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
915 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
916 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
917 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
918 EESIPR_CEEFIP | EESIPR_CELFIP |
919 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
920 EESIPR_PREIP | EESIPR_CERFIP,
921
922 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
923 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
924 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
925
926 .irq_flags = IRQF_SHARED,
927 .apr = 1,
928 .mpr = 1,
929 .tpauser = 1,
930 .hw_swap = 1,
931 .no_ade = 1,
932 .rpadir = 1,
933 .rtrate = 1,
934 .dual_port = 1,
935};
936
937#define SH_GIGA_ETH_BASE 0xfee00000UL
938#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
939#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
940static void sh_eth_chip_reset_giga(struct net_device *ndev)
941{
942 u32 mahr[2], malr[2];
943 int i;
944
945 /* save MAHR and MALR */
946 for (i = 0; i < 2; i++) {
947 malr[i] = ioread32((void *)GIGA_MALR(i));
948 mahr[i] = ioread32((void *)GIGA_MAHR(i));
949 }
950
951 sh_eth_chip_reset(ndev);
952
953 /* restore MAHR and MALR */
954 for (i = 0; i < 2; i++) {
955 iowrite32(malr[i], (void *)GIGA_MALR(i));
956 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
957 }
958}
959
960static void sh_eth_set_rate_giga(struct net_device *ndev)
961{
962 struct sh_eth_private *mdp = netdev_priv(ndev);
963
964 switch (mdp->speed) {
965 case 10: /* 10BASE */
966 sh_eth_write(ndev, 0x00000000, GECMR);
967 break;
968 case 100:/* 100BASE */
969 sh_eth_write(ndev, 0x00000010, GECMR);
970 break;
971 case 1000: /* 1000BASE */
972 sh_eth_write(ndev, 0x00000020, GECMR);
973 break;
974 }
975}
976
977/* SH7757(GETHERC) */
978static struct sh_eth_cpu_data sh7757_data_giga = {
979 .soft_reset = sh_eth_soft_reset_gether,
980
981 .chip_reset = sh_eth_chip_reset_giga,
982 .set_duplex = sh_eth_set_duplex,
983 .set_rate = sh_eth_set_rate_giga,
984
985 .register_type = SH_ETH_REG_GIGABIT,
986
987 .edtrr_trns = EDTRR_TRNS_GETHER,
988 .ecsr_value = ECSR_ICD | ECSR_MPD,
989 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
990 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
991 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
992 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
993 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
994 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
995 EESIPR_CEEFIP | EESIPR_CELFIP |
996 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
997 EESIPR_PREIP | EESIPR_CERFIP,
998
999 .tx_check = EESR_TC1 | EESR_FTC,
1000 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1001 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1002 EESR_TDE,
1003 .fdr_value = 0x0000072f,
1004
1005 .irq_flags = IRQF_SHARED,
1006 .apr = 1,
1007 .mpr = 1,
1008 .tpauser = 1,
1009 .bculr = 1,
1010 .hw_swap = 1,
1011 .rpadir = 1,
1012 .no_trimd = 1,
1013 .no_ade = 1,
1014 .xdfar_rw = 1,
1015 .tsu = 1,
1016 .cexcr = 1,
1017 .dual_port = 1,
1018};
1019
1020/* SH7734 */
1021static struct sh_eth_cpu_data sh7734_data = {
1022 .soft_reset = sh_eth_soft_reset_gether,
1023
1024 .chip_reset = sh_eth_chip_reset,
1025 .set_duplex = sh_eth_set_duplex,
1026 .set_rate = sh_eth_set_rate_gether,
1027
1028 .register_type = SH_ETH_REG_GIGABIT,
1029
1030 .edtrr_trns = EDTRR_TRNS_GETHER,
1031 .ecsr_value = ECSR_ICD | ECSR_MPD,
1032 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1033 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1034 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1035 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1036 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1037 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1038 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1039 EESIPR_PREIP | EESIPR_CERFIP,
1040
1041 .tx_check = EESR_TC1 | EESR_FTC,
1042 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1043 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1044 EESR_TDE,
1045
1046 .apr = 1,
1047 .mpr = 1,
1048 .tpauser = 1,
1049 .bculr = 1,
1050 .hw_swap = 1,
1051 .no_trimd = 1,
1052 .no_ade = 1,
1053 .xdfar_rw = 1,
1054 .tsu = 1,
1055 .csmr = 1,
1056 .rx_csum = 1,
1057 .select_mii = 1,
1058 .magic = 1,
1059 .cexcr = 1,
1060};
1061
1062/* SH7763 */
1063static struct sh_eth_cpu_data sh7763_data = {
1064 .soft_reset = sh_eth_soft_reset_gether,
1065
1066 .chip_reset = sh_eth_chip_reset,
1067 .set_duplex = sh_eth_set_duplex,
1068 .set_rate = sh_eth_set_rate_gether,
1069
1070 .register_type = SH_ETH_REG_GIGABIT,
1071
1072 .edtrr_trns = EDTRR_TRNS_GETHER,
1073 .ecsr_value = ECSR_ICD | ECSR_MPD,
1074 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1075 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1076 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1077 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1078 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1079 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1080 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1081 EESIPR_PREIP | EESIPR_CERFIP,
1082
1083 .tx_check = EESR_TC1 | EESR_FTC,
1084 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1085 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1086
1087 .apr = 1,
1088 .mpr = 1,
1089 .tpauser = 1,
1090 .bculr = 1,
1091 .hw_swap = 1,
1092 .no_trimd = 1,
1093 .no_ade = 1,
1094 .xdfar_rw = 1,
1095 .tsu = 1,
1096 .irq_flags = IRQF_SHARED,
1097 .magic = 1,
1098 .cexcr = 1,
1099 .rx_csum = 1,
1100 .dual_port = 1,
1101};
1102
1103static struct sh_eth_cpu_data sh7619_data = {
1104 .soft_reset = sh_eth_soft_reset,
1105
1106 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1107
1108 .edtrr_trns = EDTRR_TRNS_ETHER,
1109 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1110 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1111 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1112 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1113 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1114 EESIPR_CEEFIP | EESIPR_CELFIP |
1115 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1116 EESIPR_PREIP | EESIPR_CERFIP,
1117
1118 .apr = 1,
1119 .mpr = 1,
1120 .tpauser = 1,
1121 .hw_swap = 1,
1122};
1123
1124static struct sh_eth_cpu_data sh771x_data = {
1125 .soft_reset = sh_eth_soft_reset,
1126
1127 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1128
1129 .edtrr_trns = EDTRR_TRNS_ETHER,
1130 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1131 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1132 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1133 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1134 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1135 EESIPR_CEEFIP | EESIPR_CELFIP |
1136 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1137 EESIPR_PREIP | EESIPR_CERFIP,
1138
1139 .trscer_err_mask = DESC_I_RINT8,
1140
1141 .tsu = 1,
1142 .dual_port = 1,
1143};
1144
1145static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1146{
1147 if (!cd->ecsr_value)
1148 cd->ecsr_value = DEFAULT_ECSR_INIT;
1149
1150 if (!cd->ecsipr_value)
1151 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1152
1153 if (!cd->fcftr_value)
1154 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1155 DEFAULT_FIFO_F_D_RFD;
1156
1157 if (!cd->fdr_value)
1158 cd->fdr_value = DEFAULT_FDR_INIT;
1159
1160 if (!cd->tx_check)
1161 cd->tx_check = DEFAULT_TX_CHECK;
1162
1163 if (!cd->eesr_err_check)
1164 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1165
1166 if (!cd->trscer_err_mask)
1167 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1168}
1169
1170static void sh_eth_set_receive_align(struct sk_buff *skb)
1171{
1172 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1173
1174 if (reserve)
1175 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1176}
1177
1178/* Program the hardware MAC address from dev->dev_addr. */
1179static void update_mac_address(struct net_device *ndev)
1180{
1181 sh_eth_write(ndev,
1182 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1183 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1184 sh_eth_write(ndev,
1185 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1186}
1187
1188/* Get MAC address from SuperH MAC address register
1189 *
1190 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1191 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1192 * When you want use this device, you must set MAC address in bootloader.
1193 *
1194 */
1195static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1196{
1197 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1198 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1199 } else {
1200 u32 mahr = sh_eth_read(ndev, MAHR);
1201 u32 malr = sh_eth_read(ndev, MALR);
1202
1203 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1204 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1205 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1206 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1207 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1208 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1209 }
1210}
1211
1212struct bb_info {
1213 void (*set_gate)(void *addr);
1214 struct mdiobb_ctrl ctrl;
1215 void *addr;
1216};
1217
1218static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1219{
1220 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1221 u32 pir;
1222
1223 if (bitbang->set_gate)
1224 bitbang->set_gate(bitbang->addr);
1225
1226 pir = ioread32(bitbang->addr);
1227 if (set)
1228 pir |= mask;
1229 else
1230 pir &= ~mask;
1231 iowrite32(pir, bitbang->addr);
1232}
1233
1234/* Data I/O pin control */
1235static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1236{
1237 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1238}
1239
1240/* Set bit data*/
1241static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1242{
1243 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1244}
1245
1246/* Get bit data*/
1247static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1248{
1249 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1250
1251 if (bitbang->set_gate)
1252 bitbang->set_gate(bitbang->addr);
1253
1254 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1255}
1256
1257/* MDC pin control */
1258static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1259{
1260 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1261}
1262
1263/* mdio bus control struct */
1264static struct mdiobb_ops bb_ops = {
1265 .owner = THIS_MODULE,
1266 .set_mdc = sh_mdc_ctrl,
1267 .set_mdio_dir = sh_mmd_ctrl,
1268 .set_mdio_data = sh_set_mdio,
1269 .get_mdio_data = sh_get_mdio,
1270};
1271
1272/* free Tx skb function */
1273static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1274{
1275 struct sh_eth_private *mdp = netdev_priv(ndev);
1276 struct sh_eth_txdesc *txdesc;
1277 int free_num = 0;
1278 int entry;
1279 bool sent;
1280
1281 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1282 entry = mdp->dirty_tx % mdp->num_tx_ring;
1283 txdesc = &mdp->tx_ring[entry];
1284 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1285 if (sent_only && !sent)
1286 break;
1287 /* TACT bit must be checked before all the following reads */
1288 dma_rmb();
1289 netif_info(mdp, tx_done, ndev,
1290 "tx entry %d status 0x%08x\n",
1291 entry, le32_to_cpu(txdesc->status));
1292 /* Free the original skb. */
1293 if (mdp->tx_skbuff[entry]) {
1294 dma_unmap_single(&mdp->pdev->dev,
1295 le32_to_cpu(txdesc->addr),
1296 le32_to_cpu(txdesc->len) >> 16,
1297 DMA_TO_DEVICE);
1298 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1299 mdp->tx_skbuff[entry] = NULL;
1300 free_num++;
1301 }
1302 txdesc->status = cpu_to_le32(TD_TFP);
1303 if (entry >= mdp->num_tx_ring - 1)
1304 txdesc->status |= cpu_to_le32(TD_TDLE);
1305
1306 if (sent) {
1307 ndev->stats.tx_packets++;
1308 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1309 }
1310 }
1311 return free_num;
1312}
1313
1314/* free skb and descriptor buffer */
1315static void sh_eth_ring_free(struct net_device *ndev)
1316{
1317 struct sh_eth_private *mdp = netdev_priv(ndev);
1318 int ringsize, i;
1319
1320 if (mdp->rx_ring) {
1321 for (i = 0; i < mdp->num_rx_ring; i++) {
1322 if (mdp->rx_skbuff[i]) {
1323 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1324
1325 dma_unmap_single(&mdp->pdev->dev,
1326 le32_to_cpu(rxdesc->addr),
1327 ALIGN(mdp->rx_buf_sz, 32),
1328 DMA_FROM_DEVICE);
1329 }
1330 }
1331 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1332 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1333 mdp->rx_desc_dma);
1334 mdp->rx_ring = NULL;
1335 }
1336
1337 /* Free Rx skb ringbuffer */
1338 if (mdp->rx_skbuff) {
1339 for (i = 0; i < mdp->num_rx_ring; i++)
1340 dev_kfree_skb(mdp->rx_skbuff[i]);
1341 }
1342 kfree(mdp->rx_skbuff);
1343 mdp->rx_skbuff = NULL;
1344
1345 if (mdp->tx_ring) {
1346 sh_eth_tx_free(ndev, false);
1347
1348 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1349 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1350 mdp->tx_desc_dma);
1351 mdp->tx_ring = NULL;
1352 }
1353
1354 /* Free Tx skb ringbuffer */
1355 kfree(mdp->tx_skbuff);
1356 mdp->tx_skbuff = NULL;
1357}
1358
1359/* format skb and descriptor buffer */
1360static void sh_eth_ring_format(struct net_device *ndev)
1361{
1362 struct sh_eth_private *mdp = netdev_priv(ndev);
1363 int i;
1364 struct sk_buff *skb;
1365 struct sh_eth_rxdesc *rxdesc = NULL;
1366 struct sh_eth_txdesc *txdesc = NULL;
1367 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1368 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1369 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1370 dma_addr_t dma_addr;
1371 u32 buf_len;
1372
1373 mdp->cur_rx = 0;
1374 mdp->cur_tx = 0;
1375 mdp->dirty_rx = 0;
1376 mdp->dirty_tx = 0;
1377
1378 memset(mdp->rx_ring, 0, rx_ringsize);
1379
1380 /* build Rx ring buffer */
1381 for (i = 0; i < mdp->num_rx_ring; i++) {
1382 /* skb */
1383 mdp->rx_skbuff[i] = NULL;
1384 skb = netdev_alloc_skb(ndev, skbuff_size);
1385 if (skb == NULL)
1386 break;
1387 sh_eth_set_receive_align(skb);
1388
1389 /* The size of the buffer is a multiple of 32 bytes. */
1390 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1391 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1392 DMA_FROM_DEVICE);
1393 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1394 kfree_skb(skb);
1395 break;
1396 }
1397 mdp->rx_skbuff[i] = skb;
1398
1399 /* RX descriptor */
1400 rxdesc = &mdp->rx_ring[i];
1401 rxdesc->len = cpu_to_le32(buf_len << 16);
1402 rxdesc->addr = cpu_to_le32(dma_addr);
1403 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1404
1405 /* Rx descriptor address set */
1406 if (i == 0) {
1407 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1408 if (mdp->cd->xdfar_rw)
1409 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1410 }
1411 }
1412
1413 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1414
1415 /* Mark the last entry as wrapping the ring. */
1416 if (rxdesc)
1417 rxdesc->status |= cpu_to_le32(RD_RDLE);
1418
1419 memset(mdp->tx_ring, 0, tx_ringsize);
1420
1421 /* build Tx ring buffer */
1422 for (i = 0; i < mdp->num_tx_ring; i++) {
1423 mdp->tx_skbuff[i] = NULL;
1424 txdesc = &mdp->tx_ring[i];
1425 txdesc->status = cpu_to_le32(TD_TFP);
1426 txdesc->len = cpu_to_le32(0);
1427 if (i == 0) {
1428 /* Tx descriptor address set */
1429 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1430 if (mdp->cd->xdfar_rw)
1431 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1432 }
1433 }
1434
1435 txdesc->status |= cpu_to_le32(TD_TDLE);
1436}
1437
1438/* Get skb and descriptor buffer */
1439static int sh_eth_ring_init(struct net_device *ndev)
1440{
1441 struct sh_eth_private *mdp = netdev_priv(ndev);
1442 int rx_ringsize, tx_ringsize;
1443
1444 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1445 * card needs room to do 8 byte alignment, +2 so we can reserve
1446 * the first 2 bytes, and +16 gets room for the status word from the
1447 * card.
1448 */
1449 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1450 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1451 if (mdp->cd->rpadir)
1452 mdp->rx_buf_sz += NET_IP_ALIGN;
1453
1454 /* Allocate RX and TX skb rings */
1455 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1456 GFP_KERNEL);
1457 if (!mdp->rx_skbuff)
1458 return -ENOMEM;
1459
1460 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1461 GFP_KERNEL);
1462 if (!mdp->tx_skbuff)
1463 goto ring_free;
1464
1465 /* Allocate all Rx descriptors. */
1466 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1467 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1468 &mdp->rx_desc_dma, GFP_KERNEL);
1469 if (!mdp->rx_ring)
1470 goto ring_free;
1471
1472 mdp->dirty_rx = 0;
1473
1474 /* Allocate all Tx descriptors. */
1475 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1476 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1477 &mdp->tx_desc_dma, GFP_KERNEL);
1478 if (!mdp->tx_ring)
1479 goto ring_free;
1480 return 0;
1481
1482ring_free:
1483 /* Free Rx and Tx skb ring buffer and DMA buffer */
1484 sh_eth_ring_free(ndev);
1485
1486 return -ENOMEM;
1487}
1488
1489static int sh_eth_dev_init(struct net_device *ndev)
1490{
1491 struct sh_eth_private *mdp = netdev_priv(ndev);
1492 int ret;
1493
1494 /* Soft Reset */
1495 ret = mdp->cd->soft_reset(ndev);
1496 if (ret)
1497 return ret;
1498
1499 if (mdp->cd->rmiimode)
1500 sh_eth_write(ndev, 0x1, RMIIMODE);
1501
1502 /* Descriptor format */
1503 sh_eth_ring_format(ndev);
1504 if (mdp->cd->rpadir)
1505 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1506
1507 /* all sh_eth int mask */
1508 sh_eth_write(ndev, 0, EESIPR);
1509
1510#if defined(__LITTLE_ENDIAN)
1511 if (mdp->cd->hw_swap)
1512 sh_eth_write(ndev, EDMR_EL, EDMR);
1513 else
1514#endif
1515 sh_eth_write(ndev, 0, EDMR);
1516
1517 /* FIFO size set */
1518 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1519 sh_eth_write(ndev, 0, TFTR);
1520
1521 /* Frame recv control (enable multiple-packets per rx irq) */
1522 sh_eth_write(ndev, RMCR_RNC, RMCR);
1523
1524 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1525
1526 /* DMA transfer burst mode */
1527 if (mdp->cd->nbst)
1528 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1529
1530 /* Burst cycle count upper-limit */
1531 if (mdp->cd->bculr)
1532 sh_eth_write(ndev, 0x800, BCULR);
1533
1534 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1535
1536 if (!mdp->cd->no_trimd)
1537 sh_eth_write(ndev, 0, TRIMD);
1538
1539 /* Recv frame limit set register */
1540 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1541 RFLR);
1542
1543 sh_eth_modify(ndev, EESR, 0, 0);
1544 mdp->irq_enabled = true;
1545 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1546
1547 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1548 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1549 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1550 ECMR_TE | ECMR_RE, ECMR);
1551
1552 if (mdp->cd->set_rate)
1553 mdp->cd->set_rate(ndev);
1554
1555 /* E-MAC Status Register clear */
1556 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1557
1558 /* E-MAC Interrupt Enable register */
1559 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1560
1561 /* Set MAC address */
1562 update_mac_address(ndev);
1563
1564 /* mask reset */
1565 if (mdp->cd->apr)
1566 sh_eth_write(ndev, 1, APR);
1567 if (mdp->cd->mpr)
1568 sh_eth_write(ndev, 1, MPR);
1569 if (mdp->cd->tpauser)
1570 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1571
1572 /* Setting the Rx mode will start the Rx process. */
1573 sh_eth_write(ndev, EDRRR_R, EDRRR);
1574
1575 return ret;
1576}
1577
1578static void sh_eth_dev_exit(struct net_device *ndev)
1579{
1580 struct sh_eth_private *mdp = netdev_priv(ndev);
1581 int i;
1582
1583 /* Deactivate all TX descriptors, so DMA should stop at next
1584 * packet boundary if it's currently running
1585 */
1586 for (i = 0; i < mdp->num_tx_ring; i++)
1587 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1588
1589 /* Disable TX FIFO egress to MAC */
1590 sh_eth_rcv_snd_disable(ndev);
1591
1592 /* Stop RX DMA at next packet boundary */
1593 sh_eth_write(ndev, 0, EDRRR);
1594
1595 /* Aside from TX DMA, we can't tell when the hardware is
1596 * really stopped, so we need to reset to make sure.
1597 * Before doing that, wait for long enough to *probably*
1598 * finish transmitting the last packet and poll stats.
1599 */
1600 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1601 sh_eth_get_stats(ndev);
1602 mdp->cd->soft_reset(ndev);
1603
1604 /* Set the RMII mode again if required */
1605 if (mdp->cd->rmiimode)
1606 sh_eth_write(ndev, 0x1, RMIIMODE);
1607
1608 /* Set MAC address again */
1609 update_mac_address(ndev);
1610}
1611
1612static void sh_eth_rx_csum(struct sk_buff *skb)
1613{
1614 u8 *hw_csum;
1615
1616 /* The hardware checksum is 2 bytes appended to packet data */
1617 if (unlikely(skb->len < sizeof(__sum16)))
1618 return;
1619 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1620 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1621 skb->ip_summed = CHECKSUM_COMPLETE;
1622 skb_trim(skb, skb->len - sizeof(__sum16));
1623}
1624
1625/* Packet receive function */
1626static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1627{
1628 struct sh_eth_private *mdp = netdev_priv(ndev);
1629 struct sh_eth_rxdesc *rxdesc;
1630
1631 int entry = mdp->cur_rx % mdp->num_rx_ring;
1632 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1633 int limit;
1634 struct sk_buff *skb;
1635 u32 desc_status;
1636 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1637 dma_addr_t dma_addr;
1638 u16 pkt_len;
1639 u32 buf_len;
1640
1641 boguscnt = min(boguscnt, *quota);
1642 limit = boguscnt;
1643 rxdesc = &mdp->rx_ring[entry];
1644 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1645 /* RACT bit must be checked before all the following reads */
1646 dma_rmb();
1647 desc_status = le32_to_cpu(rxdesc->status);
1648 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1649
1650 if (--boguscnt < 0)
1651 break;
1652
1653 netif_info(mdp, rx_status, ndev,
1654 "rx entry %d status 0x%08x len %d\n",
1655 entry, desc_status, pkt_len);
1656
1657 if (!(desc_status & RDFEND))
1658 ndev->stats.rx_length_errors++;
1659
1660 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1661 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1662 * bit 0. However, in case of the R8A7740 and R7S72100
1663 * the RFS bits are from bit 25 to bit 16. So, the
1664 * driver needs right shifting by 16.
1665 */
1666 if (mdp->cd->csmr)
1667 desc_status >>= 16;
1668
1669 skb = mdp->rx_skbuff[entry];
1670 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1671 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1672 ndev->stats.rx_errors++;
1673 if (desc_status & RD_RFS1)
1674 ndev->stats.rx_crc_errors++;
1675 if (desc_status & RD_RFS2)
1676 ndev->stats.rx_frame_errors++;
1677 if (desc_status & RD_RFS3)
1678 ndev->stats.rx_length_errors++;
1679 if (desc_status & RD_RFS4)
1680 ndev->stats.rx_length_errors++;
1681 if (desc_status & RD_RFS6)
1682 ndev->stats.rx_missed_errors++;
1683 if (desc_status & RD_RFS10)
1684 ndev->stats.rx_over_errors++;
1685 } else if (skb) {
1686 dma_addr = le32_to_cpu(rxdesc->addr);
1687 if (!mdp->cd->hw_swap)
1688 sh_eth_soft_swap(
1689 phys_to_virt(ALIGN(dma_addr, 4)),
1690 pkt_len + 2);
1691 mdp->rx_skbuff[entry] = NULL;
1692 if (mdp->cd->rpadir)
1693 skb_reserve(skb, NET_IP_ALIGN);
1694 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1695 ALIGN(mdp->rx_buf_sz, 32),
1696 DMA_FROM_DEVICE);
1697 skb_put(skb, pkt_len);
1698 skb->protocol = eth_type_trans(skb, ndev);
1699 if (ndev->features & NETIF_F_RXCSUM)
1700 sh_eth_rx_csum(skb);
1701 netif_receive_skb(skb);
1702 ndev->stats.rx_packets++;
1703 ndev->stats.rx_bytes += pkt_len;
1704 if (desc_status & RD_RFS8)
1705 ndev->stats.multicast++;
1706 }
1707 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1708 rxdesc = &mdp->rx_ring[entry];
1709 }
1710
1711 /* Refill the Rx ring buffers. */
1712 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1713 entry = mdp->dirty_rx % mdp->num_rx_ring;
1714 rxdesc = &mdp->rx_ring[entry];
1715 /* The size of the buffer is 32 byte boundary. */
1716 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1717 rxdesc->len = cpu_to_le32(buf_len << 16);
1718
1719 if (mdp->rx_skbuff[entry] == NULL) {
1720 skb = netdev_alloc_skb(ndev, skbuff_size);
1721 if (skb == NULL)
1722 break; /* Better luck next round. */
1723 sh_eth_set_receive_align(skb);
1724 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1725 buf_len, DMA_FROM_DEVICE);
1726 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1727 kfree_skb(skb);
1728 break;
1729 }
1730 mdp->rx_skbuff[entry] = skb;
1731
1732 skb_checksum_none_assert(skb);
1733 rxdesc->addr = cpu_to_le32(dma_addr);
1734 }
1735 dma_wmb(); /* RACT bit must be set after all the above writes */
1736 if (entry >= mdp->num_rx_ring - 1)
1737 rxdesc->status |=
1738 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1739 else
1740 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1741 }
1742
1743 /* Restart Rx engine if stopped. */
1744 /* If we don't need to check status, don't. -KDU */
1745 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1746 /* fix the values for the next receiving if RDE is set */
1747 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1748 u32 count = (sh_eth_read(ndev, RDFAR) -
1749 sh_eth_read(ndev, RDLAR)) >> 4;
1750
1751 mdp->cur_rx = count;
1752 mdp->dirty_rx = count;
1753 }
1754 sh_eth_write(ndev, EDRRR_R, EDRRR);
1755 }
1756
1757 *quota -= limit - boguscnt - 1;
1758
1759 return *quota <= 0;
1760}
1761
1762static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1763{
1764 /* disable tx and rx */
1765 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1766}
1767
1768static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1769{
1770 /* enable tx and rx */
1771 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1772}
1773
1774/* E-MAC interrupt handler */
1775static void sh_eth_emac_interrupt(struct net_device *ndev)
1776{
1777 struct sh_eth_private *mdp = netdev_priv(ndev);
1778 u32 felic_stat;
1779 u32 link_stat;
1780
1781 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1782 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1783 if (felic_stat & ECSR_ICD)
1784 ndev->stats.tx_carrier_errors++;
1785 if (felic_stat & ECSR_MPD)
1786 pm_wakeup_event(&mdp->pdev->dev, 0);
1787 if (felic_stat & ECSR_LCHNG) {
1788 /* Link Changed */
1789 if (mdp->cd->no_psr || mdp->no_ether_link)
1790 return;
1791 link_stat = sh_eth_read(ndev, PSR);
1792 if (mdp->ether_link_active_low)
1793 link_stat = ~link_stat;
1794 if (!(link_stat & PHY_ST_LINK)) {
1795 sh_eth_rcv_snd_disable(ndev);
1796 } else {
1797 /* Link Up */
1798 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1799 /* clear int */
1800 sh_eth_modify(ndev, ECSR, 0, 0);
1801 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1802 /* enable tx and rx */
1803 sh_eth_rcv_snd_enable(ndev);
1804 }
1805 }
1806}
1807
1808/* error control function */
1809static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1810{
1811 struct sh_eth_private *mdp = netdev_priv(ndev);
1812 u32 mask;
1813
1814 if (intr_status & EESR_TWB) {
1815 /* Unused write back interrupt */
1816 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1817 ndev->stats.tx_aborted_errors++;
1818 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1819 }
1820 }
1821
1822 if (intr_status & EESR_RABT) {
1823 /* Receive Abort int */
1824 if (intr_status & EESR_RFRMER) {
1825 /* Receive Frame Overflow int */
1826 ndev->stats.rx_frame_errors++;
1827 }
1828 }
1829
1830 if (intr_status & EESR_TDE) {
1831 /* Transmit Descriptor Empty int */
1832 ndev->stats.tx_fifo_errors++;
1833 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1834 }
1835
1836 if (intr_status & EESR_TFE) {
1837 /* FIFO under flow */
1838 ndev->stats.tx_fifo_errors++;
1839 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1840 }
1841
1842 if (intr_status & EESR_RDE) {
1843 /* Receive Descriptor Empty int */
1844 ndev->stats.rx_over_errors++;
1845 }
1846
1847 if (intr_status & EESR_RFE) {
1848 /* Receive FIFO Overflow int */
1849 ndev->stats.rx_fifo_errors++;
1850 }
1851
1852 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1853 /* Address Error */
1854 ndev->stats.tx_fifo_errors++;
1855 netif_err(mdp, tx_err, ndev, "Address Error\n");
1856 }
1857
1858 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1859 if (mdp->cd->no_ade)
1860 mask &= ~EESR_ADE;
1861 if (intr_status & mask) {
1862 /* Tx error */
1863 u32 edtrr = sh_eth_read(ndev, EDTRR);
1864
1865 /* dmesg */
1866 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1867 intr_status, mdp->cur_tx, mdp->dirty_tx,
1868 (u32)ndev->state, edtrr);
1869 /* dirty buffer free */
1870 sh_eth_tx_free(ndev, true);
1871
1872 /* SH7712 BUG */
1873 if (edtrr ^ mdp->cd->edtrr_trns) {
1874 /* tx dma start */
1875 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1876 }
1877 /* wakeup */
1878 netif_wake_queue(ndev);
1879 }
1880}
1881
1882static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1883{
1884 struct net_device *ndev = netdev;
1885 struct sh_eth_private *mdp = netdev_priv(ndev);
1886 struct sh_eth_cpu_data *cd = mdp->cd;
1887 irqreturn_t ret = IRQ_NONE;
1888 u32 intr_status, intr_enable;
1889
1890 spin_lock(&mdp->lock);
1891
1892 /* Get interrupt status */
1893 intr_status = sh_eth_read(ndev, EESR);
1894 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1895 * enabled since it's the one that comes thru regardless of the mask,
1896 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1897 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1898 * bit...
1899 */
1900 intr_enable = sh_eth_read(ndev, EESIPR);
1901 intr_status &= intr_enable | EESIPR_ECIIP;
1902 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1903 cd->eesr_err_check))
1904 ret = IRQ_HANDLED;
1905 else
1906 goto out;
1907
1908 if (unlikely(!mdp->irq_enabled)) {
1909 sh_eth_write(ndev, 0, EESIPR);
1910 goto out;
1911 }
1912
1913 if (intr_status & EESR_RX_CHECK) {
1914 if (napi_schedule_prep(&mdp->napi)) {
1915 /* Mask Rx interrupts */
1916 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1917 EESIPR);
1918 __napi_schedule(&mdp->napi);
1919 } else {
1920 netdev_warn(ndev,
1921 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1922 intr_status, intr_enable);
1923 }
1924 }
1925
1926 /* Tx Check */
1927 if (intr_status & cd->tx_check) {
1928 /* Clear Tx interrupts */
1929 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1930
1931 sh_eth_tx_free(ndev, true);
1932 netif_wake_queue(ndev);
1933 }
1934
1935 /* E-MAC interrupt */
1936 if (intr_status & EESR_ECI)
1937 sh_eth_emac_interrupt(ndev);
1938
1939 if (intr_status & cd->eesr_err_check) {
1940 /* Clear error interrupts */
1941 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1942
1943 sh_eth_error(ndev, intr_status);
1944 }
1945
1946out:
1947 spin_unlock(&mdp->lock);
1948
1949 return ret;
1950}
1951
1952static int sh_eth_poll(struct napi_struct *napi, int budget)
1953{
1954 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1955 napi);
1956 struct net_device *ndev = napi->dev;
1957 int quota = budget;
1958 u32 intr_status;
1959
1960 for (;;) {
1961 intr_status = sh_eth_read(ndev, EESR);
1962 if (!(intr_status & EESR_RX_CHECK))
1963 break;
1964 /* Clear Rx interrupts */
1965 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1966
1967 if (sh_eth_rx(ndev, intr_status, &quota))
1968 goto out;
1969 }
1970
1971 napi_complete(napi);
1972
1973 /* Reenable Rx interrupts */
1974 if (mdp->irq_enabled)
1975 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1976out:
1977 return budget - quota;
1978}
1979
1980/* PHY state control function */
1981static void sh_eth_adjust_link(struct net_device *ndev)
1982{
1983 struct sh_eth_private *mdp = netdev_priv(ndev);
1984 struct phy_device *phydev = ndev->phydev;
1985 unsigned long flags;
1986 int new_state = 0;
1987
1988 spin_lock_irqsave(&mdp->lock, flags);
1989
1990 /* Disable TX and RX right over here, if E-MAC change is ignored */
1991 if (mdp->cd->no_psr || mdp->no_ether_link)
1992 sh_eth_rcv_snd_disable(ndev);
1993
1994 if (phydev->link) {
1995 if (phydev->duplex != mdp->duplex) {
1996 new_state = 1;
1997 mdp->duplex = phydev->duplex;
1998 if (mdp->cd->set_duplex)
1999 mdp->cd->set_duplex(ndev);
2000 }
2001
2002 if (phydev->speed != mdp->speed) {
2003 new_state = 1;
2004 mdp->speed = phydev->speed;
2005 if (mdp->cd->set_rate)
2006 mdp->cd->set_rate(ndev);
2007 }
2008 if (!mdp->link) {
2009 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
2010 new_state = 1;
2011 mdp->link = phydev->link;
2012 }
2013 } else if (mdp->link) {
2014 new_state = 1;
2015 mdp->link = 0;
2016 mdp->speed = 0;
2017 mdp->duplex = -1;
2018 }
2019
2020 /* Enable TX and RX right over here, if E-MAC change is ignored */
2021 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2022 sh_eth_rcv_snd_enable(ndev);
2023
2024 spin_unlock_irqrestore(&mdp->lock, flags);
2025
2026 if (new_state && netif_msg_link(mdp))
2027 phy_print_status(phydev);
2028}
2029
2030/* PHY init function */
2031static int sh_eth_phy_init(struct net_device *ndev)
2032{
2033 struct device_node *np = ndev->dev.parent->of_node;
2034 struct sh_eth_private *mdp = netdev_priv(ndev);
2035 struct phy_device *phydev;
2036
2037 mdp->link = 0;
2038 mdp->speed = 0;
2039 mdp->duplex = -1;
2040
2041 /* Try connect to PHY */
2042 if (np) {
2043 struct device_node *pn;
2044
2045 pn = of_parse_phandle(np, "phy-handle", 0);
2046 phydev = of_phy_connect(ndev, pn,
2047 sh_eth_adjust_link, 0,
2048 mdp->phy_interface);
2049
2050 of_node_put(pn);
2051 if (!phydev)
2052 phydev = ERR_PTR(-ENOENT);
2053 } else {
2054 char phy_id[MII_BUS_ID_SIZE + 3];
2055
2056 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2057 mdp->mii_bus->id, mdp->phy_id);
2058
2059 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2060 mdp->phy_interface);
2061 }
2062
2063 if (IS_ERR(phydev)) {
2064 netdev_err(ndev, "failed to connect PHY\n");
2065 return PTR_ERR(phydev);
2066 }
2067
2068 /* mask with MAC supported features */
2069 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2070 int err = phy_set_max_speed(phydev, SPEED_100);
2071 if (err) {
2072 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2073 phy_disconnect(phydev);
2074 return err;
2075 }
2076 }
2077
2078 phy_attached_info(phydev);
2079
2080 return 0;
2081}
2082
2083/* PHY control start function */
2084static int sh_eth_phy_start(struct net_device *ndev)
2085{
2086 int ret;
2087
2088 ret = sh_eth_phy_init(ndev);
2089 if (ret)
2090 return ret;
2091
2092 phy_start(ndev->phydev);
2093
2094 return 0;
2095}
2096
2097/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2098 * version must be bumped as well. Just adding registers up to that
2099 * limit is fine, as long as the existing register indices don't
2100 * change.
2101 */
2102#define SH_ETH_REG_DUMP_VERSION 1
2103#define SH_ETH_REG_DUMP_MAX_REGS 256
2104
2105static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2106{
2107 struct sh_eth_private *mdp = netdev_priv(ndev);
2108 struct sh_eth_cpu_data *cd = mdp->cd;
2109 u32 *valid_map;
2110 size_t len;
2111
2112 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2113
2114 /* Dump starts with a bitmap that tells ethtool which
2115 * registers are defined for this chip.
2116 */
2117 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2118 if (buf) {
2119 valid_map = buf;
2120 buf += len;
2121 } else {
2122 valid_map = NULL;
2123 }
2124
2125 /* Add a register to the dump, if it has a defined offset.
2126 * This automatically skips most undefined registers, but for
2127 * some it is also necessary to check a capability flag in
2128 * struct sh_eth_cpu_data.
2129 */
2130#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2131#define add_reg_from(reg, read_expr) do { \
2132 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2133 if (buf) { \
2134 mark_reg_valid(reg); \
2135 *buf++ = read_expr; \
2136 } \
2137 ++len; \
2138 } \
2139 } while (0)
2140#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2141#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2142
2143 add_reg(EDSR);
2144 add_reg(EDMR);
2145 add_reg(EDTRR);
2146 add_reg(EDRRR);
2147 add_reg(EESR);
2148 add_reg(EESIPR);
2149 add_reg(TDLAR);
2150 add_reg(TDFAR);
2151 add_reg(TDFXR);
2152 add_reg(TDFFR);
2153 add_reg(RDLAR);
2154 add_reg(RDFAR);
2155 add_reg(RDFXR);
2156 add_reg(RDFFR);
2157 add_reg(TRSCER);
2158 add_reg(RMFCR);
2159 add_reg(TFTR);
2160 add_reg(FDR);
2161 add_reg(RMCR);
2162 add_reg(TFUCR);
2163 add_reg(RFOCR);
2164 if (cd->rmiimode)
2165 add_reg(RMIIMODE);
2166 add_reg(FCFTR);
2167 if (cd->rpadir)
2168 add_reg(RPADIR);
2169 if (!cd->no_trimd)
2170 add_reg(TRIMD);
2171 add_reg(ECMR);
2172 add_reg(ECSR);
2173 add_reg(ECSIPR);
2174 add_reg(PIR);
2175 if (!cd->no_psr)
2176 add_reg(PSR);
2177 add_reg(RDMLR);
2178 add_reg(RFLR);
2179 add_reg(IPGR);
2180 if (cd->apr)
2181 add_reg(APR);
2182 if (cd->mpr)
2183 add_reg(MPR);
2184 add_reg(RFCR);
2185 add_reg(RFCF);
2186 if (cd->tpauser)
2187 add_reg(TPAUSER);
2188 add_reg(TPAUSECR);
2189 add_reg(GECMR);
2190 if (cd->bculr)
2191 add_reg(BCULR);
2192 add_reg(MAHR);
2193 add_reg(MALR);
2194 add_reg(TROCR);
2195 add_reg(CDCR);
2196 add_reg(LCCR);
2197 add_reg(CNDCR);
2198 add_reg(CEFCR);
2199 add_reg(FRECR);
2200 add_reg(TSFRCR);
2201 add_reg(TLFRCR);
2202 add_reg(CERCR);
2203 add_reg(CEECR);
2204 add_reg(MAFCR);
2205 if (cd->rtrate)
2206 add_reg(RTRATE);
2207 if (cd->csmr)
2208 add_reg(CSMR);
2209 if (cd->select_mii)
2210 add_reg(RMII_MII);
2211 if (cd->tsu) {
2212 add_tsu_reg(ARSTR);
2213 add_tsu_reg(TSU_CTRST);
2214 if (cd->dual_port) {
2215 add_tsu_reg(TSU_FWEN0);
2216 add_tsu_reg(TSU_FWEN1);
2217 add_tsu_reg(TSU_FCM);
2218 add_tsu_reg(TSU_BSYSL0);
2219 add_tsu_reg(TSU_BSYSL1);
2220 add_tsu_reg(TSU_PRISL0);
2221 add_tsu_reg(TSU_PRISL1);
2222 add_tsu_reg(TSU_FWSL0);
2223 add_tsu_reg(TSU_FWSL1);
2224 }
2225 add_tsu_reg(TSU_FWSLC);
2226 if (cd->dual_port) {
2227 add_tsu_reg(TSU_QTAGM0);
2228 add_tsu_reg(TSU_QTAGM1);
2229 add_tsu_reg(TSU_FWSR);
2230 add_tsu_reg(TSU_FWINMK);
2231 add_tsu_reg(TSU_ADQT0);
2232 add_tsu_reg(TSU_ADQT1);
2233 add_tsu_reg(TSU_VTAG0);
2234 add_tsu_reg(TSU_VTAG1);
2235 }
2236 add_tsu_reg(TSU_ADSBSY);
2237 add_tsu_reg(TSU_TEN);
2238 add_tsu_reg(TSU_POST1);
2239 add_tsu_reg(TSU_POST2);
2240 add_tsu_reg(TSU_POST3);
2241 add_tsu_reg(TSU_POST4);
2242 /* This is the start of a table, not just a single register. */
2243 if (buf) {
2244 unsigned int i;
2245
2246 mark_reg_valid(TSU_ADRH0);
2247 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2248 *buf++ = ioread32(mdp->tsu_addr +
2249 mdp->reg_offset[TSU_ADRH0] +
2250 i * 4);
2251 }
2252 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2253 }
2254
2255#undef mark_reg_valid
2256#undef add_reg_from
2257#undef add_reg
2258#undef add_tsu_reg
2259
2260 return len * 4;
2261}
2262
2263static int sh_eth_get_regs_len(struct net_device *ndev)
2264{
2265 return __sh_eth_get_regs(ndev, NULL);
2266}
2267
2268static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2269 void *buf)
2270{
2271 struct sh_eth_private *mdp = netdev_priv(ndev);
2272
2273 regs->version = SH_ETH_REG_DUMP_VERSION;
2274
2275 pm_runtime_get_sync(&mdp->pdev->dev);
2276 __sh_eth_get_regs(ndev, buf);
2277 pm_runtime_put_sync(&mdp->pdev->dev);
2278}
2279
2280static u32 sh_eth_get_msglevel(struct net_device *ndev)
2281{
2282 struct sh_eth_private *mdp = netdev_priv(ndev);
2283 return mdp->msg_enable;
2284}
2285
2286static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2287{
2288 struct sh_eth_private *mdp = netdev_priv(ndev);
2289 mdp->msg_enable = value;
2290}
2291
2292static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2293 "rx_current", "tx_current",
2294 "rx_dirty", "tx_dirty",
2295};
2296#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2297
2298static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2299{
2300 switch (sset) {
2301 case ETH_SS_STATS:
2302 return SH_ETH_STATS_LEN;
2303 default:
2304 return -EOPNOTSUPP;
2305 }
2306}
2307
2308static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2309 struct ethtool_stats *stats, u64 *data)
2310{
2311 struct sh_eth_private *mdp = netdev_priv(ndev);
2312 int i = 0;
2313
2314 /* device-specific stats */
2315 data[i++] = mdp->cur_rx;
2316 data[i++] = mdp->cur_tx;
2317 data[i++] = mdp->dirty_rx;
2318 data[i++] = mdp->dirty_tx;
2319}
2320
2321static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2322{
2323 switch (stringset) {
2324 case ETH_SS_STATS:
2325 memcpy(data, sh_eth_gstrings_stats,
2326 sizeof(sh_eth_gstrings_stats));
2327 break;
2328 }
2329}
2330
2331static void sh_eth_get_ringparam(struct net_device *ndev,
2332 struct ethtool_ringparam *ring)
2333{
2334 struct sh_eth_private *mdp = netdev_priv(ndev);
2335
2336 ring->rx_max_pending = RX_RING_MAX;
2337 ring->tx_max_pending = TX_RING_MAX;
2338 ring->rx_pending = mdp->num_rx_ring;
2339 ring->tx_pending = mdp->num_tx_ring;
2340}
2341
2342static int sh_eth_set_ringparam(struct net_device *ndev,
2343 struct ethtool_ringparam *ring)
2344{
2345 struct sh_eth_private *mdp = netdev_priv(ndev);
2346 int ret;
2347
2348 if (ring->tx_pending > TX_RING_MAX ||
2349 ring->rx_pending > RX_RING_MAX ||
2350 ring->tx_pending < TX_RING_MIN ||
2351 ring->rx_pending < RX_RING_MIN)
2352 return -EINVAL;
2353 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2354 return -EINVAL;
2355
2356 if (netif_running(ndev)) {
2357 netif_device_detach(ndev);
2358 netif_tx_disable(ndev);
2359
2360 /* Serialise with the interrupt handler and NAPI, then
2361 * disable interrupts. We have to clear the
2362 * irq_enabled flag first to ensure that interrupts
2363 * won't be re-enabled.
2364 */
2365 mdp->irq_enabled = false;
2366 synchronize_irq(ndev->irq);
2367 napi_synchronize(&mdp->napi);
2368 sh_eth_write(ndev, 0x0000, EESIPR);
2369
2370 sh_eth_dev_exit(ndev);
2371
2372 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2373 sh_eth_ring_free(ndev);
2374 }
2375
2376 /* Set new parameters */
2377 mdp->num_rx_ring = ring->rx_pending;
2378 mdp->num_tx_ring = ring->tx_pending;
2379
2380 if (netif_running(ndev)) {
2381 ret = sh_eth_ring_init(ndev);
2382 if (ret < 0) {
2383 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2384 __func__);
2385 return ret;
2386 }
2387 ret = sh_eth_dev_init(ndev);
2388 if (ret < 0) {
2389 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2390 __func__);
2391 return ret;
2392 }
2393
2394 netif_device_attach(ndev);
2395 }
2396
2397 return 0;
2398}
2399
2400static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2401{
2402 struct sh_eth_private *mdp = netdev_priv(ndev);
2403
2404 wol->supported = 0;
2405 wol->wolopts = 0;
2406
2407 if (mdp->cd->magic) {
2408 wol->supported = WAKE_MAGIC;
2409 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2410 }
2411}
2412
2413static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2414{
2415 struct sh_eth_private *mdp = netdev_priv(ndev);
2416
2417 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2418 return -EOPNOTSUPP;
2419
2420 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2421
2422 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2423
2424 return 0;
2425}
2426
2427static const struct ethtool_ops sh_eth_ethtool_ops = {
2428 .get_regs_len = sh_eth_get_regs_len,
2429 .get_regs = sh_eth_get_regs,
2430 .nway_reset = phy_ethtool_nway_reset,
2431 .get_msglevel = sh_eth_get_msglevel,
2432 .set_msglevel = sh_eth_set_msglevel,
2433 .get_link = ethtool_op_get_link,
2434 .get_strings = sh_eth_get_strings,
2435 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2436 .get_sset_count = sh_eth_get_sset_count,
2437 .get_ringparam = sh_eth_get_ringparam,
2438 .set_ringparam = sh_eth_set_ringparam,
2439 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2440 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2441 .get_wol = sh_eth_get_wol,
2442 .set_wol = sh_eth_set_wol,
2443};
2444
2445/* network device open function */
2446static int sh_eth_open(struct net_device *ndev)
2447{
2448 struct sh_eth_private *mdp = netdev_priv(ndev);
2449 int ret;
2450
2451 pm_runtime_get_sync(&mdp->pdev->dev);
2452
2453 napi_enable(&mdp->napi);
2454
2455 ret = request_irq(ndev->irq, sh_eth_interrupt,
2456 mdp->cd->irq_flags, ndev->name, ndev);
2457 if (ret) {
2458 netdev_err(ndev, "Can not assign IRQ number\n");
2459 goto out_napi_off;
2460 }
2461
2462 /* Descriptor set */
2463 ret = sh_eth_ring_init(ndev);
2464 if (ret)
2465 goto out_free_irq;
2466
2467 /* device init */
2468 ret = sh_eth_dev_init(ndev);
2469 if (ret)
2470 goto out_free_irq;
2471
2472 /* PHY control start*/
2473 ret = sh_eth_phy_start(ndev);
2474 if (ret)
2475 goto out_free_irq;
2476
2477 netif_start_queue(ndev);
2478
2479 mdp->is_opened = 1;
2480
2481 return ret;
2482
2483out_free_irq:
2484 free_irq(ndev->irq, ndev);
2485out_napi_off:
2486 napi_disable(&mdp->napi);
2487 pm_runtime_put_sync(&mdp->pdev->dev);
2488 return ret;
2489}
2490
2491/* Timeout function */
2492static void sh_eth_tx_timeout(struct net_device *ndev)
2493{
2494 struct sh_eth_private *mdp = netdev_priv(ndev);
2495 struct sh_eth_rxdesc *rxdesc;
2496 int i;
2497
2498 netif_stop_queue(ndev);
2499
2500 netif_err(mdp, timer, ndev,
2501 "transmit timed out, status %8.8x, resetting...\n",
2502 sh_eth_read(ndev, EESR));
2503
2504 /* tx_errors count up */
2505 ndev->stats.tx_errors++;
2506
2507 /* Free all the skbuffs in the Rx queue. */
2508 for (i = 0; i < mdp->num_rx_ring; i++) {
2509 rxdesc = &mdp->rx_ring[i];
2510 rxdesc->status = cpu_to_le32(0);
2511 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2512 dev_kfree_skb(mdp->rx_skbuff[i]);
2513 mdp->rx_skbuff[i] = NULL;
2514 }
2515 for (i = 0; i < mdp->num_tx_ring; i++) {
2516 dev_kfree_skb(mdp->tx_skbuff[i]);
2517 mdp->tx_skbuff[i] = NULL;
2518 }
2519
2520 /* device init */
2521 sh_eth_dev_init(ndev);
2522
2523 netif_start_queue(ndev);
2524}
2525
2526/* Packet transmit function */
2527static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2528{
2529 struct sh_eth_private *mdp = netdev_priv(ndev);
2530 struct sh_eth_txdesc *txdesc;
2531 dma_addr_t dma_addr;
2532 u32 entry;
2533 unsigned long flags;
2534
2535 spin_lock_irqsave(&mdp->lock, flags);
2536 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2537 if (!sh_eth_tx_free(ndev, true)) {
2538 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2539 netif_stop_queue(ndev);
2540 spin_unlock_irqrestore(&mdp->lock, flags);
2541 return NETDEV_TX_BUSY;
2542 }
2543 }
2544 spin_unlock_irqrestore(&mdp->lock, flags);
2545
2546 if (skb_put_padto(skb, ETH_ZLEN))
2547 return NETDEV_TX_OK;
2548
2549 entry = mdp->cur_tx % mdp->num_tx_ring;
2550 mdp->tx_skbuff[entry] = skb;
2551 txdesc = &mdp->tx_ring[entry];
2552 /* soft swap. */
2553 if (!mdp->cd->hw_swap)
2554 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2555 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2556 DMA_TO_DEVICE);
2557 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2558 kfree_skb(skb);
2559 return NETDEV_TX_OK;
2560 }
2561 txdesc->addr = cpu_to_le32(dma_addr);
2562 txdesc->len = cpu_to_le32(skb->len << 16);
2563
2564 dma_wmb(); /* TACT bit must be set after all the above writes */
2565 if (entry >= mdp->num_tx_ring - 1)
2566 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2567 else
2568 txdesc->status |= cpu_to_le32(TD_TACT);
2569
2570 wmb(); /* cur_tx must be incremented after TACT bit was set */
2571 mdp->cur_tx++;
2572
2573 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2574 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2575
2576 return NETDEV_TX_OK;
2577}
2578
2579/* The statistics registers have write-clear behaviour, which means we
2580 * will lose any increment between the read and write. We mitigate
2581 * this by only clearing when we read a non-zero value, so we will
2582 * never falsely report a total of zero.
2583 */
2584static void
2585sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2586{
2587 u32 delta = sh_eth_read(ndev, reg);
2588
2589 if (delta) {
2590 *stat += delta;
2591 sh_eth_write(ndev, 0, reg);
2592 }
2593}
2594
2595static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2596{
2597 struct sh_eth_private *mdp = netdev_priv(ndev);
2598
2599 if (mdp->cd->no_tx_cntrs)
2600 return &ndev->stats;
2601
2602 if (!mdp->is_opened)
2603 return &ndev->stats;
2604
2605 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2606 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2607 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2608
2609 if (mdp->cd->cexcr) {
2610 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2611 CERCR);
2612 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2613 CEECR);
2614 } else {
2615 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2616 CNDCR);
2617 }
2618
2619 return &ndev->stats;
2620}
2621
2622/* device close function */
2623static int sh_eth_close(struct net_device *ndev)
2624{
2625 struct sh_eth_private *mdp = netdev_priv(ndev);
2626
2627 netif_stop_queue(ndev);
2628
2629 /* Serialise with the interrupt handler and NAPI, then disable
2630 * interrupts. We have to clear the irq_enabled flag first to
2631 * ensure that interrupts won't be re-enabled.
2632 */
2633 mdp->irq_enabled = false;
2634 synchronize_irq(ndev->irq);
2635 napi_disable(&mdp->napi);
2636 sh_eth_write(ndev, 0x0000, EESIPR);
2637
2638 sh_eth_dev_exit(ndev);
2639
2640 /* PHY Disconnect */
2641 if (ndev->phydev) {
2642 phy_stop(ndev->phydev);
2643 phy_disconnect(ndev->phydev);
2644 }
2645
2646 free_irq(ndev->irq, ndev);
2647
2648 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2649 sh_eth_ring_free(ndev);
2650
2651 mdp->is_opened = 0;
2652
2653 pm_runtime_put(&mdp->pdev->dev);
2654
2655 return 0;
2656}
2657
2658/* ioctl to device function */
2659static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2660{
2661 struct phy_device *phydev = ndev->phydev;
2662
2663 if (!netif_running(ndev))
2664 return -EINVAL;
2665
2666 if (!phydev)
2667 return -ENODEV;
2668
2669 return phy_mii_ioctl(phydev, rq, cmd);
2670}
2671
2672static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2673{
2674 if (netif_running(ndev))
2675 return -EBUSY;
2676
2677 ndev->mtu = new_mtu;
2678 netdev_update_features(ndev);
2679
2680 return 0;
2681}
2682
2683/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2684static u32 sh_eth_tsu_get_post_mask(int entry)
2685{
2686 return 0x0f << (28 - ((entry % 8) * 4));
2687}
2688
2689static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2690{
2691 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2692}
2693
2694static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2695 int entry)
2696{
2697 struct sh_eth_private *mdp = netdev_priv(ndev);
2698 int reg = TSU_POST1 + entry / 8;
2699 u32 tmp;
2700
2701 tmp = sh_eth_tsu_read(mdp, reg);
2702 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2703}
2704
2705static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2706 int entry)
2707{
2708 struct sh_eth_private *mdp = netdev_priv(ndev);
2709 int reg = TSU_POST1 + entry / 8;
2710 u32 post_mask, ref_mask, tmp;
2711
2712 post_mask = sh_eth_tsu_get_post_mask(entry);
2713 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2714
2715 tmp = sh_eth_tsu_read(mdp, reg);
2716 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2717
2718 /* If other port enables, the function returns "true" */
2719 return tmp & ref_mask;
2720}
2721
2722static int sh_eth_tsu_busy(struct net_device *ndev)
2723{
2724 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2725 struct sh_eth_private *mdp = netdev_priv(ndev);
2726
2727 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2728 udelay(10);
2729 timeout--;
2730 if (timeout <= 0) {
2731 netdev_err(ndev, "%s: timeout\n", __func__);
2732 return -ETIMEDOUT;
2733 }
2734 }
2735
2736 return 0;
2737}
2738
2739static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2740 const u8 *addr)
2741{
2742 struct sh_eth_private *mdp = netdev_priv(ndev);
2743 u32 val;
2744
2745 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2746 iowrite32(val, mdp->tsu_addr + offset);
2747 if (sh_eth_tsu_busy(ndev) < 0)
2748 return -EBUSY;
2749
2750 val = addr[4] << 8 | addr[5];
2751 iowrite32(val, mdp->tsu_addr + offset + 4);
2752 if (sh_eth_tsu_busy(ndev) < 0)
2753 return -EBUSY;
2754
2755 return 0;
2756}
2757
2758static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2759{
2760 struct sh_eth_private *mdp = netdev_priv(ndev);
2761 u32 val;
2762
2763 val = ioread32(mdp->tsu_addr + offset);
2764 addr[0] = (val >> 24) & 0xff;
2765 addr[1] = (val >> 16) & 0xff;
2766 addr[2] = (val >> 8) & 0xff;
2767 addr[3] = val & 0xff;
2768 val = ioread32(mdp->tsu_addr + offset + 4);
2769 addr[4] = (val >> 8) & 0xff;
2770 addr[5] = val & 0xff;
2771}
2772
2773
2774static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2775{
2776 struct sh_eth_private *mdp = netdev_priv(ndev);
2777 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2778 int i;
2779 u8 c_addr[ETH_ALEN];
2780
2781 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2782 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2783 if (ether_addr_equal(addr, c_addr))
2784 return i;
2785 }
2786
2787 return -ENOENT;
2788}
2789
2790static int sh_eth_tsu_find_empty(struct net_device *ndev)
2791{
2792 u8 blank[ETH_ALEN];
2793 int entry;
2794
2795 memset(blank, 0, sizeof(blank));
2796 entry = sh_eth_tsu_find_entry(ndev, blank);
2797 return (entry < 0) ? -ENOMEM : entry;
2798}
2799
2800static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2801 int entry)
2802{
2803 struct sh_eth_private *mdp = netdev_priv(ndev);
2804 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2805 int ret;
2806 u8 blank[ETH_ALEN];
2807
2808 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2809 ~(1 << (31 - entry)), TSU_TEN);
2810
2811 memset(blank, 0, sizeof(blank));
2812 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2813 if (ret < 0)
2814 return ret;
2815 return 0;
2816}
2817
2818static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2819{
2820 struct sh_eth_private *mdp = netdev_priv(ndev);
2821 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2822 int i, ret;
2823
2824 if (!mdp->cd->tsu)
2825 return 0;
2826
2827 i = sh_eth_tsu_find_entry(ndev, addr);
2828 if (i < 0) {
2829 /* No entry found, create one */
2830 i = sh_eth_tsu_find_empty(ndev);
2831 if (i < 0)
2832 return -ENOMEM;
2833 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2834 if (ret < 0)
2835 return ret;
2836
2837 /* Enable the entry */
2838 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2839 (1 << (31 - i)), TSU_TEN);
2840 }
2841
2842 /* Entry found or created, enable POST */
2843 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2844
2845 return 0;
2846}
2847
2848static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2849{
2850 struct sh_eth_private *mdp = netdev_priv(ndev);
2851 int i, ret;
2852
2853 if (!mdp->cd->tsu)
2854 return 0;
2855
2856 i = sh_eth_tsu_find_entry(ndev, addr);
2857 if (i) {
2858 /* Entry found */
2859 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2860 goto done;
2861
2862 /* Disable the entry if both ports was disabled */
2863 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2864 if (ret < 0)
2865 return ret;
2866 }
2867done:
2868 return 0;
2869}
2870
2871static int sh_eth_tsu_purge_all(struct net_device *ndev)
2872{
2873 struct sh_eth_private *mdp = netdev_priv(ndev);
2874 int i, ret;
2875
2876 if (!mdp->cd->tsu)
2877 return 0;
2878
2879 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2880 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2881 continue;
2882
2883 /* Disable the entry if both ports was disabled */
2884 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2885 if (ret < 0)
2886 return ret;
2887 }
2888
2889 return 0;
2890}
2891
2892static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2893{
2894 struct sh_eth_private *mdp = netdev_priv(ndev);
2895 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2896 u8 addr[ETH_ALEN];
2897 int i;
2898
2899 if (!mdp->cd->tsu)
2900 return;
2901
2902 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2903 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2904 if (is_multicast_ether_addr(addr))
2905 sh_eth_tsu_del_entry(ndev, addr);
2906 }
2907}
2908
2909/* Update promiscuous flag and multicast filter */
2910static void sh_eth_set_rx_mode(struct net_device *ndev)
2911{
2912 struct sh_eth_private *mdp = netdev_priv(ndev);
2913 u32 ecmr_bits;
2914 int mcast_all = 0;
2915 unsigned long flags;
2916
2917 spin_lock_irqsave(&mdp->lock, flags);
2918 /* Initial condition is MCT = 1, PRM = 0.
2919 * Depending on ndev->flags, set PRM or clear MCT
2920 */
2921 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2922 if (mdp->cd->tsu)
2923 ecmr_bits |= ECMR_MCT;
2924
2925 if (!(ndev->flags & IFF_MULTICAST)) {
2926 sh_eth_tsu_purge_mcast(ndev);
2927 mcast_all = 1;
2928 }
2929 if (ndev->flags & IFF_ALLMULTI) {
2930 sh_eth_tsu_purge_mcast(ndev);
2931 ecmr_bits &= ~ECMR_MCT;
2932 mcast_all = 1;
2933 }
2934
2935 if (ndev->flags & IFF_PROMISC) {
2936 sh_eth_tsu_purge_all(ndev);
2937 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2938 } else if (mdp->cd->tsu) {
2939 struct netdev_hw_addr *ha;
2940 netdev_for_each_mc_addr(ha, ndev) {
2941 if (mcast_all && is_multicast_ether_addr(ha->addr))
2942 continue;
2943
2944 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2945 if (!mcast_all) {
2946 sh_eth_tsu_purge_mcast(ndev);
2947 ecmr_bits &= ~ECMR_MCT;
2948 mcast_all = 1;
2949 }
2950 }
2951 }
2952 }
2953
2954 /* update the ethernet mode */
2955 sh_eth_write(ndev, ecmr_bits, ECMR);
2956
2957 spin_unlock_irqrestore(&mdp->lock, flags);
2958}
2959
2960static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2961{
2962 struct sh_eth_private *mdp = netdev_priv(ndev);
2963 unsigned long flags;
2964
2965 spin_lock_irqsave(&mdp->lock, flags);
2966
2967 /* Disable TX and RX */
2968 sh_eth_rcv_snd_disable(ndev);
2969
2970 /* Modify RX Checksum setting */
2971 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2972
2973 /* Enable TX and RX */
2974 sh_eth_rcv_snd_enable(ndev);
2975
2976 spin_unlock_irqrestore(&mdp->lock, flags);
2977}
2978
2979static int sh_eth_set_features(struct net_device *ndev,
2980 netdev_features_t features)
2981{
2982 netdev_features_t changed = ndev->features ^ features;
2983 struct sh_eth_private *mdp = netdev_priv(ndev);
2984
2985 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2986 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2987
2988 ndev->features = features;
2989
2990 return 0;
2991}
2992
2993static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2994{
2995 if (!mdp->port)
2996 return TSU_VTAG0;
2997 else
2998 return TSU_VTAG1;
2999}
3000
3001static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
3002 __be16 proto, u16 vid)
3003{
3004 struct sh_eth_private *mdp = netdev_priv(ndev);
3005 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3006
3007 if (unlikely(!mdp->cd->tsu))
3008 return -EPERM;
3009
3010 /* No filtering if vid = 0 */
3011 if (!vid)
3012 return 0;
3013
3014 mdp->vlan_num_ids++;
3015
3016 /* The controller has one VLAN tag HW filter. So, if the filter is
3017 * already enabled, the driver disables it and the filte
3018 */
3019 if (mdp->vlan_num_ids > 1) {
3020 /* disable VLAN filter */
3021 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3022 return 0;
3023 }
3024
3025 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
3026 vtag_reg_index);
3027
3028 return 0;
3029}
3030
3031static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
3032 __be16 proto, u16 vid)
3033{
3034 struct sh_eth_private *mdp = netdev_priv(ndev);
3035 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3036
3037 if (unlikely(!mdp->cd->tsu))
3038 return -EPERM;
3039
3040 /* No filtering if vid = 0 */
3041 if (!vid)
3042 return 0;
3043
3044 mdp->vlan_num_ids--;
3045 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3046
3047 return 0;
3048}
3049
3050/* SuperH's TSU register init function */
3051static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3052{
3053 if (!mdp->cd->dual_port) {
3054 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3055 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3056 TSU_FWSLC); /* Enable POST registers */
3057 return;
3058 }
3059
3060 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3061 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3062 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3063 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3064 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3065 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3066 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3067 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3068 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3069 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3070 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3071 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3072 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3073 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3074 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3075 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3076 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3077 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3078 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3079}
3080
3081/* MDIO bus release function */
3082static int sh_mdio_release(struct sh_eth_private *mdp)
3083{
3084 /* unregister mdio bus */
3085 mdiobus_unregister(mdp->mii_bus);
3086
3087 /* free bitbang info */
3088 free_mdio_bitbang(mdp->mii_bus);
3089
3090 return 0;
3091}
3092
3093/* MDIO bus init function */
3094static int sh_mdio_init(struct sh_eth_private *mdp,
3095 struct sh_eth_plat_data *pd)
3096{
3097 int ret;
3098 struct bb_info *bitbang;
3099 struct platform_device *pdev = mdp->pdev;
3100 struct device *dev = &mdp->pdev->dev;
3101
3102 /* create bit control struct for PHY */
3103 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3104 if (!bitbang)
3105 return -ENOMEM;
3106
3107 /* bitbang init */
3108 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3109 bitbang->set_gate = pd->set_mdio_gate;
3110 bitbang->ctrl.ops = &bb_ops;
3111
3112 /* MII controller setting */
3113 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3114 if (!mdp->mii_bus)
3115 return -ENOMEM;
3116
3117 /* Hook up MII support for ethtool */
3118 mdp->mii_bus->name = "sh_mii";
3119 mdp->mii_bus->parent = dev;
3120 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3121 pdev->name, pdev->id);
3122
3123 /* register MDIO bus */
3124 if (pd->phy_irq > 0)
3125 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3126
3127 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3128 if (ret)
3129 goto out_free_bus;
3130
3131 return 0;
3132
3133out_free_bus:
3134 free_mdio_bitbang(mdp->mii_bus);
3135 return ret;
3136}
3137
3138static const u16 *sh_eth_get_register_offset(int register_type)
3139{
3140 const u16 *reg_offset = NULL;
3141
3142 switch (register_type) {
3143 case SH_ETH_REG_GIGABIT:
3144 reg_offset = sh_eth_offset_gigabit;
3145 break;
3146 case SH_ETH_REG_FAST_RZ:
3147 reg_offset = sh_eth_offset_fast_rz;
3148 break;
3149 case SH_ETH_REG_FAST_RCAR:
3150 reg_offset = sh_eth_offset_fast_rcar;
3151 break;
3152 case SH_ETH_REG_FAST_SH4:
3153 reg_offset = sh_eth_offset_fast_sh4;
3154 break;
3155 case SH_ETH_REG_FAST_SH3_SH2:
3156 reg_offset = sh_eth_offset_fast_sh3_sh2;
3157 break;
3158 }
3159
3160 return reg_offset;
3161}
3162
3163static const struct net_device_ops sh_eth_netdev_ops = {
3164 .ndo_open = sh_eth_open,
3165 .ndo_stop = sh_eth_close,
3166 .ndo_start_xmit = sh_eth_start_xmit,
3167 .ndo_get_stats = sh_eth_get_stats,
3168 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3169 .ndo_tx_timeout = sh_eth_tx_timeout,
3170 .ndo_do_ioctl = sh_eth_do_ioctl,
3171 .ndo_change_mtu = sh_eth_change_mtu,
3172 .ndo_validate_addr = eth_validate_addr,
3173 .ndo_set_mac_address = eth_mac_addr,
3174 .ndo_set_features = sh_eth_set_features,
3175};
3176
3177static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3178 .ndo_open = sh_eth_open,
3179 .ndo_stop = sh_eth_close,
3180 .ndo_start_xmit = sh_eth_start_xmit,
3181 .ndo_get_stats = sh_eth_get_stats,
3182 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3183 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3184 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3185 .ndo_tx_timeout = sh_eth_tx_timeout,
3186 .ndo_do_ioctl = sh_eth_do_ioctl,
3187 .ndo_change_mtu = sh_eth_change_mtu,
3188 .ndo_validate_addr = eth_validate_addr,
3189 .ndo_set_mac_address = eth_mac_addr,
3190 .ndo_set_features = sh_eth_set_features,
3191};
3192
3193#ifdef CONFIG_OF
3194static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3195{
3196 struct device_node *np = dev->of_node;
3197 struct sh_eth_plat_data *pdata;
3198 const char *mac_addr;
3199 int ret;
3200
3201 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3202 if (!pdata)
3203 return NULL;
3204
3205 ret = of_get_phy_mode(np);
3206 if (ret < 0)
3207 return NULL;
3208 pdata->phy_interface = ret;
3209
3210 mac_addr = of_get_mac_address(np);
3211 if (!IS_ERR(mac_addr))
3212 ether_addr_copy(pdata->mac_addr, mac_addr);
3213
3214 pdata->no_ether_link =
3215 of_property_read_bool(np, "renesas,no-ether-link");
3216 pdata->ether_link_active_low =
3217 of_property_read_bool(np, "renesas,ether-link-active-low");
3218
3219 return pdata;
3220}
3221
3222static const struct of_device_id sh_eth_match_table[] = {
3223 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3224 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3225 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3226 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3227 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3228 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3229 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3230 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3231 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3232 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3233 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3234 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3235 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3236 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3237 { }
3238};
3239MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3240#else
3241static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3242{
3243 return NULL;
3244}
3245#endif
3246
3247static int sh_eth_drv_probe(struct platform_device *pdev)
3248{
3249 struct resource *res;
3250 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3251 const struct platform_device_id *id = platform_get_device_id(pdev);
3252 struct sh_eth_private *mdp;
3253 struct net_device *ndev;
3254 int ret;
3255
3256 /* get base addr */
3257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3258
3259 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3260 if (!ndev)
3261 return -ENOMEM;
3262
3263 pm_runtime_enable(&pdev->dev);
3264 pm_runtime_get_sync(&pdev->dev);
3265
3266 ret = platform_get_irq(pdev, 0);
3267 if (ret < 0)
3268 goto out_release;
3269 ndev->irq = ret;
3270
3271 SET_NETDEV_DEV(ndev, &pdev->dev);
3272
3273 mdp = netdev_priv(ndev);
3274 mdp->num_tx_ring = TX_RING_SIZE;
3275 mdp->num_rx_ring = RX_RING_SIZE;
3276 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3277 if (IS_ERR(mdp->addr)) {
3278 ret = PTR_ERR(mdp->addr);
3279 goto out_release;
3280 }
3281
3282 ndev->base_addr = res->start;
3283
3284 spin_lock_init(&mdp->lock);
3285 mdp->pdev = pdev;
3286
3287 if (pdev->dev.of_node)
3288 pd = sh_eth_parse_dt(&pdev->dev);
3289 if (!pd) {
3290 dev_err(&pdev->dev, "no platform data\n");
3291 ret = -EINVAL;
3292 goto out_release;
3293 }
3294
3295 /* get PHY ID */
3296 mdp->phy_id = pd->phy;
3297 mdp->phy_interface = pd->phy_interface;
3298 mdp->no_ether_link = pd->no_ether_link;
3299 mdp->ether_link_active_low = pd->ether_link_active_low;
3300
3301 /* set cpu data */
3302 if (id)
3303 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3304 else
3305 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3306
3307 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3308 if (!mdp->reg_offset) {
3309 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3310 mdp->cd->register_type);
3311 ret = -EINVAL;
3312 goto out_release;
3313 }
3314 sh_eth_set_default_cpu_data(mdp->cd);
3315
3316 /* User's manual states max MTU should be 2048 but due to the
3317 * alignment calculations in sh_eth_ring_init() the practical
3318 * MTU is a bit less. Maybe this can be optimized some more.
3319 */
3320 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3321 ndev->min_mtu = ETH_MIN_MTU;
3322
3323 if (mdp->cd->rx_csum) {
3324 ndev->features = NETIF_F_RXCSUM;
3325 ndev->hw_features = NETIF_F_RXCSUM;
3326 }
3327
3328 /* set function */
3329 if (mdp->cd->tsu)
3330 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3331 else
3332 ndev->netdev_ops = &sh_eth_netdev_ops;
3333 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3334 ndev->watchdog_timeo = TX_TIMEOUT;
3335
3336 /* debug message level */
3337 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3338
3339 /* read and set MAC address */
3340 read_mac_address(ndev, pd->mac_addr);
3341 if (!is_valid_ether_addr(ndev->dev_addr)) {
3342 dev_warn(&pdev->dev,
3343 "no valid MAC address supplied, using a random one.\n");
3344 eth_hw_addr_random(ndev);
3345 }
3346
3347 if (mdp->cd->tsu) {
3348 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3349 struct resource *rtsu;
3350
3351 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3352 if (!rtsu) {
3353 dev_err(&pdev->dev, "no TSU resource\n");
3354 ret = -ENODEV;
3355 goto out_release;
3356 }
3357 /* We can only request the TSU region for the first port
3358 * of the two sharing this TSU for the probe to succeed...
3359 */
3360 if (port == 0 &&
3361 !devm_request_mem_region(&pdev->dev, rtsu->start,
3362 resource_size(rtsu),
3363 dev_name(&pdev->dev))) {
3364 dev_err(&pdev->dev, "can't request TSU resource.\n");
3365 ret = -EBUSY;
3366 goto out_release;
3367 }
3368 /* ioremap the TSU registers */
3369 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3370 resource_size(rtsu));
3371 if (!mdp->tsu_addr) {
3372 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3373 ret = -ENOMEM;
3374 goto out_release;
3375 }
3376 mdp->port = port;
3377 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3378
3379 /* Need to init only the first port of the two sharing a TSU */
3380 if (port == 0) {
3381 if (mdp->cd->chip_reset)
3382 mdp->cd->chip_reset(ndev);
3383
3384 /* TSU init (Init only)*/
3385 sh_eth_tsu_init(mdp);
3386 }
3387 }
3388
3389 if (mdp->cd->rmiimode)
3390 sh_eth_write(ndev, 0x1, RMIIMODE);
3391
3392 /* MDIO bus init */
3393 ret = sh_mdio_init(mdp, pd);
3394 if (ret) {
3395 if (ret != -EPROBE_DEFER)
3396 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3397 goto out_release;
3398 }
3399
3400 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3401
3402 /* network device register */
3403 ret = register_netdev(ndev);
3404 if (ret)
3405 goto out_napi_del;
3406
3407 if (mdp->cd->magic)
3408 device_set_wakeup_capable(&pdev->dev, 1);
3409
3410 /* print device information */
3411 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3412 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3413
3414 pm_runtime_put(&pdev->dev);
3415 platform_set_drvdata(pdev, ndev);
3416
3417 return ret;
3418
3419out_napi_del:
3420 netif_napi_del(&mdp->napi);
3421 sh_mdio_release(mdp);
3422
3423out_release:
3424 /* net_dev free */
3425 free_netdev(ndev);
3426
3427 pm_runtime_put(&pdev->dev);
3428 pm_runtime_disable(&pdev->dev);
3429 return ret;
3430}
3431
3432static int sh_eth_drv_remove(struct platform_device *pdev)
3433{
3434 struct net_device *ndev = platform_get_drvdata(pdev);
3435 struct sh_eth_private *mdp = netdev_priv(ndev);
3436
3437 unregister_netdev(ndev);
3438 netif_napi_del(&mdp->napi);
3439 sh_mdio_release(mdp);
3440 pm_runtime_disable(&pdev->dev);
3441 free_netdev(ndev);
3442
3443 return 0;
3444}
3445
3446#ifdef CONFIG_PM
3447#ifdef CONFIG_PM_SLEEP
3448static int sh_eth_wol_setup(struct net_device *ndev)
3449{
3450 struct sh_eth_private *mdp = netdev_priv(ndev);
3451
3452 /* Only allow ECI interrupts */
3453 synchronize_irq(ndev->irq);
3454 napi_disable(&mdp->napi);
3455 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3456
3457 /* Enable MagicPacket */
3458 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3459
3460 return enable_irq_wake(ndev->irq);
3461}
3462
3463static int sh_eth_wol_restore(struct net_device *ndev)
3464{
3465 struct sh_eth_private *mdp = netdev_priv(ndev);
3466 int ret;
3467
3468 napi_enable(&mdp->napi);
3469
3470 /* Disable MagicPacket */
3471 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3472
3473 /* The device needs to be reset to restore MagicPacket logic
3474 * for next wakeup. If we close and open the device it will
3475 * both be reset and all registers restored. This is what
3476 * happens during suspend and resume without WoL enabled.
3477 */
3478 ret = sh_eth_close(ndev);
3479 if (ret < 0)
3480 return ret;
3481 ret = sh_eth_open(ndev);
3482 if (ret < 0)
3483 return ret;
3484
3485 return disable_irq_wake(ndev->irq);
3486}
3487
3488static int sh_eth_suspend(struct device *dev)
3489{
3490 struct net_device *ndev = dev_get_drvdata(dev);
3491 struct sh_eth_private *mdp = netdev_priv(ndev);
3492 int ret = 0;
3493
3494 if (!netif_running(ndev))
3495 return 0;
3496
3497 netif_device_detach(ndev);
3498
3499 if (mdp->wol_enabled)
3500 ret = sh_eth_wol_setup(ndev);
3501 else
3502 ret = sh_eth_close(ndev);
3503
3504 return ret;
3505}
3506
3507static int sh_eth_resume(struct device *dev)
3508{
3509 struct net_device *ndev = dev_get_drvdata(dev);
3510 struct sh_eth_private *mdp = netdev_priv(ndev);
3511 int ret = 0;
3512
3513 if (!netif_running(ndev))
3514 return 0;
3515
3516 if (mdp->wol_enabled)
3517 ret = sh_eth_wol_restore(ndev);
3518 else
3519 ret = sh_eth_open(ndev);
3520
3521 if (ret < 0)
3522 return ret;
3523
3524 netif_device_attach(ndev);
3525
3526 return ret;
3527}
3528#endif
3529
3530static int sh_eth_runtime_nop(struct device *dev)
3531{
3532 /* Runtime PM callback shared between ->runtime_suspend()
3533 * and ->runtime_resume(). Simply returns success.
3534 *
3535 * This driver re-initializes all registers after
3536 * pm_runtime_get_sync() anyway so there is no need
3537 * to save and restore registers here.
3538 */
3539 return 0;
3540}
3541
3542static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3543 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3544 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3545};
3546#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3547#else
3548#define SH_ETH_PM_OPS NULL
3549#endif
3550
3551static const struct platform_device_id sh_eth_id_table[] = {
3552 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3553 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3554 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3555 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3556 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3557 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3558 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3559 { }
3560};
3561MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3562
3563static struct platform_driver sh_eth_driver = {
3564 .probe = sh_eth_drv_probe,
3565 .remove = sh_eth_drv_remove,
3566 .id_table = sh_eth_id_table,
3567 .driver = {
3568 .name = CARDNAME,
3569 .pm = SH_ETH_PM_OPS,
3570 .of_match_table = of_match_ptr(sh_eth_match_table),
3571 },
3572};
3573
3574module_platform_driver(sh_eth_driver);
3575
3576MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3577MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3578MODULE_LICENSE("GPL v2");