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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / pci / controller / dwc / Kconfig
blob: ab4025e7ce9c91c8841511d9fe126c681bba31bc [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1# SPDX-License-Identifier: GPL-2.0
2
3menu "DesignWare PCI Core Support"
4 depends on PCI
5
6config PCIE_DW
7 bool
8
9config PCIE_DW_HOST
10 bool
11 select PCIE_DW
12
13config PCIE_DW_EP
14 bool
15 depends on PCI_ENDPOINT
16 select PCIE_DW
17
18config PCI_DRA7XX
19 bool
20
21config PCI_DRA7XX_HOST
22 bool "TI DRA7xx PCIe controller Host Mode"
23 depends on SOC_DRA7XX || COMPILE_TEST
24 depends on PCI_MSI_IRQ_DOMAIN
25 depends on OF && HAS_IOMEM && TI_PIPE3
26 select PCIE_DW_HOST
27 select PCI_DRA7XX
28 default y
29 help
30 Enables support for the PCIe controller in the DRA7xx SoC to work in
31 host mode. There are two instances of PCIe controller in DRA7xx.
32 This controller can work either as EP or RC. In order to enable
33 host-specific features PCI_DRA7XX_HOST must be selected and in order
34 to enable device-specific features PCI_DRA7XX_EP must be selected.
35 This uses the DesignWare core.
36
37config PCI_DRA7XX_EP
38 bool "TI DRA7xx PCIe controller Endpoint Mode"
39 depends on SOC_DRA7XX || COMPILE_TEST
40 depends on PCI_ENDPOINT
41 depends on OF && HAS_IOMEM && TI_PIPE3
42 select PCIE_DW_EP
43 select PCI_DRA7XX
44 help
45 Enables support for the PCIe controller in the DRA7xx SoC to work in
46 endpoint mode. There are two instances of PCIe controller in DRA7xx.
47 This controller can work either as EP or RC. In order to enable
48 host-specific features PCI_DRA7XX_HOST must be selected and in order
49 to enable device-specific features PCI_DRA7XX_EP must be selected.
50 This uses the DesignWare core.
51
52config PCIE_DW_PLAT
53 bool
54
55config PCIE_DW_PLAT_HOST
56 bool "Platform bus based DesignWare PCIe Controller - Host mode"
57 depends on PCI && PCI_MSI_IRQ_DOMAIN
58 select PCIE_DW_HOST
59 select PCIE_DW_PLAT
60 help
61 Enables support for the PCIe controller in the Designware IP to
62 work in host mode. There are two instances of PCIe controller in
63 Designware IP.
64 This controller can work either as EP or RC. In order to enable
65 host-specific features PCIE_DW_PLAT_HOST must be selected and in
66 order to enable device-specific features PCI_DW_PLAT_EP must be
67 selected.
68
69config PCIE_DW_PLAT_EP
70 bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
71 depends on PCI && PCI_MSI_IRQ_DOMAIN
72 depends on PCI_ENDPOINT
73 select PCIE_DW_EP
74 select PCIE_DW_PLAT
75 help
76 Enables support for the PCIe controller in the Designware IP to
77 work in endpoint mode. There are two instances of PCIe controller
78 in Designware IP.
79 This controller can work either as EP or RC. In order to enable
80 host-specific features PCIE_DW_PLAT_HOST must be selected and in
81 order to enable device-specific features PCI_DW_PLAT_EP must be
82 selected.
83
84config PCI_EXYNOS
85 bool "Samsung Exynos PCIe controller"
86 depends on SOC_EXYNOS5440 || COMPILE_TEST
87 depends on PCI_MSI_IRQ_DOMAIN
88 select PCIE_DW_HOST
89
90config PCI_IMX6
91 bool "Freescale i.MX6/7/8 PCIe controller"
92 depends on ARCH_MXC || COMPILE_TEST
93 depends on PCI_MSI_IRQ_DOMAIN
94 select PCIE_DW_HOST
95
96config PCIE_SPEAR13XX
97 bool "STMicroelectronics SPEAr PCIe controller"
98 depends on ARCH_SPEAR13XX || COMPILE_TEST
99 depends on PCI_MSI_IRQ_DOMAIN
100 select PCIE_DW_HOST
101 help
102 Say Y here if you want PCIe support on SPEAr13XX SoCs.
103
104config PCI_KEYSTONE
105 bool
106
107config PCI_KEYSTONE_HOST
108 bool "PCI Keystone Host Mode"
109 depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
110 depends on PCI_MSI_IRQ_DOMAIN
111 select PCIE_DW_HOST
112 select PCI_KEYSTONE
113 default y
114 help
115 Enables support for the PCIe controller in the Keystone SoC to
116 work in host mode. The PCI controller on Keystone is based on
117 DesignWare hardware and therefore the driver re-uses the
118 DesignWare core functions to implement the driver.
119
120config PCI_KEYSTONE_EP
121 bool "PCI Keystone Endpoint Mode"
122 depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
123 depends on PCI_ENDPOINT
124 select PCIE_DW_EP
125 select PCI_KEYSTONE
126 help
127 Enables support for the PCIe controller in the Keystone SoC to
128 work in endpoint mode. The PCI controller on Keystone is based
129 on DesignWare hardware and therefore the driver re-uses the
130 DesignWare core functions to implement the driver.
131
132config PCI_LAYERSCAPE
133 bool "Freescale Layerscape PCIe controller - Host mode"
134 depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
135 depends on PCI_MSI_IRQ_DOMAIN
136 select MFD_SYSCON
137 select PCIE_DW_HOST
138 help
139 Say Y here if you want to enable PCIe controller support on Layerscape
140 SoCs to work in Host mode.
141 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
142 determines which PCIe controller works in EP mode and which PCIe
143 controller works in RC mode.
144
145config PCI_LAYERSCAPE_EP
146 bool "Freescale Layerscape PCIe controller - Endpoint mode"
147 depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
148 depends on PCI_ENDPOINT
149 select PCIE_DW_EP
150 help
151 Say Y here if you want to enable PCIe controller support on Layerscape
152 SoCs to work in Endpoint mode.
153 This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
154 determines which PCIe controller works in EP mode and which PCIe
155 controller works in RC mode.
156
157config PCI_HISI
158 depends on OF && (ARM64 || COMPILE_TEST)
159 bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
160 depends on PCI_MSI_IRQ_DOMAIN
161 select PCIE_DW_HOST
162 select PCI_HOST_COMMON
163 help
164 Say Y here if you want PCIe controller support on HiSilicon
165 Hip05 and Hip06 SoCs
166
167config PCIE_QCOM
168 bool "Qualcomm PCIe controller"
169 depends on OF && (ARCH_QCOM || COMPILE_TEST)
170 depends on PCI_MSI_IRQ_DOMAIN
171 select PCIE_DW_HOST
172 help
173 Say Y here to enable PCIe controller support on Qualcomm SoCs. The
174 PCIe controller uses the DesignWare core plus Qualcomm-specific
175 hardware wrappers.
176
177config PCIE_ARMADA_8K
178 bool "Marvell Armada-8K PCIe controller"
179 depends on ARCH_MVEBU || COMPILE_TEST
180 depends on PCI_MSI_IRQ_DOMAIN
181 select PCIE_DW_HOST
182 help
183 Say Y here if you want to enable PCIe controller support on
184 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
185 DesignWare hardware and therefore the driver re-uses the
186 DesignWare core functions to implement the driver.
187
188config PCIE_ARTPEC6
189 bool
190
191config PCIE_ARTPEC6_HOST
192 bool "Axis ARTPEC-6 PCIe controller Host Mode"
193 depends on MACH_ARTPEC6 || COMPILE_TEST
194 depends on PCI_MSI_IRQ_DOMAIN
195 select PCIE_DW_HOST
196 select PCIE_ARTPEC6
197 help
198 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
199 host mode. This uses the DesignWare core.
200
201config PCIE_ARTPEC6_EP
202 bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
203 depends on MACH_ARTPEC6 || COMPILE_TEST
204 depends on PCI_ENDPOINT
205 select PCIE_DW_EP
206 select PCIE_ARTPEC6
207 help
208 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
209 endpoint mode. This uses the DesignWare core.
210
211config PCIE_KIRIN
212 depends on OF && (ARM64 || COMPILE_TEST)
213 bool "HiSilicon Kirin series SoCs PCIe controllers"
214 depends on PCI_MSI_IRQ_DOMAIN
215 select PCIE_DW_HOST
216 help
217 Say Y here if you want PCIe controller support
218 on HiSilicon Kirin series SoCs.
219
220config PCIE_HISI_STB
221 bool "HiSilicon STB SoCs PCIe controllers"
222 depends on ARCH_HISI || COMPILE_TEST
223 depends on PCI_MSI_IRQ_DOMAIN
224 select PCIE_DW_HOST
225 help
226 Say Y here if you want PCIe controller support on HiSilicon STB SoCs
227
228config PCI_MESON
229 bool "MESON PCIe controller"
230 depends on PCI_MSI_IRQ_DOMAIN
231 select PCIE_DW_HOST
232 help
233 Say Y here if you want to enable PCI controller support on Amlogic
234 SoCs. The PCI controller on Amlogic is based on DesignWare hardware
235 and therefore the driver re-uses the DesignWare core functions to
236 implement the driver.
237
238config PCIE_TEGRA194
239 tristate "NVIDIA Tegra194 (and later) PCIe controller"
240 depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
241 depends on PCI_MSI_IRQ_DOMAIN
242 select PCIE_DW_HOST
243 select PHY_TEGRA194_P2U
244 help
245 Say Y here if you want support for DesignWare core based PCIe host
246 controller found in NVIDIA Tegra194 SoC.
247
248config PCIE_UNIPHIER
249 bool "Socionext UniPhier PCIe controllers"
250 depends on ARCH_UNIPHIER || COMPILE_TEST
251 depends on OF && HAS_IOMEM
252 depends on PCI_MSI_IRQ_DOMAIN
253 select PCIE_DW_HOST
254 help
255 Say Y here if you want PCIe controller support on UniPhier SoCs.
256 This driver supports LD20 and PXs3 SoCs.
257
258config PCIE_AL
259 bool "Amazon Annapurna Labs PCIe controller"
260 depends on OF && (ARM64 || COMPILE_TEST)
261 depends on PCI_MSI_IRQ_DOMAIN
262 select PCIE_DW_HOST
263 help
264 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
265 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
266 core plus Annapurna Labs proprietary hardware wrappers. This is
267 required only for DT-based platforms. ACPI platforms with the
268 Annapurna Labs PCIe controller don't need to enable this.
269
270config PCIE_ASR1901
271 bool "ASR1901 PCIe controller"
272 depends on CPU_ASR1901 || COMPILE_TEST
273 select PCIE_DW_HOST
274 help
275 Say Y here if you want to enable PCIe controller support on
276 ASR1901 SoCs. The PCIe controller on ASR1901 is based on
277 DesignWare hardware and therefore the driver re-uses the
278 DesignWare core functions to implement the driver.
279
280endmenu