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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / phy / qualcomm / phy-qcom-qmp.c
blob: ceb168172bbad592458b527c93b1610d85f42d01 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
38/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
39#define PCS_READY BIT(0)
40
41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
42/* DP PHY soft reset */
43#define SW_DPPHY_RESET BIT(0)
44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
45#define SW_DPPHY_RESET_MUX BIT(1)
46/* USB3 PHY soft reset */
47#define SW_USB3PHY_RESET BIT(2)
48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
52#define USB3_MODE BIT(0) /* enables USB3 mode */
53#define DP_MODE BIT(1) /* enables DP mode */
54
55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61#define IRQ_CLEAR BIT(0)
62
63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
64#define RCVR_DETECT BIT(0)
65
66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
68
69#define PHY_INIT_COMPLETE_TIMEOUT 10000
70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
75/* Define the assumed distance between lanes for underspecified device trees. */
76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
77
78struct qmp_phy_init_tbl {
79 unsigned int offset;
80 unsigned int val;
81 /*
82 * register part of layout ?
83 * if yes, then offset gives index in the reg-layout
84 */
85 int in_layout;
86};
87
88#define QMP_PHY_INIT_CFG(o, v) \
89 { \
90 .offset = o, \
91 .val = v, \
92 }
93
94#define QMP_PHY_INIT_CFG_L(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .in_layout = 1, \
99 }
100
101/* set of registers with offsets different per-PHY */
102enum qphy_reg_layout {
103 /* Common block control registers */
104 QPHY_COM_SW_RESET,
105 QPHY_COM_POWER_DOWN_CONTROL,
106 QPHY_COM_START_CONTROL,
107 QPHY_COM_PCS_READY_STATUS,
108 /* PCS registers */
109 QPHY_PLL_LOCK_CHK_DLY_TIME,
110 QPHY_FLL_CNTRL1,
111 QPHY_FLL_CNTRL2,
112 QPHY_FLL_CNT_VAL_L,
113 QPHY_FLL_CNT_VAL_H_TOL,
114 QPHY_FLL_MAN_CODE,
115 QPHY_SW_RESET,
116 QPHY_START_CTRL,
117 QPHY_PCS_READY_STATUS,
118 QPHY_PCS_STATUS,
119 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
120 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
121 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
122};
123
124static const unsigned int pciephy_regs_layout[] = {
125 [QPHY_COM_SW_RESET] = 0x400,
126 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
127 [QPHY_COM_START_CONTROL] = 0x408,
128 [QPHY_COM_PCS_READY_STATUS] = 0x448,
129 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
130 [QPHY_FLL_CNTRL1] = 0xc4,
131 [QPHY_FLL_CNTRL2] = 0xc8,
132 [QPHY_FLL_CNT_VAL_L] = 0xcc,
133 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
134 [QPHY_FLL_MAN_CODE] = 0xd4,
135 [QPHY_SW_RESET] = 0x00,
136 [QPHY_START_CTRL] = 0x08,
137 [QPHY_PCS_STATUS] = 0x174,
138};
139
140static const unsigned int usb3phy_regs_layout[] = {
141 [QPHY_FLL_CNTRL1] = 0xc0,
142 [QPHY_FLL_CNTRL2] = 0xc4,
143 [QPHY_FLL_CNT_VAL_L] = 0xc8,
144 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
145 [QPHY_FLL_MAN_CODE] = 0xd0,
146 [QPHY_SW_RESET] = 0x00,
147 [QPHY_START_CTRL] = 0x08,
148 [QPHY_PCS_STATUS] = 0x17c,
149 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
150 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
151 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
152};
153
154static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
155 [QPHY_SW_RESET] = 0x00,
156 [QPHY_START_CTRL] = 0x08,
157 [QPHY_PCS_STATUS] = 0x174,
158 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
159 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
160 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
161};
162
163static const unsigned int sdm845_qmp_pciephy_regs_layout[] = {
164 [QPHY_SW_RESET] = 0x00,
165 [QPHY_START_CTRL] = 0x08,
166 [QPHY_PCS_STATUS] = 0x174,
167};
168
169static const unsigned int sdm845_qhp_pciephy_regs_layout[] = {
170 [QPHY_SW_RESET] = 0x00,
171 [QPHY_START_CTRL] = 0x08,
172 [QPHY_PCS_STATUS] = 0x2ac,
173};
174
175static const unsigned int sdm845_ufsphy_regs_layout[] = {
176 [QPHY_START_CTRL] = 0x00,
177 [QPHY_PCS_READY_STATUS] = 0x160,
178};
179
180static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
181 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
182 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
183 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
184 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
185 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
186 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
187 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
188 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
189 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
190 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
191 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
192 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
193 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
194 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
195 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
196 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
197 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
198 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
199 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
200 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
201 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
202 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
203 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
204 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
205 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
206 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
207 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
208 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
209 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
210 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
211 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
212 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
213 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
214 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
215 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
216 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
217 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
218 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
219 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
220 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
221 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
222 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
223 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
224};
225
226static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
227 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
228 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
229};
230
231static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
232 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
233 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
234 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
235 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
236 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
237 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
238 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
239 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
240 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
241 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
242};
243
244static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
245 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
246 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
247 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
248
249 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
250
251 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
252 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
253 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
254 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
255 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
256};
257
258static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
301};
302
303static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
304 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
305 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
306 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
307 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
308};
309
310static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
311 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
312 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
313 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
314 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
315 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
316 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
317 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
318 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
319 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
324 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
325};
326
327static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
338};
339
340static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
341 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
342 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
343 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
344 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
345 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
346 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
347 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
348 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
349 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
350 /* PLL and Loop filter settings */
351 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
352 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
353 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
354 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
355 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
356 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
357 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
358 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
359 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
360 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
361 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
362 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
363 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
364 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
365 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
366 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
367 /* SSC settings */
368 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
369 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
370 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
371 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
372 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
373 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
374 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
375};
376
377static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
378 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
379 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
380 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
381};
382
383static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
384 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
385 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
386 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
387 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
388 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
389 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
390 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
391 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
392 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
393 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
394};
395
396static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
397 /* FLL settings */
398 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
399 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
400 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
401 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
402 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
403
404 /* Lock Det settings */
405 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
406 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
407 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
408 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
409};
410
411static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
412 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
413 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
414 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
415 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
416 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
417 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
418 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
419 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
420 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
421 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
422 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
423 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
424 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
425 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
426 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
427 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
428 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
429 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
430 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
431 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
432 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
433 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
434 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
435 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
436 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
437 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
438 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
439 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
440 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
441 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
442 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
443 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
444 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
445 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
446 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
447 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
448 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
449 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
450 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
451 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
452};
453
454static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
455 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
456 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
457 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
458 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
459 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
460 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
461};
462
463static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
464 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
465 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
466 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
467 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
468 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
469 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
470 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
471};
472
473static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
474 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
475 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
476 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
477 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
478 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
479 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
480 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
481 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
482 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
483 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
484 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
485 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
486 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
487};
488
489static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
532};
533
534static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
535 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
536 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
537 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
538 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
539};
540
541static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
542 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
543 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
544 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
547 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
548 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
558};
559
560static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
562
563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
568
569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
576
577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
580
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
582};
583
584static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
590};
591
592static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
593 { 0x0dc, 0x27 },
594 { 0x014, 0x01 },
595 { 0x020, 0x31 },
596 { 0x024, 0x01 },
597 { 0x028, 0xde },
598 { 0x02c, 0x07 },
599 { 0x034, 0x4c },
600 { 0x038, 0x06 },
601 { 0x054, 0x18 },
602 { 0x058, 0xb0 },
603 { 0x06c, 0x8c },
604 { 0x070, 0x20 },
605 { 0x078, 0x14 },
606 { 0x07c, 0x34 },
607 { 0x0b4, 0x06 },
608 { 0x0b8, 0x06 },
609 { 0x0c0, 0x16 },
610 { 0x0c4, 0x16 },
611 { 0x0cc, 0x36 },
612 { 0x0d0, 0x36 },
613 { 0x0f0, 0x05 },
614 { 0x0f8, 0x42 },
615 { 0x100, 0x82 },
616 { 0x108, 0x68 },
617 { 0x11c, 0x55 },
618 { 0x120, 0x55 },
619 { 0x124, 0x03 },
620 { 0x128, 0xab },
621 { 0x12c, 0xaa },
622 { 0x130, 0x02 },
623 { 0x150, 0x3f },
624 { 0x158, 0x3f },
625 { 0x178, 0x10 },
626 { 0x1cc, 0x04 },
627 { 0x1d0, 0x30 },
628 { 0x1e0, 0x04 },
629 { 0x1e8, 0x73 },
630 { 0x1f0, 0x0c },
631 { 0x1fc, 0x15 },
632 { 0x21c, 0x04 },
633 { 0x224, 0x01 },
634 { 0x228, 0x22 },
635 { 0x22c, 0x00 },
636 { 0x098, 0x20 },
637 { 0x1c8, 0x07 },
638};
639
640static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
641 { 0x00c, 0x00 },
642 { 0x018, 0x0d },
643 { 0x060, 0x01 },
644 { 0x064, 0x1a },
645 { 0x07c, 0x2f },
646 { 0x0c0, 0x09 },
647 { 0x0c4, 0x09 },
648 { 0x0c8, 0x1b },
649 { 0x0d0, 0x01 },
650 { 0x0d4, 0x07 },
651 { 0x0d8, 0x31 },
652 { 0x0dc, 0x31 },
653 { 0x0e0, 0x03 },
654 { 0x0fc, 0x02 },
655 { 0x100, 0x00 },
656 { 0x108, 0x12 },
657 { 0x114, 0x25 },
658 { 0x118, 0x00 },
659 { 0x11c, 0x05 },
660 { 0x120, 0x01 },
661 { 0x124, 0x26 },
662 { 0x128, 0x12 },
663 { 0x130, 0x04 },
664 { 0x134, 0x04 },
665 { 0x138, 0x09 },
666 { 0x154, 0x15 },
667 { 0x160, 0x28 },
668 { 0x168, 0x7f },
669 { 0x16c, 0x07 },
670 { 0x178, 0x04 },
671 { 0x180, 0x70 },
672 { 0x184, 0x8b },
673 { 0x188, 0x08 },
674 { 0x18c, 0x0a },
675 { 0x190, 0x03 },
676 { 0x194, 0x04 },
677 { 0x198, 0x04 },
678 { 0x19c, 0x0c },
679 { 0x1a4, 0x02 },
680 { 0x1c0, 0x5c },
681 { 0x1c4, 0x3e },
682 { 0x1c8, 0x3f },
683 { 0x230, 0x01 },
684 { 0x234, 0xa0 },
685 { 0x238, 0x08 },
686 { 0x2a4, 0x01 },
687 { 0x2ac, 0xc3 },
688 { 0x2b0, 0x00 },
689 { 0x2b8, 0xbc },
690 { 0x2c0, 0x7f },
691 { 0x2c4, 0x15 },
692 { 0x010, 0x0c },
693 { 0x014, 0x0f },
694 { 0x2cc, 0x04 },
695 { 0x13c, 0x20 },
696 { 0x2a8, 0x01 },
697};
698
699static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
700};
701
702static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
703 { 0x15c, 0x3f },
704 { 0x174, 0x50 },
705 { 0x02c, 0x19 },
706 { 0x040, 0x07 },
707 { 0x054, 0x17 },
708 { 0x068, 0x09 },
709 { 0x16c, 0x9f },
710};
711
712static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
713 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
714 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
715 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
716 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
717 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
718 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
719 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
720 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
721 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
722 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
723 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
724 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
725 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
726 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
727 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
728 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
729 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
730 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
731 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
732 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
733 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
734 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
735 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
736 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
737 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
738 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
739 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
740 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
741 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
742 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
743 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
744 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
745 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
746 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
747 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
748 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
749};
750
751static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
752 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
753 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
754 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
755 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
756 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
757};
758
759static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
760 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
761 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
762 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
763 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
764 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
765 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
766 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
767 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
768 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
769};
770
771static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
772 /* FLL settings */
773 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
774 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
777 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
778
779 /* Lock Det settings */
780 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
781 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
782 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
783 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
784
785 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
786 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
787 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
788 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
789 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
790 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
791 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
792 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
793 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
794 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
795 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
796 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
797 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
798 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
799 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
800 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
801 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
802 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
803 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
804
805 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
806 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
807 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
808 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
809 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
810 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
811 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
812 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
813 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
814 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
815 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
816};
817
818static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
819 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
820 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
821 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
822 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
823 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
824 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
825 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
826 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
827 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
840 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
841 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
842 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
843 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
844 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
845 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
846 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
847 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
848 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
849 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
850 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
851 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
852 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
853 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
854 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
855};
856
857static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
858 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
859 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
860 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
861 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
862 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
863};
864
865static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
866 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
867 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
868 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
869 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
870 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
871 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
872 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
873 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
874 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
875 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
876 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
877};
878
879static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
880 /* FLL settings */
881 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
882 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
883 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
884 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
885 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
886
887 /* Lock Det settings */
888 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
889 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
890 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
891 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
892
893 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
894 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
895 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
896 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
897 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
898 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
899 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
900 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
901 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
902 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
903 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
904 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
905 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
906 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
907 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
908 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
909 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
910 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
911 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
912
913 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
914 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
915 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
916 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
917 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
918 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
919 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
920 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
921 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
922 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
923 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
924
925 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
926 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
927};
928
929static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
930 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
931 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
932 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
933 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
934 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
935 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
936 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
937 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
938 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
939 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
940 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
941 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
942 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
943 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
944 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
945 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
946 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
947 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
948 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
949 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
950 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
951 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
952 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
953 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
954 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
955 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
956 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
957 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
958 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
959 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
960 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
961 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
962 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
963 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
964 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
965 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
966
967 /* Rate B */
968 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
969};
970
971static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
972 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
973 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
974 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
975};
976
977static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
978 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
979 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
980 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
981 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
982 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
983 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
984 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
985 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
986 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
987 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
988 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
989 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
990 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
991 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
992 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
993 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
994};
995
996static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
997 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
998 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
999 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1000 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1001 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1002 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1003 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1004 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1005};
1006
1007static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1008 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1009 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1010 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1011 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1012 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1013 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1014 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1015 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1016 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1017 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1018 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1019 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1020 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1021 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1022 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1023 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1024 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1025 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1026 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1027 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1028 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1029 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1030 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1031 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1032 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1033 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1034 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1035 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1036 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1037 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1038 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1039 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1040 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1041 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1042 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1043 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1044 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1045 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1046};
1047
1048static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1049 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1050 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1051 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1053};
1054
1055static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1056 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1057 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1058 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1059 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1060 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1061 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1062 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1063 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1064 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1065 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1066 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1067 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1068 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1069 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1070 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1071 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1072 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1073};
1074
1075static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1076 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1077 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1078 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1079 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1080 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1081 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1082 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1083 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1084 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1085 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1086 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1087 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1088 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1089 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1090 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1091 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1092 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1093 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1094 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1095 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1096 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1097 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1098 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1099 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1100 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1101 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1102 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1103 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1104 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1105 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1106 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1107 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1108 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1109 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1110 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1111 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1112 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1113 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1114};
1115
1116
1117/* struct qmp_phy_cfg - per-PHY initialization config */
1118struct qmp_phy_cfg {
1119 /* phy-type - PCIE/UFS/USB */
1120 unsigned int type;
1121 /* number of lanes provided by phy */
1122 int nlanes;
1123
1124 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1125 const struct qmp_phy_init_tbl *serdes_tbl;
1126 int serdes_tbl_num;
1127 const struct qmp_phy_init_tbl *tx_tbl;
1128 int tx_tbl_num;
1129 const struct qmp_phy_init_tbl *rx_tbl;
1130 int rx_tbl_num;
1131 const struct qmp_phy_init_tbl *pcs_tbl;
1132 int pcs_tbl_num;
1133 const struct qmp_phy_init_tbl *pcs_misc_tbl;
1134 int pcs_misc_tbl_num;
1135
1136 /* clock ids to be requested */
1137 const char * const *clk_list;
1138 int num_clks;
1139 /* resets to be requested */
1140 const char * const *reset_list;
1141 int num_resets;
1142 /* regulators to be requested */
1143 const char * const *vreg_list;
1144 int num_vregs;
1145
1146 /* array of registers with different offsets */
1147 const unsigned int *regs;
1148
1149 unsigned int start_ctrl;
1150 unsigned int pwrdn_ctrl;
1151 unsigned int mask_com_pcs_ready;
1152
1153 /* true, if PHY has a separate PHY_COM control block */
1154 bool has_phy_com_ctrl;
1155 /* true, if PHY has a reset for individual lanes */
1156 bool has_lane_rst;
1157 /* true, if PHY needs delay after POWER_DOWN */
1158 bool has_pwrdn_delay;
1159 /* power_down delay in usec */
1160 int pwrdn_delay_min;
1161 int pwrdn_delay_max;
1162
1163 /* true, if PHY has a separate DP_COM control block */
1164 bool has_phy_dp_com_ctrl;
1165 /* true, if PHY has secondary tx/rx lanes to be configured */
1166 bool is_dual_lane_phy;
1167
1168 /* true, if PCS block has no separate SW_RESET register */
1169 bool no_pcs_sw_reset;
1170};
1171
1172/**
1173 * struct qmp_phy - per-lane phy descriptor
1174 *
1175 * @phy: generic phy
1176 * @tx: iomapped memory space for lane's tx
1177 * @rx: iomapped memory space for lane's rx
1178 * @pcs: iomapped memory space for lane's pcs
1179 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1180 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
1181 * @pcs_misc: iomapped memory space for lane's pcs_misc
1182 * @pipe_clk: pipe lock
1183 * @index: lane index
1184 * @qmp: QMP phy to which this lane belongs
1185 * @lane_rst: lane's reset controller
1186 */
1187struct qmp_phy {
1188 struct phy *phy;
1189 void __iomem *tx;
1190 void __iomem *rx;
1191 void __iomem *pcs;
1192 void __iomem *tx2;
1193 void __iomem *rx2;
1194 void __iomem *pcs_misc;
1195 struct clk *pipe_clk;
1196 unsigned int index;
1197 struct qcom_qmp *qmp;
1198 struct reset_control *lane_rst;
1199};
1200
1201/**
1202 * struct qcom_qmp - structure holding QMP phy block attributes
1203 *
1204 * @dev: device
1205 * @serdes: iomapped memory space for phy's serdes
1206 * @dp_com: iomapped memory space for phy's dp_com control block
1207 *
1208 * @clks: array of clocks required by phy
1209 * @resets: array of resets required by phy
1210 * @vregs: regulator supplies bulk data
1211 *
1212 * @cfg: phy specific configuration
1213 * @phys: array of per-lane phy descriptors
1214 * @phy_mutex: mutex lock for PHY common block initialization
1215 * @init_count: phy common block initialization count
1216 * @phy_initialized: indicate if PHY has been initialized
1217 * @mode: current PHY mode
1218 * @ufs_reset: optional UFS PHY reset handle
1219 */
1220struct qcom_qmp {
1221 struct device *dev;
1222 void __iomem *serdes;
1223 void __iomem *dp_com;
1224
1225 struct clk_bulk_data *clks;
1226 struct reset_control **resets;
1227 struct regulator_bulk_data *vregs;
1228
1229 const struct qmp_phy_cfg *cfg;
1230 struct qmp_phy **phys;
1231
1232 struct mutex phy_mutex;
1233 int init_count;
1234 bool phy_initialized;
1235 enum phy_mode mode;
1236
1237 struct reset_control *ufs_reset;
1238};
1239
1240static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1241{
1242 u32 reg;
1243
1244 reg = readl(base + offset);
1245 reg |= val;
1246 writel(reg, base + offset);
1247
1248 /* ensure that above write is through */
1249 readl(base + offset);
1250}
1251
1252static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1253{
1254 u32 reg;
1255
1256 reg = readl(base + offset);
1257 reg &= ~val;
1258 writel(reg, base + offset);
1259
1260 /* ensure that above write is through */
1261 readl(base + offset);
1262}
1263
1264/* list of clocks required by phy */
1265static const char * const msm8996_phy_clk_l[] = {
1266 "aux", "cfg_ahb", "ref",
1267};
1268
1269static const char * const qmp_v3_phy_clk_l[] = {
1270 "aux", "cfg_ahb", "ref", "com_aux",
1271};
1272
1273static const char * const sdm845_pciephy_clk_l[] = {
1274 "aux", "cfg_ahb", "ref", "refgen",
1275};
1276
1277static const char * const sdm845_ufs_phy_clk_l[] = {
1278 "ref", "ref_aux",
1279};
1280
1281/* list of resets */
1282static const char * const msm8996_pciephy_reset_l[] = {
1283 "phy", "common", "cfg",
1284};
1285
1286static const char * const msm8996_usb3phy_reset_l[] = {
1287 "phy", "common",
1288};
1289
1290static const char * const sdm845_pciephy_reset_l[] = {
1291 "phy",
1292};
1293
1294/* list of regulators */
1295static const char * const qmp_phy_vreg_l[] = {
1296 "vdda-phy", "vdda-pll",
1297};
1298
1299static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1300 .type = PHY_TYPE_PCIE,
1301 .nlanes = 3,
1302
1303 .serdes_tbl = msm8996_pcie_serdes_tbl,
1304 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1305 .tx_tbl = msm8996_pcie_tx_tbl,
1306 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1307 .rx_tbl = msm8996_pcie_rx_tbl,
1308 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1309 .pcs_tbl = msm8996_pcie_pcs_tbl,
1310 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1311 .clk_list = msm8996_phy_clk_l,
1312 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1313 .reset_list = msm8996_pciephy_reset_l,
1314 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
1315 .vreg_list = qmp_phy_vreg_l,
1316 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1317 .regs = pciephy_regs_layout,
1318
1319 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
1320 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1321 .mask_com_pcs_ready = PCS_READY,
1322
1323 .has_phy_com_ctrl = true,
1324 .has_lane_rst = true,
1325 .has_pwrdn_delay = true,
1326 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1327 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1328};
1329
1330static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1331 .type = PHY_TYPE_USB3,
1332 .nlanes = 1,
1333
1334 .serdes_tbl = msm8996_usb3_serdes_tbl,
1335 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1336 .tx_tbl = msm8996_usb3_tx_tbl,
1337 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1338 .rx_tbl = msm8996_usb3_rx_tbl,
1339 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1340 .pcs_tbl = msm8996_usb3_pcs_tbl,
1341 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1342 .clk_list = msm8996_phy_clk_l,
1343 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1344 .reset_list = msm8996_usb3phy_reset_l,
1345 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1346 .vreg_list = qmp_phy_vreg_l,
1347 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1348 .regs = usb3phy_regs_layout,
1349
1350 .start_ctrl = SERDES_START | PCS_START,
1351 .pwrdn_ctrl = SW_PWRDN,
1352};
1353
1354static const char * const ipq8074_pciephy_clk_l[] = {
1355 "aux", "cfg_ahb",
1356};
1357/* list of resets */
1358static const char * const ipq8074_pciephy_reset_l[] = {
1359 "phy", "common",
1360};
1361
1362static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1363 .type = PHY_TYPE_PCIE,
1364 .nlanes = 1,
1365
1366 .serdes_tbl = ipq8074_pcie_serdes_tbl,
1367 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1368 .tx_tbl = ipq8074_pcie_tx_tbl,
1369 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1370 .rx_tbl = ipq8074_pcie_rx_tbl,
1371 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1372 .pcs_tbl = ipq8074_pcie_pcs_tbl,
1373 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1374 .clk_list = ipq8074_pciephy_clk_l,
1375 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1376 .reset_list = ipq8074_pciephy_reset_l,
1377 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1378 .vreg_list = NULL,
1379 .num_vregs = 0,
1380 .regs = pciephy_regs_layout,
1381
1382 .start_ctrl = SERDES_START | PCS_START,
1383 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1384
1385 .has_phy_com_ctrl = false,
1386 .has_lane_rst = false,
1387 .has_pwrdn_delay = true,
1388 .pwrdn_delay_min = 995, /* us */
1389 .pwrdn_delay_max = 1005, /* us */
1390};
1391
1392static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
1393 .type = PHY_TYPE_PCIE,
1394 .nlanes = 1,
1395
1396 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
1397 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
1398 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
1399 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
1400 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
1401 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
1402 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
1403 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
1404 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
1405 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
1406 .clk_list = sdm845_pciephy_clk_l,
1407 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1408 .reset_list = sdm845_pciephy_reset_l,
1409 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1410 .vreg_list = qmp_phy_vreg_l,
1411 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1412 .regs = sdm845_qmp_pciephy_regs_layout,
1413
1414 .start_ctrl = PCS_START | SERDES_START,
1415 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1416
1417 .has_pwrdn_delay = true,
1418 .pwrdn_delay_min = 995, /* us */
1419 .pwrdn_delay_max = 1005, /* us */
1420};
1421
1422static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
1423 .type = PHY_TYPE_PCIE,
1424 .nlanes = 1,
1425
1426 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
1427 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
1428 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
1429 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
1430 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
1431 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
1432 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
1433 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
1434 .clk_list = sdm845_pciephy_clk_l,
1435 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1436 .reset_list = sdm845_pciephy_reset_l,
1437 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1438 .vreg_list = qmp_phy_vreg_l,
1439 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1440 .regs = sdm845_qhp_pciephy_regs_layout,
1441
1442 .start_ctrl = PCS_START | SERDES_START,
1443 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1444
1445 .has_pwrdn_delay = true,
1446 .pwrdn_delay_min = 995, /* us */
1447 .pwrdn_delay_max = 1005, /* us */
1448};
1449
1450static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1451 .type = PHY_TYPE_USB3,
1452 .nlanes = 1,
1453
1454 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1455 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1456 .tx_tbl = qmp_v3_usb3_tx_tbl,
1457 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1458 .rx_tbl = qmp_v3_usb3_rx_tbl,
1459 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1460 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1461 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1462 .clk_list = qmp_v3_phy_clk_l,
1463 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1464 .reset_list = msm8996_usb3phy_reset_l,
1465 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1466 .vreg_list = qmp_phy_vreg_l,
1467 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1468 .regs = qmp_v3_usb3phy_regs_layout,
1469
1470 .start_ctrl = SERDES_START | PCS_START,
1471 .pwrdn_ctrl = SW_PWRDN,
1472
1473 .has_pwrdn_delay = true,
1474 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1475 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1476
1477 .has_phy_dp_com_ctrl = true,
1478 .is_dual_lane_phy = true,
1479};
1480
1481static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1482 .type = PHY_TYPE_USB3,
1483 .nlanes = 1,
1484
1485 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1486 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1487 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1488 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1489 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1490 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1491 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1492 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1493 .clk_list = qmp_v3_phy_clk_l,
1494 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1495 .reset_list = msm8996_usb3phy_reset_l,
1496 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1497 .vreg_list = qmp_phy_vreg_l,
1498 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1499 .regs = qmp_v3_usb3phy_regs_layout,
1500
1501 .start_ctrl = SERDES_START | PCS_START,
1502 .pwrdn_ctrl = SW_PWRDN,
1503
1504 .has_pwrdn_delay = true,
1505 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1506 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1507};
1508
1509static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1510 .type = PHY_TYPE_UFS,
1511 .nlanes = 2,
1512
1513 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
1514 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1515 .tx_tbl = sdm845_ufsphy_tx_tbl,
1516 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1517 .rx_tbl = sdm845_ufsphy_rx_tbl,
1518 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1519 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
1520 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1521 .clk_list = sdm845_ufs_phy_clk_l,
1522 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1523 .vreg_list = qmp_phy_vreg_l,
1524 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1525 .regs = sdm845_ufsphy_regs_layout,
1526
1527 .start_ctrl = SERDES_START,
1528 .pwrdn_ctrl = SW_PWRDN,
1529
1530 .is_dual_lane_phy = true,
1531 .no_pcs_sw_reset = true,
1532};
1533
1534static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1535 .type = PHY_TYPE_PCIE,
1536 .nlanes = 1,
1537
1538 .serdes_tbl = msm8998_pcie_serdes_tbl,
1539 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1540 .tx_tbl = msm8998_pcie_tx_tbl,
1541 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1542 .rx_tbl = msm8998_pcie_rx_tbl,
1543 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1544 .pcs_tbl = msm8998_pcie_pcs_tbl,
1545 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1546 .clk_list = msm8996_phy_clk_l,
1547 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1548 .reset_list = ipq8074_pciephy_reset_l,
1549 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1550 .vreg_list = qmp_phy_vreg_l,
1551 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1552 .regs = pciephy_regs_layout,
1553
1554 .start_ctrl = SERDES_START | PCS_START,
1555 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1556};
1557
1558static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1559 .type = PHY_TYPE_USB3,
1560 .nlanes = 1,
1561
1562 .serdes_tbl = msm8998_usb3_serdes_tbl,
1563 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1564 .tx_tbl = msm8998_usb3_tx_tbl,
1565 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1566 .rx_tbl = msm8998_usb3_rx_tbl,
1567 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1568 .pcs_tbl = msm8998_usb3_pcs_tbl,
1569 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1570 .clk_list = msm8996_phy_clk_l,
1571 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1572 .reset_list = msm8996_usb3phy_reset_l,
1573 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1574 .vreg_list = qmp_phy_vreg_l,
1575 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1576 .regs = qmp_v3_usb3phy_regs_layout,
1577
1578 .start_ctrl = SERDES_START | PCS_START,
1579 .pwrdn_ctrl = SW_PWRDN,
1580
1581 .is_dual_lane_phy = true,
1582};
1583
1584static void qcom_qmp_phy_configure(void __iomem *base,
1585 const unsigned int *regs,
1586 const struct qmp_phy_init_tbl tbl[],
1587 int num)
1588{
1589 int i;
1590 const struct qmp_phy_init_tbl *t = tbl;
1591
1592 if (!t)
1593 return;
1594
1595 for (i = 0; i < num; i++, t++) {
1596 if (t->in_layout)
1597 writel(t->val, base + regs[t->offset]);
1598 else
1599 writel(t->val, base + t->offset);
1600 }
1601}
1602
1603static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1604{
1605 struct qcom_qmp *qmp = qphy->qmp;
1606 const struct qmp_phy_cfg *cfg = qmp->cfg;
1607 void __iomem *serdes = qmp->serdes;
1608 void __iomem *pcs = qphy->pcs;
1609 void __iomem *dp_com = qmp->dp_com;
1610 int ret, i;
1611
1612 mutex_lock(&qmp->phy_mutex);
1613 if (qmp->init_count++) {
1614 mutex_unlock(&qmp->phy_mutex);
1615 return 0;
1616 }
1617
1618 /* turn on regulator supplies */
1619 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1620 if (ret) {
1621 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1622 goto err_reg_enable;
1623 }
1624
1625 for (i = 0; i < cfg->num_resets; i++) {
1626 ret = reset_control_assert(qmp->resets[i]);
1627 if (ret) {
1628 dev_err(qmp->dev, "%s reset assert failed\n",
1629 cfg->reset_list[i]);
1630 goto err_rst_assert;
1631 }
1632 }
1633
1634 for (i = cfg->num_resets - 1; i >= 0; i--) {
1635 ret = reset_control_deassert(qmp->resets[i]);
1636 if (ret) {
1637 dev_err(qmp->dev, "%s reset deassert failed\n",
1638 qmp->cfg->reset_list[i]);
1639 goto err_rst;
1640 }
1641 }
1642
1643 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1644 if (ret) {
1645 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1646 goto err_rst;
1647 }
1648
1649 if (cfg->has_phy_dp_com_ctrl) {
1650 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1651 SW_PWRDN);
1652 /* override hardware control for reset of qmp phy */
1653 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1654 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1655 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1656
1657 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1658 USB3_MODE | DP_MODE);
1659
1660 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1661 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1662 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1663 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1664 }
1665
1666 if (cfg->has_phy_com_ctrl)
1667 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1668 SW_PWRDN);
1669 else
1670 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1671
1672 /* Serdes configuration */
1673 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1674 cfg->serdes_tbl_num);
1675
1676 if (cfg->has_phy_com_ctrl) {
1677 void __iomem *status;
1678 unsigned int mask, val;
1679
1680 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1681 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1682 SERDES_START | PCS_START);
1683
1684 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1685 mask = cfg->mask_com_pcs_ready;
1686
1687 ret = readl_poll_timeout(status, val, (val & mask), 10,
1688 PHY_INIT_COMPLETE_TIMEOUT);
1689 if (ret) {
1690 dev_err(qmp->dev,
1691 "phy common block init timed-out\n");
1692 goto err_com_init;
1693 }
1694 }
1695
1696 mutex_unlock(&qmp->phy_mutex);
1697
1698 return 0;
1699
1700err_com_init:
1701 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1702err_rst:
1703 while (++i < cfg->num_resets)
1704 reset_control_assert(qmp->resets[i]);
1705err_rst_assert:
1706 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1707err_reg_enable:
1708 mutex_unlock(&qmp->phy_mutex);
1709
1710 return ret;
1711}
1712
1713static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1714{
1715 const struct qmp_phy_cfg *cfg = qmp->cfg;
1716 void __iomem *serdes = qmp->serdes;
1717 int i = cfg->num_resets;
1718
1719 mutex_lock(&qmp->phy_mutex);
1720 if (--qmp->init_count) {
1721 mutex_unlock(&qmp->phy_mutex);
1722 return 0;
1723 }
1724
1725 reset_control_assert(qmp->ufs_reset);
1726 if (cfg->has_phy_com_ctrl) {
1727 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1728 SERDES_START | PCS_START);
1729 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1730 SW_RESET);
1731 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1732 SW_PWRDN);
1733 }
1734
1735 while (--i >= 0)
1736 reset_control_assert(qmp->resets[i]);
1737
1738 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1739
1740 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1741
1742 mutex_unlock(&qmp->phy_mutex);
1743
1744 return 0;
1745}
1746
1747static int qcom_qmp_phy_enable(struct phy *phy)
1748{
1749 struct qmp_phy *qphy = phy_get_drvdata(phy);
1750 struct qcom_qmp *qmp = qphy->qmp;
1751 const struct qmp_phy_cfg *cfg = qmp->cfg;
1752 void __iomem *tx = qphy->tx;
1753 void __iomem *rx = qphy->rx;
1754 void __iomem *pcs = qphy->pcs;
1755 void __iomem *pcs_misc = qphy->pcs_misc;
1756 void __iomem *dp_com = qmp->dp_com;
1757 void __iomem *status;
1758 unsigned int mask, val, ready;
1759 int ret;
1760
1761 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1762
1763 if (cfg->no_pcs_sw_reset) {
1764 /*
1765 * Get UFS reset, which is delayed until now to avoid a
1766 * circular dependency where UFS needs its PHY, but the PHY
1767 * needs this UFS reset.
1768 */
1769 if (!qmp->ufs_reset) {
1770 qmp->ufs_reset =
1771 devm_reset_control_get_exclusive(qmp->dev,
1772 "ufsphy");
1773
1774 if (IS_ERR(qmp->ufs_reset)) {
1775 ret = PTR_ERR(qmp->ufs_reset);
1776 dev_err(qmp->dev,
1777 "failed to get UFS reset: %d\n",
1778 ret);
1779
1780 qmp->ufs_reset = NULL;
1781 return ret;
1782 }
1783 }
1784
1785 ret = reset_control_assert(qmp->ufs_reset);
1786 if (ret)
1787 goto err_lane_rst;
1788 }
1789
1790 ret = qcom_qmp_phy_com_init(qphy);
1791 if (ret)
1792 return ret;
1793
1794 if (cfg->has_lane_rst) {
1795 ret = reset_control_deassert(qphy->lane_rst);
1796 if (ret) {
1797 dev_err(qmp->dev, "lane%d reset deassert failed\n",
1798 qphy->index);
1799 goto err_lane_rst;
1800 }
1801 }
1802
1803 ret = clk_prepare_enable(qphy->pipe_clk);
1804 if (ret) {
1805 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1806 goto err_clk_enable;
1807 }
1808
1809 /* Tx, Rx, and PCS configurations */
1810 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1811 /* Configuration for other LANE for USB-DP combo PHY */
1812 if (cfg->is_dual_lane_phy)
1813 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
1814 cfg->tx_tbl, cfg->tx_tbl_num);
1815
1816 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1817 if (cfg->is_dual_lane_phy)
1818 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
1819 cfg->rx_tbl, cfg->rx_tbl_num);
1820
1821 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1822 ret = reset_control_deassert(qmp->ufs_reset);
1823 if (ret)
1824 goto err_pcs_ready;
1825
1826 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
1827 cfg->pcs_misc_tbl_num);
1828
1829 /*
1830 * Pull out PHY from POWER DOWN state.
1831 * This is active low enable signal to power-down PHY.
1832 */
1833 if(cfg->type == PHY_TYPE_PCIE)
1834 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1835
1836 if (cfg->has_pwrdn_delay)
1837 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1838
1839 /* Pull PHY out of reset state */
1840 if (!cfg->no_pcs_sw_reset)
1841 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1842
1843 if (cfg->has_phy_dp_com_ctrl)
1844 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1845
1846 /* start SerDes and Phy-Coding-Sublayer */
1847 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1848
1849 if (cfg->type == PHY_TYPE_UFS) {
1850 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1851 mask = PCS_READY;
1852 ready = PCS_READY;
1853 } else {
1854 status = pcs + cfg->regs[QPHY_PCS_STATUS];
1855 mask = PHYSTATUS;
1856 ready = 0;
1857 }
1858
1859 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
1860 PHY_INIT_COMPLETE_TIMEOUT);
1861 if (ret) {
1862 dev_err(qmp->dev, "phy initialization timed-out\n");
1863 goto err_pcs_ready;
1864 }
1865 qmp->phy_initialized = true;
1866 return 0;
1867
1868err_pcs_ready:
1869 reset_control_assert(qmp->ufs_reset);
1870 clk_disable_unprepare(qphy->pipe_clk);
1871err_clk_enable:
1872 if (cfg->has_lane_rst)
1873 reset_control_assert(qphy->lane_rst);
1874err_lane_rst:
1875 qcom_qmp_phy_com_exit(qmp);
1876
1877 return ret;
1878}
1879
1880static int qcom_qmp_phy_disable(struct phy *phy)
1881{
1882 struct qmp_phy *qphy = phy_get_drvdata(phy);
1883 struct qcom_qmp *qmp = qphy->qmp;
1884 const struct qmp_phy_cfg *cfg = qmp->cfg;
1885
1886 clk_disable_unprepare(qphy->pipe_clk);
1887
1888 /* PHY reset */
1889 if (!cfg->no_pcs_sw_reset)
1890 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1891
1892 /* stop SerDes and Phy-Coding-Sublayer */
1893 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1894
1895 /* Put PHY into POWER DOWN state: active low */
1896 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1897
1898 if (cfg->has_lane_rst)
1899 reset_control_assert(qphy->lane_rst);
1900
1901 qcom_qmp_phy_com_exit(qmp);
1902
1903 qmp->phy_initialized = false;
1904
1905 return 0;
1906}
1907
1908static int qcom_qmp_phy_set_mode(struct phy *phy,
1909 enum phy_mode mode, int submode)
1910{
1911 struct qmp_phy *qphy = phy_get_drvdata(phy);
1912 struct qcom_qmp *qmp = qphy->qmp;
1913
1914 qmp->mode = mode;
1915
1916 return 0;
1917}
1918
1919static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1920{
1921 struct qcom_qmp *qmp = qphy->qmp;
1922 const struct qmp_phy_cfg *cfg = qmp->cfg;
1923 void __iomem *pcs = qphy->pcs;
1924 void __iomem *pcs_misc = qphy->pcs_misc;
1925 u32 intr_mask;
1926
1927 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1928 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1929 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1930 else
1931 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1932
1933 /* Clear any pending interrupts status */
1934 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1935 /* Writing 1 followed by 0 clears the interrupt */
1936 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1937
1938 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1939 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1940
1941 /* Enable required PHY autonomous mode interrupts */
1942 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1943
1944 /* Enable i/o clamp_n for autonomous mode */
1945 if (pcs_misc)
1946 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1947}
1948
1949static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1950{
1951 struct qcom_qmp *qmp = qphy->qmp;
1952 const struct qmp_phy_cfg *cfg = qmp->cfg;
1953 void __iomem *pcs = qphy->pcs;
1954 void __iomem *pcs_misc = qphy->pcs_misc;
1955
1956 /* Disable i/o clamp_n on resume for normal mode */
1957 if (pcs_misc)
1958 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1959
1960 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1961 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1962
1963 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1964 /* Writing 1 followed by 0 clears the interrupt */
1965 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1966}
1967
1968static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1969{
1970 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1971 struct qmp_phy *qphy = qmp->phys[0];
1972 const struct qmp_phy_cfg *cfg = qmp->cfg;
1973
1974 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1975
1976 /* Supported only for USB3 PHY */
1977 if (cfg->type != PHY_TYPE_USB3)
1978 return 0;
1979
1980 if (!qmp->phy_initialized) {
1981 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1982 return 0;
1983 }
1984
1985 qcom_qmp_phy_enable_autonomous_mode(qphy);
1986
1987 clk_disable_unprepare(qphy->pipe_clk);
1988 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1989
1990 return 0;
1991}
1992
1993static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1994{
1995 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1996 struct qmp_phy *qphy = qmp->phys[0];
1997 const struct qmp_phy_cfg *cfg = qmp->cfg;
1998 int ret = 0;
1999
2000 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2001
2002 /* Supported only for USB3 PHY */
2003 if (cfg->type != PHY_TYPE_USB3)
2004 return 0;
2005
2006 if (!qmp->phy_initialized) {
2007 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2008 return 0;
2009 }
2010
2011 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2012 if (ret) {
2013 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2014 return ret;
2015 }
2016
2017 ret = clk_prepare_enable(qphy->pipe_clk);
2018 if (ret) {
2019 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2020 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2021 return ret;
2022 }
2023
2024 qcom_qmp_phy_disable_autonomous_mode(qphy);
2025
2026 return 0;
2027}
2028
2029static int qcom_qmp_phy_vreg_init(struct device *dev)
2030{
2031 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2032 int num = qmp->cfg->num_vregs;
2033 int i;
2034
2035 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2036 if (!qmp->vregs)
2037 return -ENOMEM;
2038
2039 for (i = 0; i < num; i++)
2040 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
2041
2042 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2043}
2044
2045static int qcom_qmp_phy_reset_init(struct device *dev)
2046{
2047 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2048 int i;
2049
2050 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
2051 sizeof(*qmp->resets), GFP_KERNEL);
2052 if (!qmp->resets)
2053 return -ENOMEM;
2054
2055 for (i = 0; i < qmp->cfg->num_resets; i++) {
2056 struct reset_control *rst;
2057 const char *name = qmp->cfg->reset_list[i];
2058
2059 rst = devm_reset_control_get(dev, name);
2060 if (IS_ERR(rst)) {
2061 dev_err(dev, "failed to get %s reset\n", name);
2062 return PTR_ERR(rst);
2063 }
2064 qmp->resets[i] = rst;
2065 }
2066
2067 return 0;
2068}
2069
2070static int qcom_qmp_phy_clk_init(struct device *dev)
2071{
2072 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2073 int num = qmp->cfg->num_clks;
2074 int i;
2075
2076 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2077 if (!qmp->clks)
2078 return -ENOMEM;
2079
2080 for (i = 0; i < num; i++)
2081 qmp->clks[i].id = qmp->cfg->clk_list[i];
2082
2083 return devm_clk_bulk_get(dev, num, qmp->clks);
2084}
2085
2086static void phy_pipe_clk_release_provider(void *res)
2087{
2088 of_clk_del_provider(res);
2089}
2090
2091/*
2092 * Register a fixed rate pipe clock.
2093 *
2094 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2095 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2096 * by the PHY driver for its operations.
2097 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2098 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2099 * Below picture shows this relationship.
2100 *
2101 * +---------------+
2102 * | PHY block |<<---------------------------------------+
2103 * | | |
2104 * | +-------+ | +-----+ |
2105 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2106 * clk | +-------+ | +-----+
2107 * +---------------+
2108 */
2109static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
2110{
2111 struct clk_fixed_rate *fixed;
2112 struct clk_init_data init = { };
2113 int ret;
2114
2115 if ((qmp->cfg->type != PHY_TYPE_USB3) &&
2116 (qmp->cfg->type != PHY_TYPE_PCIE)) {
2117 /* not all phys register pipe clocks, so return success */
2118 return 0;
2119 }
2120
2121 ret = of_property_read_string(np, "clock-output-names", &init.name);
2122 if (ret) {
2123 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2124 return ret;
2125 }
2126
2127 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2128 if (!fixed)
2129 return -ENOMEM;
2130
2131 init.ops = &clk_fixed_rate_ops;
2132
2133 /* controllers using QMP phys use 125MHz pipe clock interface */
2134 fixed->fixed_rate = 125000000;
2135 fixed->hw.init = &init;
2136
2137 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2138 if (ret)
2139 return ret;
2140
2141 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2142 if (ret)
2143 return ret;
2144
2145 /*
2146 * Roll a devm action because the clock provider is the child node, but
2147 * the child node is not actually a device.
2148 */
2149 ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
2150 if (ret)
2151 phy_pipe_clk_release_provider(np);
2152
2153 return ret;
2154}
2155
2156static const struct phy_ops qcom_qmp_phy_gen_ops = {
2157 .init = qcom_qmp_phy_enable,
2158 .exit = qcom_qmp_phy_disable,
2159 .set_mode = qcom_qmp_phy_set_mode,
2160 .owner = THIS_MODULE,
2161};
2162
2163static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
2164 .power_on = qcom_qmp_phy_enable,
2165 .power_off = qcom_qmp_phy_disable,
2166 .set_mode = qcom_qmp_phy_set_mode,
2167 .owner = THIS_MODULE,
2168};
2169
2170static void qcom_qmp_reset_control_put(void *data)
2171{
2172 reset_control_put(data);
2173}
2174
2175static
2176int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
2177{
2178 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2179 struct phy *generic_phy;
2180 struct qmp_phy *qphy;
2181 const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
2182 char prop_name[MAX_PROP_NAME];
2183 int ret;
2184
2185 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
2186 if (!qphy)
2187 return -ENOMEM;
2188
2189 /*
2190 * Get memory resources for each phy lane:
2191 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2192 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2193 * For single lane PHYs: pcs_misc (optional) -> 3.
2194 */
2195 qphy->tx = of_iomap(np, 0);
2196 if (!qphy->tx)
2197 return -ENOMEM;
2198
2199 qphy->rx = of_iomap(np, 1);
2200 if (!qphy->rx)
2201 return -ENOMEM;
2202
2203 qphy->pcs = of_iomap(np, 2);
2204 if (!qphy->pcs)
2205 return -ENOMEM;
2206
2207 /*
2208 * If this is a dual-lane PHY, then there should be registers for the
2209 * second lane. Some old device trees did not specify this, so fall
2210 * back to old legacy behavior of assuming they can be reached at an
2211 * offset from the first lane.
2212 */
2213 if (qmp->cfg->is_dual_lane_phy) {
2214 qphy->tx2 = of_iomap(np, 3);
2215 qphy->rx2 = of_iomap(np, 4);
2216 if (!qphy->tx2 || !qphy->rx2) {
2217 dev_warn(dev,
2218 "Underspecified device tree, falling back to legacy register regions\n");
2219
2220 /* In the old version, pcs_misc is at index 3. */
2221 qphy->pcs_misc = qphy->tx2;
2222 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
2223 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
2224
2225 } else {
2226 qphy->pcs_misc = of_iomap(np, 5);
2227 }
2228
2229 } else {
2230 qphy->pcs_misc = of_iomap(np, 3);
2231 }
2232
2233 if (!qphy->pcs_misc)
2234 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2235
2236 /*
2237 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
2238 * based phys, so they essentially have pipe clock. So,
2239 * we return error in case phy is USB3 or PIPE type.
2240 * Otherwise, we initialize pipe clock to NULL for
2241 * all phys that don't need this.
2242 */
2243 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
2244 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
2245 if (IS_ERR(qphy->pipe_clk)) {
2246 if (qmp->cfg->type == PHY_TYPE_PCIE ||
2247 qmp->cfg->type == PHY_TYPE_USB3) {
2248 ret = PTR_ERR(qphy->pipe_clk);
2249 if (ret != -EPROBE_DEFER)
2250 dev_err(dev,
2251 "failed to get lane%d pipe_clk, %d\n",
2252 id, ret);
2253 return ret;
2254 }
2255 qphy->pipe_clk = NULL;
2256 }
2257
2258 /* Get lane reset, if any */
2259 if (qmp->cfg->has_lane_rst) {
2260 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
2261 qphy->lane_rst = of_reset_control_get(np, prop_name);
2262 if (IS_ERR(qphy->lane_rst)) {
2263 dev_err(dev, "failed to get lane%d reset\n", id);
2264 return PTR_ERR(qphy->lane_rst);
2265 }
2266 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
2267 qphy->lane_rst);
2268 if (ret)
2269 return ret;
2270 }
2271
2272 if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE)
2273 ops = &qcom_qmp_pcie_ufs_ops;
2274
2275 generic_phy = devm_phy_create(dev, np, ops);
2276 if (IS_ERR(generic_phy)) {
2277 ret = PTR_ERR(generic_phy);
2278 dev_err(dev, "failed to create qphy %d\n", ret);
2279 return ret;
2280 }
2281
2282 qphy->phy = generic_phy;
2283 qphy->index = id;
2284 qphy->qmp = qmp;
2285 qmp->phys[id] = qphy;
2286 phy_set_drvdata(generic_phy, qphy);
2287
2288 return 0;
2289}
2290
2291static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
2292 {
2293 .compatible = "qcom,msm8996-qmp-pcie-phy",
2294 .data = &msm8996_pciephy_cfg,
2295 }, {
2296 .compatible = "qcom,msm8996-qmp-usb3-phy",
2297 .data = &msm8996_usb3phy_cfg,
2298 }, {
2299 .compatible = "qcom,msm8998-qmp-pcie-phy",
2300 .data = &msm8998_pciephy_cfg,
2301 }, {
2302 .compatible = "qcom,msm8998-qmp-ufs-phy",
2303 .data = &sdm845_ufsphy_cfg,
2304 }, {
2305 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2306 .data = &ipq8074_pciephy_cfg,
2307 }, {
2308 .compatible = "qcom,sdm845-qhp-pcie-phy",
2309 .data = &sdm845_qhp_pciephy_cfg,
2310 }, {
2311 .compatible = "qcom,sdm845-qmp-pcie-phy",
2312 .data = &sdm845_qmp_pciephy_cfg,
2313 }, {
2314 .compatible = "qcom,sdm845-qmp-usb3-phy",
2315 .data = &qmp_v3_usb3phy_cfg,
2316 }, {
2317 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2318 .data = &qmp_v3_usb3_uniphy_cfg,
2319 }, {
2320 .compatible = "qcom,sdm845-qmp-ufs-phy",
2321 .data = &sdm845_ufsphy_cfg,
2322 }, {
2323 .compatible = "qcom,msm8998-qmp-usb3-phy",
2324 .data = &msm8998_usb3phy_cfg,
2325 },
2326 { },
2327};
2328MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2329
2330static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2331 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2332 qcom_qmp_phy_runtime_resume, NULL)
2333};
2334
2335static int qcom_qmp_phy_probe(struct platform_device *pdev)
2336{
2337 struct qcom_qmp *qmp;
2338 struct device *dev = &pdev->dev;
2339 struct resource *res;
2340 struct device_node *child;
2341 struct phy_provider *phy_provider;
2342 void __iomem *base;
2343 int num, id;
2344 int ret;
2345
2346 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2347 if (!qmp)
2348 return -ENOMEM;
2349
2350 qmp->dev = dev;
2351 dev_set_drvdata(dev, qmp);
2352
2353 /* Get the specific init parameters of QMP phy */
2354 qmp->cfg = of_device_get_match_data(dev);
2355 if (!qmp->cfg)
2356 return -EINVAL;
2357
2358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2359 base = devm_ioremap_resource(dev, res);
2360 if (IS_ERR(base))
2361 return PTR_ERR(base);
2362
2363 /* per PHY serdes; usually located at base address */
2364 qmp->serdes = base;
2365
2366 /* per PHY dp_com; if PHY has dp_com control block */
2367 if (qmp->cfg->has_phy_dp_com_ctrl) {
2368 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2369 "dp_com");
2370 base = devm_ioremap_resource(dev, res);
2371 if (IS_ERR(base))
2372 return PTR_ERR(base);
2373
2374 qmp->dp_com = base;
2375 }
2376
2377 mutex_init(&qmp->phy_mutex);
2378
2379 ret = qcom_qmp_phy_clk_init(dev);
2380 if (ret)
2381 return ret;
2382
2383 ret = qcom_qmp_phy_reset_init(dev);
2384 if (ret)
2385 return ret;
2386
2387 ret = qcom_qmp_phy_vreg_init(dev);
2388 if (ret) {
2389 if (ret != -EPROBE_DEFER)
2390 dev_err(dev, "failed to get regulator supplies: %d\n",
2391 ret);
2392 return ret;
2393 }
2394
2395 num = of_get_available_child_count(dev->of_node);
2396 /* do we have a rogue child node ? */
2397 if (num > qmp->cfg->nlanes)
2398 return -EINVAL;
2399
2400 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2401 if (!qmp->phys)
2402 return -ENOMEM;
2403
2404 id = 0;
2405 pm_runtime_set_active(dev);
2406 pm_runtime_enable(dev);
2407 /*
2408 * Prevent runtime pm from being ON by default. Users can enable
2409 * it using power/control in sysfs.
2410 */
2411 pm_runtime_forbid(dev);
2412
2413 for_each_available_child_of_node(dev->of_node, child) {
2414 /* Create per-lane phy */
2415 ret = qcom_qmp_phy_create(dev, child, id);
2416 if (ret) {
2417 dev_err(dev, "failed to create lane%d phy, %d\n",
2418 id, ret);
2419 goto err_node_put;
2420 }
2421
2422 /*
2423 * Register the pipe clock provided by phy.
2424 * See function description to see details of this pipe clock.
2425 */
2426 ret = phy_pipe_clk_register(qmp, child);
2427 if (ret) {
2428 dev_err(qmp->dev,
2429 "failed to register pipe clock source\n");
2430 goto err_node_put;
2431 }
2432 id++;
2433 }
2434
2435 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2436 if (!IS_ERR(phy_provider))
2437 dev_info(dev, "Registered Qcom-QMP phy\n");
2438 else
2439 pm_runtime_disable(dev);
2440
2441 return PTR_ERR_OR_ZERO(phy_provider);
2442
2443err_node_put:
2444 pm_runtime_disable(dev);
2445 of_node_put(child);
2446 return ret;
2447}
2448
2449static struct platform_driver qcom_qmp_phy_driver = {
2450 .probe = qcom_qmp_phy_probe,
2451 .driver = {
2452 .name = "qcom-qmp-phy",
2453 .pm = &qcom_qmp_phy_pm_ops,
2454 .of_match_table = qcom_qmp_phy_of_match_table,
2455 },
2456};
2457
2458module_platform_driver(qcom_qmp_phy_driver);
2459
2460MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2461MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2462MODULE_LICENSE("GPL v2");