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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / reset / reset-zynqmp.c
blob: 8a7473b6ba585f4d0c50a8cb5a3065abfc1ef85b [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Xilinx, Inc.
4 *
5 */
6
7#include <linux/err.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/reset-controller.h>
11#include <linux/firmware/xlnx-zynqmp.h>
12
13#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
14#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
15
16struct zynqmp_reset_data {
17 struct reset_controller_dev rcdev;
18 const struct zynqmp_eemi_ops *eemi_ops;
19};
20
21static inline struct zynqmp_reset_data *
22to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
23{
24 return container_of(rcdev, struct zynqmp_reset_data, rcdev);
25}
26
27static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
28 unsigned long id)
29{
30 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
31
32 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
33 PM_RESET_ACTION_ASSERT);
34}
35
36static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
37 unsigned long id)
38{
39 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
40
41 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
42 PM_RESET_ACTION_RELEASE);
43}
44
45static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
46 unsigned long id)
47{
48 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
49 int err;
50 u32 val;
51
52 err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, &val);
53 if (err)
54 return err;
55
56 return val;
57}
58
59static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
60 unsigned long id)
61{
62 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
63
64 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
65 PM_RESET_ACTION_PULSE);
66}
67
68static struct reset_control_ops zynqmp_reset_ops = {
69 .reset = zynqmp_reset_reset,
70 .assert = zynqmp_reset_assert,
71 .deassert = zynqmp_reset_deassert,
72 .status = zynqmp_reset_status,
73};
74
75static int zynqmp_reset_probe(struct platform_device *pdev)
76{
77 struct zynqmp_reset_data *priv;
78
79 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
80 if (!priv)
81 return -ENOMEM;
82
83 priv->eemi_ops = zynqmp_pm_get_eemi_ops();
84 if (IS_ERR(priv->eemi_ops))
85 return PTR_ERR(priv->eemi_ops);
86
87 platform_set_drvdata(pdev, priv);
88
89 priv->rcdev.ops = &zynqmp_reset_ops;
90 priv->rcdev.owner = THIS_MODULE;
91 priv->rcdev.of_node = pdev->dev.of_node;
92 priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
93
94 return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
95}
96
97static const struct of_device_id zynqmp_reset_dt_ids[] = {
98 { .compatible = "xlnx,zynqmp-reset", },
99 { /* sentinel */ },
100};
101
102static struct platform_driver zynqmp_reset_driver = {
103 .probe = zynqmp_reset_probe,
104 .driver = {
105 .name = KBUILD_MODNAME,
106 .of_match_table = zynqmp_reset_dt_ids,
107 },
108};
109
110static int __init zynqmp_reset_init(void)
111{
112 return platform_driver_register(&zynqmp_reset_driver);
113}
114
115arch_initcall(zynqmp_reset_init);