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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / scsi / megaraid / megaraid_sas_fusion.h
blob: dd2e37e40d6b0e56169e1592622a1dd6f927e089 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
5 * Copyright (c) 2009-2013 LSI Corporation
6 * Copyright (c) 2013-2016 Avago Technologies
7 * Copyright (c) 2016-2018 Broadcom Inc.
8 *
9 * FILE: megaraid_sas_fusion.h
10 *
11 * Authors: Broadcom Inc.
12 * Manoj Jose
13 * Sumant Patro
14 * Kashyap Desai <kashyap.desai@broadcom.com>
15 * Sumit Saxena <sumit.saxena@broadcom.com>
16 *
17 * Send feedback to: megaraidlinux.pdl@broadcom.com
18 */
19
20#ifndef _MEGARAID_SAS_FUSION_H_
21#define _MEGARAID_SAS_FUSION_H_
22
23/* Fusion defines */
24#define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
25#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
26#define MEGASAS_MAX_CHAIN_SHIFT 5
27#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
28#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
29#define MEGASAS_256K_IO 128
30#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
31#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
32#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
33#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
34#define MEGASAS_LOAD_BALANCE_FLAG 0x1
35#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
36#define HOST_DIAG_WRITE_ENABLE 0x80
37#define HOST_DIAG_RESET_ADAPTER 0x4
38#define MEGASAS_FUSION_MAX_RESET_TRIES 3
39#define MAX_MSIX_QUEUES_FUSION 128
40#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
41#define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
42
43/* Invader defines */
44#define MPI2_TYPE_CUDA 0x2
45#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
46#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
47#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
48#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
49#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
50#define MR_RL_WRITE_THROUGH_MODE 0x00
51#define MR_RL_WRITE_BACK_MODE 0x01
52
53/* T10 PI defines */
54#define MR_PROT_INFO_TYPE_CONTROLLER 0x8
55#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
56#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
57#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
58#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
59#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
60#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
61
62#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
63#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
64
65/*
66 * Raid context flags
67 */
68
69#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
70#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
71enum MR_RAID_FLAGS_IO_SUB_TYPE {
72 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
73 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
74 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
75 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
76 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
77 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
78 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7,
79 MR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD = 8
80};
81
82/*
83 * Request descriptor types
84 */
85#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
86#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
87#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
88#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
89
90#define MEGASAS_FP_CMD_LEN 16
91#define MEGASAS_FUSION_IN_RESET 0
92#define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
93#define RAID_1_PEER_CMDS 2
94#define JBOD_MAPS_COUNT 2
95#define MEGASAS_REDUCE_QD_COUNT 64
96#define IOC_INIT_FRAME_SIZE 4096
97
98/*
99 * Raid Context structure which describes MegaRAID specific IO Parameters
100 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
101 */
102
103struct RAID_CONTEXT {
104#if defined(__BIG_ENDIAN_BITFIELD)
105 u8 nseg:4;
106 u8 type:4;
107#else
108 u8 type:4;
109 u8 nseg:4;
110#endif
111 u8 resvd0;
112 __le16 timeout_value;
113 u8 reg_lock_flags;
114 u8 resvd1;
115 __le16 virtual_disk_tgt_id;
116 __le64 reg_lock_row_lba;
117 __le32 reg_lock_length;
118 __le16 next_lmid;
119 u8 ex_status;
120 u8 status;
121 u8 raid_flags;
122 u8 num_sge;
123 __le16 config_seq_num;
124 u8 span_arm;
125 u8 priority;
126 u8 num_sge_ext;
127 u8 resvd2;
128};
129
130/*
131 * Raid Context structure which describes ventura MegaRAID specific
132 * IO Paramenters ,This resides at offset 0x60 where the SGL normally
133 * starts in MPT IO Frames
134 */
135struct RAID_CONTEXT_G35 {
136 #define RAID_CONTEXT_NSEG_MASK 0x00F0
137 #define RAID_CONTEXT_NSEG_SHIFT 4
138 #define RAID_CONTEXT_TYPE_MASK 0x000F
139 #define RAID_CONTEXT_TYPE_SHIFT 0
140 u16 nseg_type;
141 u16 timeout_value; /* 0x02 -0x03 */
142 u16 routing_flags; // 0x04 -0x05 routing flags
143 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */
144 __le64 reg_lock_row_lba; /* 0x08 - 0x0F */
145 u32 reg_lock_length; /* 0x10 - 0x13 */
146 union { // flow specific
147 u16 rmw_op_index; /* 0x14 - 0x15, R5/6 RMW: rmw operation index*/
148 u16 peer_smid; /* 0x14 - 0x15, R1 Write: peer smid*/
149 u16 r56_arm_map; /* 0x14 - 0x15, Unused [15], LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */
150
151 } flow_specific;
152
153 u8 ex_status; /* 0x16 : OUT */
154 u8 status; /* 0x17 status */
155 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4],
156 * resvd[3:1], preferredCpu[0]
157 */
158 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */
159 u16 config_seq_num; /* 0x1A -0x1B */
160 union {
161 /*
162 * Bit format:
163 * ---------------------------------
164 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
165 * ---------------------------------
166 * Byte0 | numSGE[7]- numSGE[0] |
167 * ---------------------------------
168 * Byte1 |SD | resvd | numSGE 8-11 |
169 * --------------------------------
170 */
171 #define NUM_SGE_MASK_LOWER 0xFF
172 #define NUM_SGE_MASK_UPPER 0x0F
173 #define NUM_SGE_SHIFT_UPPER 8
174 #define STREAM_DETECT_SHIFT 7
175 #define STREAM_DETECT_MASK 0x80
176 struct {
177#if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
178 u16 stream_detected:1;
179 u16 reserved:3;
180 u16 num_sge:12;
181#else
182 u16 num_sge:12;
183 u16 reserved:3;
184 u16 stream_detected:1;
185#endif
186 } bits;
187 u8 bytes[2];
188 } u;
189 u8 resvd2[2]; /* 0x1E-0x1F */
190};
191
192#define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
193#define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
194#define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
195#define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
196#define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
197#define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
198#define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
199#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
200#define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
201#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
202#define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
203
204static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
205 u16 sge_count)
206{
207 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
208 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
209 & NUM_SGE_MASK_UPPER);
210}
211
212static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
213{
214 u16 sge_count;
215
216 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
217 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
218 return sge_count;
219}
220
221#define SET_STREAM_DETECTED(rctx_g35) \
222 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
223
224#define CLEAR_STREAM_DETECTED(rctx_g35) \
225 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
226
227static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
228{
229 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
230}
231
232union RAID_CONTEXT_UNION {
233 struct RAID_CONTEXT raid_context;
234 struct RAID_CONTEXT_G35 raid_context_g35;
235};
236
237#define RAID_CTX_SPANARM_ARM_SHIFT (0)
238#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
239
240#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
241#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
242
243/* LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */
244#define RAID_CTX_R56_Q_ARM_MASK (0x1F)
245#define RAID_CTX_R56_P_ARM_SHIFT (5)
246#define RAID_CTX_R56_P_ARM_MASK (0x3E0)
247#define RAID_CTX_R56_LOG_ARM_SHIFT (10)
248#define RAID_CTX_R56_LOG_ARM_MASK (0x7C00)
249
250/* number of bits per index in U32 TrackStream */
251#define BITS_PER_INDEX_STREAM 4
252#define INVALID_STREAM_NUM 16
253#define MR_STREAM_BITMAP 0x76543210
254#define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
255#define ZERO_LAST_STREAM 0x0fffffff
256#define MAX_STREAMS_TRACKED 8
257
258/*
259 * define region lock types
260 */
261enum REGION_TYPE {
262 REGION_TYPE_UNUSED = 0,
263 REGION_TYPE_SHARED_READ = 1,
264 REGION_TYPE_SHARED_WRITE = 2,
265 REGION_TYPE_EXCLUSIVE = 3,
266};
267
268/* MPI2 defines */
269#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
270#define MPI2_WHOINIT_HOST_DRIVER (0x04)
271#define MPI2_VERSION_MAJOR (0x02)
272#define MPI2_VERSION_MINOR (0x00)
273#define MPI2_VERSION_MAJOR_MASK (0xFF00)
274#define MPI2_VERSION_MAJOR_SHIFT (8)
275#define MPI2_VERSION_MINOR_MASK (0x00FF)
276#define MPI2_VERSION_MINOR_SHIFT (0)
277#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
278 MPI2_VERSION_MINOR)
279#define MPI2_HEADER_VERSION_UNIT (0x10)
280#define MPI2_HEADER_VERSION_DEV (0x00)
281#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
282#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
283#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
284#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
285#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
286 MPI2_HEADER_VERSION_DEV)
287#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
288#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
289#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
290#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
291#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
292#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
293#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
294/* EEDP escape mode */
295#define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
296#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
297#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
298#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
299#define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
300#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
301#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
302#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
303#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
304#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
305#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
306#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
307#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
308#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
309#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
310#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
311#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
312#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
313#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
314#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
315#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
316
317struct MPI25_IEEE_SGE_CHAIN64 {
318 __le64 Address;
319 __le32 Length;
320 __le16 Reserved1;
321 u8 NextChainOffset;
322 u8 Flags;
323};
324
325struct MPI2_SGE_SIMPLE_UNION {
326 __le32 FlagsLength;
327 union {
328 __le32 Address32;
329 __le64 Address64;
330 } u;
331};
332
333struct MPI2_SCSI_IO_CDB_EEDP32 {
334 u8 CDB[20]; /* 0x00 */
335 __be32 PrimaryReferenceTag; /* 0x14 */
336 __be16 PrimaryApplicationTag; /* 0x18 */
337 __be16 PrimaryApplicationTagMask; /* 0x1A */
338 __le32 TransferLength; /* 0x1C */
339};
340
341struct MPI2_SGE_CHAIN_UNION {
342 __le16 Length;
343 u8 NextChainOffset;
344 u8 Flags;
345 union {
346 __le32 Address32;
347 __le64 Address64;
348 } u;
349};
350
351struct MPI2_IEEE_SGE_SIMPLE32 {
352 __le32 Address;
353 __le32 FlagsLength;
354};
355
356struct MPI2_IEEE_SGE_CHAIN32 {
357 __le32 Address;
358 __le32 FlagsLength;
359};
360
361struct MPI2_IEEE_SGE_SIMPLE64 {
362 __le64 Address;
363 __le32 Length;
364 __le16 Reserved1;
365 u8 Reserved2;
366 u8 Flags;
367};
368
369struct MPI2_IEEE_SGE_CHAIN64 {
370 __le64 Address;
371 __le32 Length;
372 __le16 Reserved1;
373 u8 Reserved2;
374 u8 Flags;
375};
376
377union MPI2_IEEE_SGE_SIMPLE_UNION {
378 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
379 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
380};
381
382union MPI2_IEEE_SGE_CHAIN_UNION {
383 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
384 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
385};
386
387union MPI2_SGE_IO_UNION {
388 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
389 struct MPI2_SGE_CHAIN_UNION MpiChain;
390 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
391 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
392};
393
394union MPI2_SCSI_IO_CDB_UNION {
395 u8 CDB32[32];
396 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
397 struct MPI2_SGE_SIMPLE_UNION SGE;
398};
399
400/****************************************************************************
401* SCSI Task Management messages
402****************************************************************************/
403
404/*SCSI Task Management Request Message */
405struct MPI2_SCSI_TASK_MANAGE_REQUEST {
406 u16 DevHandle; /*0x00 */
407 u8 ChainOffset; /*0x02 */
408 u8 Function; /*0x03 */
409 u8 Reserved1; /*0x04 */
410 u8 TaskType; /*0x05 */
411 u8 Reserved2; /*0x06 */
412 u8 MsgFlags; /*0x07 */
413 u8 VP_ID; /*0x08 */
414 u8 VF_ID; /*0x09 */
415 u16 Reserved3; /*0x0A */
416 u8 LUN[8]; /*0x0C */
417 u32 Reserved4[7]; /*0x14 */
418 u16 TaskMID; /*0x30 */
419 u16 Reserved5; /*0x32 */
420};
421
422
423/*SCSI Task Management Reply Message */
424struct MPI2_SCSI_TASK_MANAGE_REPLY {
425 u16 DevHandle; /*0x00 */
426 u8 MsgLength; /*0x02 */
427 u8 Function; /*0x03 */
428 u8 ResponseCode; /*0x04 */
429 u8 TaskType; /*0x05 */
430 u8 Reserved1; /*0x06 */
431 u8 MsgFlags; /*0x07 */
432 u8 VP_ID; /*0x08 */
433 u8 VF_ID; /*0x09 */
434 u16 Reserved2; /*0x0A */
435 u16 Reserved3; /*0x0C */
436 u16 IOCStatus; /*0x0E */
437 u32 IOCLogInfo; /*0x10 */
438 u32 TerminationCount; /*0x14 */
439 u32 ResponseInfo; /*0x18 */
440};
441
442struct MR_TM_REQUEST {
443 char request[128];
444};
445
446struct MR_TM_REPLY {
447 char reply[128];
448};
449
450/* SCSI Task Management Request Message */
451struct MR_TASK_MANAGE_REQUEST {
452 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
453 struct MR_TM_REQUEST TmRequest;
454 union {
455 struct {
456#if defined(__BIG_ENDIAN_BITFIELD)
457 u32 reserved1:30;
458 u32 isTMForPD:1;
459 u32 isTMForLD:1;
460#else
461 u32 isTMForLD:1;
462 u32 isTMForPD:1;
463 u32 reserved1:30;
464#endif
465 u32 reserved2;
466 } tmReqFlags;
467 struct MR_TM_REPLY TMReply;
468 };
469};
470
471/* TaskType values */
472
473#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
474#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
475#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
476#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
477#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
478#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
479#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
480#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
481#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
482
483/* ResponseCode values */
484
485#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
486#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
487#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
488#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
489#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
490#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
491#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
492#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
493
494/*
495 * RAID SCSI IO Request Message
496 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
497 */
498struct MPI2_RAID_SCSI_IO_REQUEST {
499 __le16 DevHandle; /* 0x00 */
500 u8 ChainOffset; /* 0x02 */
501 u8 Function; /* 0x03 */
502 __le16 Reserved1; /* 0x04 */
503 u8 Reserved2; /* 0x06 */
504 u8 MsgFlags; /* 0x07 */
505 u8 VP_ID; /* 0x08 */
506 u8 VF_ID; /* 0x09 */
507 __le16 Reserved3; /* 0x0A */
508 __le32 SenseBufferLowAddress; /* 0x0C */
509 __le16 SGLFlags; /* 0x10 */
510 u8 SenseBufferLength; /* 0x12 */
511 u8 Reserved4; /* 0x13 */
512 u8 SGLOffset0; /* 0x14 */
513 u8 SGLOffset1; /* 0x15 */
514 u8 SGLOffset2; /* 0x16 */
515 u8 SGLOffset3; /* 0x17 */
516 __le32 SkipCount; /* 0x18 */
517 __le32 DataLength; /* 0x1C */
518 __le32 BidirectionalDataLength; /* 0x20 */
519 __le16 IoFlags; /* 0x24 */
520 __le16 EEDPFlags; /* 0x26 */
521 __le32 EEDPBlockSize; /* 0x28 */
522 __le32 SecondaryReferenceTag; /* 0x2C */
523 __le16 SecondaryApplicationTag; /* 0x30 */
524 __le16 ApplicationTagTranslationMask; /* 0x32 */
525 u8 LUN[8]; /* 0x34 */
526 __le32 Control; /* 0x3C */
527 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
528 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */
529 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
530};
531
532/*
533 * MPT RAID MFA IO Descriptor.
534 */
535struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
536 u32 RequestFlags:8;
537 u32 MessageAddress1:24;
538 u32 MessageAddress2;
539};
540
541/* Default Request Descriptor */
542struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
543 u8 RequestFlags; /* 0x00 */
544 u8 MSIxIndex; /* 0x01 */
545 __le16 SMID; /* 0x02 */
546 __le16 LMID; /* 0x04 */
547 __le16 DescriptorTypeDependent; /* 0x06 */
548};
549
550/* High Priority Request Descriptor */
551struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
552 u8 RequestFlags; /* 0x00 */
553 u8 MSIxIndex; /* 0x01 */
554 __le16 SMID; /* 0x02 */
555 __le16 LMID; /* 0x04 */
556 __le16 Reserved1; /* 0x06 */
557};
558
559/* SCSI IO Request Descriptor */
560struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
561 u8 RequestFlags; /* 0x00 */
562 u8 MSIxIndex; /* 0x01 */
563 __le16 SMID; /* 0x02 */
564 __le16 LMID; /* 0x04 */
565 __le16 DevHandle; /* 0x06 */
566};
567
568/* SCSI Target Request Descriptor */
569struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
570 u8 RequestFlags; /* 0x00 */
571 u8 MSIxIndex; /* 0x01 */
572 __le16 SMID; /* 0x02 */
573 __le16 LMID; /* 0x04 */
574 __le16 IoIndex; /* 0x06 */
575};
576
577/* RAID Accelerator Request Descriptor */
578struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
579 u8 RequestFlags; /* 0x00 */
580 u8 MSIxIndex; /* 0x01 */
581 __le16 SMID; /* 0x02 */
582 __le16 LMID; /* 0x04 */
583 __le16 Reserved; /* 0x06 */
584};
585
586/* union of Request Descriptors */
587union MEGASAS_REQUEST_DESCRIPTOR_UNION {
588 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
589 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
590 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
591 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
592 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
593 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
594 union {
595 struct {
596 __le32 low;
597 __le32 high;
598 } u;
599 __le64 Words;
600 };
601};
602
603/* Default Reply Descriptor */
604struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
605 u8 ReplyFlags; /* 0x00 */
606 u8 MSIxIndex; /* 0x01 */
607 __le16 DescriptorTypeDependent1; /* 0x02 */
608 __le32 DescriptorTypeDependent2; /* 0x04 */
609};
610
611/* Address Reply Descriptor */
612struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
613 u8 ReplyFlags; /* 0x00 */
614 u8 MSIxIndex; /* 0x01 */
615 __le16 SMID; /* 0x02 */
616 __le32 ReplyFrameAddress; /* 0x04 */
617};
618
619/* SCSI IO Success Reply Descriptor */
620struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
621 u8 ReplyFlags; /* 0x00 */
622 u8 MSIxIndex; /* 0x01 */
623 __le16 SMID; /* 0x02 */
624 __le16 TaskTag; /* 0x04 */
625 __le16 Reserved1; /* 0x06 */
626};
627
628/* TargetAssist Success Reply Descriptor */
629struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
630 u8 ReplyFlags; /* 0x00 */
631 u8 MSIxIndex; /* 0x01 */
632 __le16 SMID; /* 0x02 */
633 u8 SequenceNumber; /* 0x04 */
634 u8 Reserved1; /* 0x05 */
635 __le16 IoIndex; /* 0x06 */
636};
637
638/* Target Command Buffer Reply Descriptor */
639struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
640 u8 ReplyFlags; /* 0x00 */
641 u8 MSIxIndex; /* 0x01 */
642 u8 VP_ID; /* 0x02 */
643 u8 Flags; /* 0x03 */
644 __le16 InitiatorDevHandle; /* 0x04 */
645 __le16 IoIndex; /* 0x06 */
646};
647
648/* RAID Accelerator Success Reply Descriptor */
649struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
650 u8 ReplyFlags; /* 0x00 */
651 u8 MSIxIndex; /* 0x01 */
652 __le16 SMID; /* 0x02 */
653 __le32 Reserved; /* 0x04 */
654};
655
656/* union of Reply Descriptors */
657union MPI2_REPLY_DESCRIPTORS_UNION {
658 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
659 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
660 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
661 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
662 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
663 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
664 RAIDAcceleratorSuccess;
665 __le64 Words;
666};
667
668/* IOCInit Request message */
669struct MPI2_IOC_INIT_REQUEST {
670 u8 WhoInit; /* 0x00 */
671 u8 Reserved1; /* 0x01 */
672 u8 ChainOffset; /* 0x02 */
673 u8 Function; /* 0x03 */
674 __le16 Reserved2; /* 0x04 */
675 u8 Reserved3; /* 0x06 */
676 u8 MsgFlags; /* 0x07 */
677 u8 VP_ID; /* 0x08 */
678 u8 VF_ID; /* 0x09 */
679 __le16 Reserved4; /* 0x0A */
680 __le16 MsgVersion; /* 0x0C */
681 __le16 HeaderVersion; /* 0x0E */
682 u32 Reserved5; /* 0x10 */
683 __le16 Reserved6; /* 0x14 */
684 u8 HostPageSize; /* 0x16 */
685 u8 HostMSIxVectors; /* 0x17 */
686 __le16 Reserved8; /* 0x18 */
687 __le16 SystemRequestFrameSize; /* 0x1A */
688 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */
689 __le16 ReplyFreeQueueDepth; /* 0x1E */
690 __le32 SenseBufferAddressHigh; /* 0x20 */
691 __le32 SystemReplyAddressHigh; /* 0x24 */
692 __le64 SystemRequestFrameBaseAddress; /* 0x28 */
693 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */
694 __le64 ReplyFreeQueueAddress; /* 0x38 */
695 __le64 TimeStamp; /* 0x40 */
696};
697
698/* mrpriv defines */
699#define MR_PD_INVALID 0xFFFF
700#define MR_DEVHANDLE_INVALID 0xFFFF
701#define MAX_SPAN_DEPTH 8
702#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
703#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
704#define MAX_ROW_SIZE 32
705#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
706#define MAX_LOGICAL_DRIVES 64
707#define MAX_LOGICAL_DRIVES_EXT 256
708#define MAX_LOGICAL_DRIVES_DYN 512
709#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
710#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
711#define MAX_ARRAYS 128
712#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
713#define MAX_ARRAYS_EXT 256
714#define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
715#define MAX_API_ARRAYS_DYN 512
716#define MAX_PHYSICAL_DEVICES 256
717#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
718#define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
719#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
720#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
721#define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
722#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
723#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
724#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
725#define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES 0x01200100
726#define MR_DCMD_CTRL_DEVICE_LIST_GET 0x01190600
727
728struct MR_DEV_HANDLE_INFO {
729 __le16 curDevHdl;
730 u8 validHandles;
731 u8 interfaceType;
732 __le16 devHandle[2];
733};
734
735struct MR_ARRAY_INFO {
736 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
737};
738
739struct MR_QUAD_ELEMENT {
740 __le64 logStart;
741 __le64 logEnd;
742 __le64 offsetInSpan;
743 __le32 diff;
744 __le32 reserved1;
745};
746
747struct MR_SPAN_INFO {
748 __le32 noElements;
749 __le32 reserved1;
750 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
751};
752
753struct MR_LD_SPAN {
754 __le64 startBlk;
755 __le64 numBlks;
756 __le16 arrayRef;
757 u8 spanRowSize;
758 u8 spanRowDataSize;
759 u8 reserved[4];
760};
761
762struct MR_SPAN_BLOCK_INFO {
763 __le64 num_rows;
764 struct MR_LD_SPAN span;
765 struct MR_SPAN_INFO block_span_info;
766};
767
768#define MR_RAID_CTX_CPUSEL_0 0
769#define MR_RAID_CTX_CPUSEL_1 1
770#define MR_RAID_CTX_CPUSEL_2 2
771#define MR_RAID_CTX_CPUSEL_3 3
772#define MR_RAID_CTX_CPUSEL_FCFS 0xF
773
774struct MR_CPU_AFFINITY_MASK {
775 union {
776 struct {
777#ifndef MFI_BIG_ENDIAN
778 u8 hw_path:1;
779 u8 cpu0:1;
780 u8 cpu1:1;
781 u8 cpu2:1;
782 u8 cpu3:1;
783 u8 reserved:3;
784#else
785 u8 reserved:3;
786 u8 cpu3:1;
787 u8 cpu2:1;
788 u8 cpu1:1;
789 u8 cpu0:1;
790 u8 hw_path:1;
791#endif
792 };
793 u8 core_mask;
794 };
795};
796
797struct MR_IO_AFFINITY {
798 union {
799 struct {
800 struct MR_CPU_AFFINITY_MASK pdRead;
801 struct MR_CPU_AFFINITY_MASK pdWrite;
802 struct MR_CPU_AFFINITY_MASK ldRead;
803 struct MR_CPU_AFFINITY_MASK ldWrite;
804 };
805 u32 word;
806 };
807 u8 maxCores; /* Total cores + HW Path in ROC */
808 u8 reserved[3];
809};
810
811struct MR_LD_RAID {
812 struct {
813#if defined(__BIG_ENDIAN_BITFIELD)
814 u32 reserved4:2;
815 u32 fp_cache_bypass_capable:1;
816 u32 fp_rmw_capable:1;
817 u32 disable_coalescing:1;
818 u32 fpBypassRegionLock:1;
819 u32 tmCapable:1;
820 u32 fpNonRWCapable:1;
821 u32 fpReadAcrossStripe:1;
822 u32 fpWriteAcrossStripe:1;
823 u32 fpReadCapable:1;
824 u32 fpWriteCapable:1;
825 u32 encryptionType:8;
826 u32 pdPiMode:4;
827 u32 ldPiMode:4;
828 u32 reserved5:2;
829 u32 ra_capable:1;
830 u32 fpCapable:1;
831#else
832 u32 fpCapable:1;
833 u32 ra_capable:1;
834 u32 reserved5:2;
835 u32 ldPiMode:4;
836 u32 pdPiMode:4;
837 u32 encryptionType:8;
838 u32 fpWriteCapable:1;
839 u32 fpReadCapable:1;
840 u32 fpWriteAcrossStripe:1;
841 u32 fpReadAcrossStripe:1;
842 u32 fpNonRWCapable:1;
843 u32 tmCapable:1;
844 u32 fpBypassRegionLock:1;
845 u32 disable_coalescing:1;
846 u32 fp_rmw_capable:1;
847 u32 fp_cache_bypass_capable:1;
848 u32 reserved4:2;
849#endif
850 } capability;
851 __le32 reserved6;
852 __le64 size;
853 u8 spanDepth;
854 u8 level;
855 u8 stripeShift;
856 u8 rowSize;
857 u8 rowDataSize;
858 u8 writeMode;
859 u8 PRL;
860 u8 SRL;
861 __le16 targetId;
862 u8 ldState;
863 u8 regTypeReqOnWrite;
864 u8 modFactor;
865 u8 regTypeReqOnRead;
866 __le16 seqNum;
867
868 struct {
869 u32 ldSyncRequired:1;
870 u32 reserved:31;
871 } flags;
872
873 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
874 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
875 /* Ox2D This LD accept priority boost of this type */
876 u8 ld_accept_priority_type;
877 u8 reserved2[2]; /* 0x2E - 0x2F */
878 /* 0x30 - 0x33, Logical block size for the LD */
879 u32 logical_block_length;
880 struct {
881#ifndef MFI_BIG_ENDIAN
882 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
883 u32 ld_pi_exp:4;
884 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
885 * BLOCK EXPONENT from READ CAPACITY 16
886 */
887 u32 ld_logical_block_exp:4;
888 u32 reserved1:24; /* 0x34 */
889#else
890 u32 reserved1:24; /* 0x34 */
891 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
892 * BLOCK EXPONENT from READ CAPACITY 16
893 */
894 u32 ld_logical_block_exp:4;
895 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
896 u32 ld_pi_exp:4;
897#endif
898 }; /* 0x34 - 0x37 */
899 /* 0x38 - 0x3f, This will determine which
900 * core will process LD IO and PD IO.
901 */
902 struct MR_IO_AFFINITY cpuAffinity;
903 /* Bit definiations are specified by MR_IO_AFFINITY */
904 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */
905};
906
907struct MR_LD_SPAN_MAP {
908 struct MR_LD_RAID ldRaid;
909 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
910 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
911};
912
913struct MR_FW_RAID_MAP {
914 __le32 totalSize;
915 union {
916 struct {
917 __le32 maxLd;
918 __le32 maxSpanDepth;
919 __le32 maxRowSize;
920 __le32 maxPdCount;
921 __le32 maxArrays;
922 } validationInfo;
923 __le32 version[5];
924 };
925
926 __le32 ldCount;
927 __le32 Reserved1;
928 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
929 MAX_RAIDMAP_VIEWS];
930 u8 fpPdIoTimeoutSec;
931 u8 reserved2[7];
932 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
933 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
934 struct MR_LD_SPAN_MAP ldSpanMap[1];
935};
936
937struct IO_REQUEST_INFO {
938 u64 ldStartBlock;
939 u32 numBlocks;
940 u16 ldTgtId;
941 u8 isRead;
942 __le16 devHandle;
943 u8 pd_interface;
944 u64 pdBlock;
945 u8 fpOkForIo;
946 u8 IoforUnevenSpan;
947 u8 start_span;
948 u8 do_fp_rlbypass;
949 u64 start_row;
950 u8 span_arm; /* span[7:5], arm[4:0] */
951 u8 pd_after_lb;
952 u16 r1_alt_dev_handle; /* raid 1/10 only */
953 bool ra_capable;
954 u8 data_arms;
955};
956
957struct MR_LD_TARGET_SYNC {
958 u8 targetId;
959 u8 reserved;
960 __le16 seqNum;
961};
962
963/*
964 * RAID Map descriptor Types.
965 * Each element should uniquely idetify one data structure in the RAID map
966 */
967enum MR_RAID_MAP_DESC_TYPE {
968 /* MR_DEV_HANDLE_INFO data */
969 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
970 /* target to Ld num Index map */
971 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
972 /* MR_ARRAY_INFO data */
973 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
974 /* MR_LD_SPAN_MAP data */
975 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
976 RAID_MAP_DESC_TYPE_COUNT,
977};
978
979/*
980 * This table defines the offset, size and num elements of each descriptor
981 * type in the RAID Map buffer
982 */
983struct MR_RAID_MAP_DESC_TABLE {
984 /* Raid map descriptor type */
985 u32 raid_map_desc_type;
986 /* Offset into the RAID map buffer where
987 * descriptor data is saved
988 */
989 u32 raid_map_desc_offset;
990 /* total size of the
991 * descriptor buffer
992 */
993 u32 raid_map_desc_buffer_size;
994 /* Number of elements contained in the
995 * descriptor buffer
996 */
997 u32 raid_map_desc_elements;
998};
999
1000/*
1001 * Dynamic Raid Map Structure.
1002 */
1003struct MR_FW_RAID_MAP_DYNAMIC {
1004 u32 raid_map_size; /* total size of RAID Map structure */
1005 u32 desc_table_offset;/* Offset of desc table into RAID map*/
1006 u32 desc_table_size; /* Total Size of desc table */
1007 /* Total Number of elements in the desc table */
1008 u32 desc_table_num_elements;
1009 u64 reserved1;
1010 u32 reserved2[3]; /*future use */
1011 /* timeout value used by driver in FP IOs */
1012 u8 fp_pd_io_timeout_sec;
1013 u8 reserved3[3];
1014 /* when this seqNum increments, driver needs to
1015 * release RMW buffers asap
1016 */
1017 u32 rmw_fp_seq_num;
1018 u16 ld_count; /* count of lds. */
1019 u16 ar_count; /* count of arrays */
1020 u16 span_count; /* count of spans */
1021 u16 reserved4[3];
1022/*
1023 * The below structure of pointers is only to be used by the driver.
1024 * This is added in the ,API to reduce the amount of code changes
1025 * needed in the driver to support dynamic RAID map Firmware should
1026 * not update these pointers while preparing the raid map
1027 */
1028 union {
1029 struct {
1030 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1031 u16 *ld_tgt_id_to_ld;
1032 struct MR_ARRAY_INFO *ar_map_info;
1033 struct MR_LD_SPAN_MAP *ld_span_map;
1034 };
1035 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1036 };
1037/*
1038 * RAID Map descriptor table defines the layout of data in the RAID Map.
1039 * The size of the descriptor table itself could change.
1040 */
1041 /* Variable Size descriptor Table. */
1042 struct MR_RAID_MAP_DESC_TABLE
1043 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1044 /* Variable Size buffer containing all data */
1045 u32 raid_map_desc_data[1];
1046}; /* Dynamicaly sized RAID MAp structure */
1047
1048#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1049#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1050#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1051#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1052#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1053#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1054#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1055
1056#define MPI2_SGE_FLAGS_SHIFT (0x02)
1057#define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1058#define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1059#define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1060
1061#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1062#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1063#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1064#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1065
1066#define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15
1067#define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60
1068
1069struct megasas_register_set;
1070struct megasas_instance;
1071
1072union desc_word {
1073 u64 word;
1074 struct {
1075 u32 low;
1076 u32 high;
1077 } u;
1078};
1079
1080struct megasas_cmd_fusion {
1081 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1082 dma_addr_t io_request_phys_addr;
1083
1084 union MPI2_SGE_IO_UNION *sg_frame;
1085 dma_addr_t sg_frame_phys_addr;
1086
1087 u8 *sense;
1088 dma_addr_t sense_phys_addr;
1089
1090 struct list_head list;
1091 struct scsi_cmnd *scmd;
1092 struct megasas_instance *instance;
1093
1094 u8 retry_for_fw_reset;
1095 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1096
1097 /*
1098 * Context for a MFI frame.
1099 * Used to get the mfi cmd from list when a MFI cmd is completed
1100 */
1101 u32 sync_cmd_idx;
1102 u32 index;
1103 u8 pd_r1_lb;
1104 struct completion done;
1105 u8 pd_interface;
1106 u16 r1_alt_dev_handle; /* raid 1/10 only*/
1107 bool cmd_completed; /* raid 1/10 fp writes status holder */
1108
1109};
1110
1111struct LD_LOAD_BALANCE_INFO {
1112 u8 loadBalanceFlag;
1113 u8 reserved1;
1114 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1115 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
1116};
1117
1118/* SPAN_SET is info caclulated from span info from Raid map per LD */
1119typedef struct _LD_SPAN_SET {
1120 u64 log_start_lba;
1121 u64 log_end_lba;
1122 u64 span_row_start;
1123 u64 span_row_end;
1124 u64 data_strip_start;
1125 u64 data_strip_end;
1126 u64 data_row_start;
1127 u64 data_row_end;
1128 u8 strip_offset[MAX_SPAN_DEPTH];
1129 u32 span_row_data_width;
1130 u32 diff;
1131 u32 reserved[2];
1132} LD_SPAN_SET, *PLD_SPAN_SET;
1133
1134typedef struct LOG_BLOCK_SPAN_INFO {
1135 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1136} LD_SPAN_INFO, *PLD_SPAN_INFO;
1137
1138struct MR_FW_RAID_MAP_ALL {
1139 struct MR_FW_RAID_MAP raidMap;
1140 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1141} __attribute__ ((packed));
1142
1143struct MR_DRV_RAID_MAP {
1144 /* total size of this structure, including this field.
1145 * This feild will be manupulated by driver for ext raid map,
1146 * else pick the value from firmware raid map.
1147 */
1148 __le32 totalSize;
1149
1150 union {
1151 struct {
1152 __le32 maxLd;
1153 __le32 maxSpanDepth;
1154 __le32 maxRowSize;
1155 __le32 maxPdCount;
1156 __le32 maxArrays;
1157 } validationInfo;
1158 __le32 version[5];
1159 };
1160
1161 /* timeout value used by driver in FP IOs*/
1162 u8 fpPdIoTimeoutSec;
1163 u8 reserved2[7];
1164
1165 __le16 ldCount;
1166 __le16 arCount;
1167 __le16 spanCount;
1168 __le16 reserve3;
1169
1170 struct MR_DEV_HANDLE_INFO
1171 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1172 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1173 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1174 struct MR_LD_SPAN_MAP ldSpanMap[1];
1175
1176};
1177
1178/* Driver raid map size is same as raid map ext
1179 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1180 * And it is mainly for code re-use purpose.
1181 */
1182struct MR_DRV_RAID_MAP_ALL {
1183
1184 struct MR_DRV_RAID_MAP raidMap;
1185 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1186} __packed;
1187
1188
1189
1190struct MR_FW_RAID_MAP_EXT {
1191 /* Not usred in new map */
1192 u32 reserved;
1193
1194 union {
1195 struct {
1196 u32 maxLd;
1197 u32 maxSpanDepth;
1198 u32 maxRowSize;
1199 u32 maxPdCount;
1200 u32 maxArrays;
1201 } validationInfo;
1202 u32 version[5];
1203 };
1204
1205 u8 fpPdIoTimeoutSec;
1206 u8 reserved2[7];
1207
1208 __le16 ldCount;
1209 __le16 arCount;
1210 __le16 spanCount;
1211 __le16 reserve3;
1212
1213 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1214 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1215 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1216 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1217};
1218
1219/*
1220 * * define MR_PD_CFG_SEQ structure for system PDs
1221 * */
1222struct MR_PD_CFG_SEQ {
1223 u16 seqNum;
1224 u16 devHandle;
1225 struct {
1226#if defined(__BIG_ENDIAN_BITFIELD)
1227 u8 reserved:7;
1228 u8 tmCapable:1;
1229#else
1230 u8 tmCapable:1;
1231 u8 reserved:7;
1232#endif
1233 } capability;
1234 u8 reserved;
1235 u16 pd_target_id;
1236} __packed;
1237
1238struct MR_PD_CFG_SEQ_NUM_SYNC {
1239 __le32 size;
1240 __le32 count;
1241 struct MR_PD_CFG_SEQ seq[1];
1242} __packed;
1243
1244/* stream detection */
1245struct STREAM_DETECT {
1246 u64 next_seq_lba; /* next LBA to match sequential access */
1247 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1248 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1249 u32 count_cmds_in_stream; /* count of host commands in this stream */
1250 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1251 u8 is_read; /* SCSI OpCode for this stream */
1252 u8 group_depth; /* total number of host commands in group */
1253 /* TRUE if cannot add any more commands to this group */
1254 bool group_flush;
1255 u8 reserved[7]; /* pad to 64-bit alignment */
1256};
1257
1258struct LD_STREAM_DETECT {
1259 bool write_back; /* TRUE if WB, FALSE if WT */
1260 bool fp_write_enabled;
1261 bool members_ssds;
1262 bool fp_cache_bypass_capable;
1263 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1264 /* this is the array of stream detect structures (one per stream) */
1265 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1266};
1267
1268struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1269 u64 RDPQBaseAddress;
1270 u32 Reserved1;
1271 u32 Reserved2;
1272};
1273
1274struct rdpq_alloc_detail {
1275 struct dma_pool *dma_pool_ptr;
1276 dma_addr_t pool_entry_phys;
1277 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1278};
1279
1280struct fusion_context {
1281 struct megasas_cmd_fusion **cmd_list;
1282 dma_addr_t req_frames_desc_phys;
1283 u8 *req_frames_desc;
1284
1285 struct dma_pool *io_request_frames_pool;
1286 dma_addr_t io_request_frames_phys;
1287 u8 *io_request_frames;
1288
1289 struct dma_pool *sg_dma_pool;
1290 struct dma_pool *sense_dma_pool;
1291
1292 u8 *sense;
1293 dma_addr_t sense_phys_addr;
1294
1295 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1296 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1297 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
1298 struct dma_pool *reply_frames_desc_pool;
1299 struct dma_pool *reply_frames_desc_pool_align;
1300
1301 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1302
1303 u32 reply_q_depth;
1304 u32 request_alloc_sz;
1305 u32 reply_alloc_sz;
1306 u32 io_frames_alloc_sz;
1307
1308 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1309 dma_addr_t rdpq_phys;
1310 u16 max_sge_in_main_msg;
1311 u16 max_sge_in_chain;
1312
1313 u8 chain_offset_io_request;
1314 u8 chain_offset_mfi_pthru;
1315
1316 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1317 dma_addr_t ld_map_phys[2];
1318
1319 /*Non dma-able memory. Driver local copy.*/
1320 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1321
1322 u32 max_map_sz;
1323 u32 current_map_sz;
1324 u32 old_map_sz;
1325 u32 new_map_sz;
1326 u32 drv_map_sz;
1327 u32 drv_map_pages;
1328 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1329 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1330 u8 fast_path_io;
1331 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1332 u32 load_balance_info_pages;
1333 LD_SPAN_INFO *log_to_span;
1334 u32 log_to_span_pages;
1335 struct LD_STREAM_DETECT **stream_detect_by_ld;
1336 dma_addr_t ioc_init_request_phys;
1337 struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1338 struct megasas_cmd *ioc_init_cmd;
1339 bool pcie_bw_limitation;
1340 bool r56_div_offload;
1341};
1342
1343union desc_value {
1344 __le64 word;
1345 struct {
1346 __le32 low;
1347 __le32 high;
1348 } u;
1349};
1350
1351enum CMD_RET_VALUES {
1352 REFIRE_CMD = 1,
1353 COMPLETE_CMD = 2,
1354 RETURN_CMD = 3,
1355};
1356
1357struct MR_SNAPDUMP_PROPERTIES {
1358 u8 offload_num;
1359 u8 max_num_supported;
1360 u8 cur_num_supported;
1361 u8 trigger_min_num_sec_before_ocr;
1362 u8 reserved[12];
1363};
1364
1365struct megasas_debugfs_buffer {
1366 void *buf;
1367 u32 len;
1368};
1369
1370void megasas_free_cmds_fusion(struct megasas_instance *instance);
1371int megasas_ioc_init_fusion(struct megasas_instance *instance);
1372u8 megasas_get_map_info(struct megasas_instance *instance);
1373int megasas_sync_map_info(struct megasas_instance *instance);
1374void megasas_release_fusion(struct megasas_instance *instance);
1375void megasas_reset_reply_desc(struct megasas_instance *instance);
1376int megasas_check_mpio_paths(struct megasas_instance *instance,
1377 struct scsi_cmnd *scmd);
1378void megasas_fusion_ocr_wq(struct work_struct *work);
1379
1380#endif /* _MEGARAID_SAS_FUSION_H_ */