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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / drivers / scsi / mpt3sas / mpi / mpi2_cnfg.h
blob: 3a6871aecadac414976b8a44e89d28f375dfd005 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2_cnfg.h
7 * Title: MPI Configuration messages and pages
8 * Creation Date: November 10, 2006
9 *
10 * mpi2_cnfg.h Version: 02.00.47
11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 *
17 * Version History
18 * ---------------
19 *
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
24 * Added Manufacturing Page 11.
25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26 * define.
27 * 06-26-07 02.00.02 Adding generic structure for product-specific
28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29 * Rework of BIOS Page 2 configuration page.
30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31 * forms.
32 * Added configuration pages IOC Page 8 and Driver
33 * Persistent Mapping Page 0.
34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36 * RAID Physical Disk Pages 0 and 1, RAID Configuration
37 * Page 0).
38 * Added new value for AccessStatus field of SAS Device
39 * Page 0 (_SATA_NEEDS_INITIALIZATION).
40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
43 * NVDATA.
44 * Modified IOC Page 7 to use masks and added field for
45 * SASBroadcastPrimitiveMasks.
46 * Added MPI2_CONFIG_PAGE_BIOS_4.
47 * Added MPI2_CONFIG_PAGE_LOG_0.
48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
49 * Added SAS Device IDs.
50 * Updated Integrated RAID configuration pages including
51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
52 * Page 0.
53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56 * Added missing MaxNumRoutedSasAddresses field to
57 * MPI2_CONFIG_PAGE_EXPANDER_0.
58 * Added SAS Port Page 0.
59 * Modified structure layout for
60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64 * to 0x000000FF.
65 * Added two new values for the Physical Disk Coercion Size
66 * bits in the Flags field of Manufacturing Page 4.
67 * Added product-specific Manufacturing pages 16 to 31.
68 * Modified Flags bits for controlling write cache on SATA
69 * drives in IO Unit Page 1.
70 * Added new bit to AdditionalControlFlags of SAS IO Unit
71 * Page 1 to control Invalid Topology Correction.
72 * Added additional defines for RAID Volume Page 0
73 * VolumeStatusFlags field.
74 * Modified meaning of RAID Volume Page 0 VolumeSettings
75 * define for auto-configure of hot-swap drives.
76 * Added SupportedPhysDisks field to RAID Volume Page 1 and
77 * added related defines.
78 * Added PhysDiskAttributes field (and related defines) to
79 * RAID Physical Disk Page 0.
80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81 * Added three new DiscoveryStatus bits for SAS IO Unit
82 * Page 0 and SAS Expander Page 0.
83 * Removed multiplexing information from SAS IO Unit pages.
84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85 * Removed Zone Address Resolved bit from PhyInfo and from
86 * Expander Page 0 Flags field.
87 * Added two new AccessStatus values to SAS Device Page 0
88 * for indicating routing problems. Added 3 reserved words
89 * to this page.
90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
91 * Inserted missing reserved field into structure for IOC
92 * Page 6.
93 * Added more pending task bits to RAID Volume Page 0
94 * VolumeStatusFlags defines.
95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97 * and SAS Expander Page 0 to flag a downstream initiator
98 * when in simplified routing mode.
99 * Removed SATA Init Failure defines for DiscoveryStatus
100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102 * Added PortGroups, DmaGroup, and ControlGroup fields to
103 * SAS Device Page 0.
104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
105 * Unit Page 6.
106 * Added expander reduced functionality data to SAS
107 * Expander Page 0.
108 * Added SAS PHY Page 2 and SAS PHY Page 3.
109 * 07-30-09 02.00.12 Added IO Unit Page 7.
110 * Added new device ids.
111 * Added SAS IO Unit Page 5.
112 * Added partial and slumber power management capable flags
113 * to SAS Device Page 0 Flags field.
114 * Added PhyInfo defines for power condition.
115 * Added Ethernet configuration pages.
116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117 * Added SAS PHY Page 4 structure and defines.
118 * 02-10-10 02.00.14 Modified the comments for the configuration page
119 * structures that contain an array of data. The host
120 * should use the "count" field in the page data (e.g. the
121 * NumPhys field) to determine the number of valid elements
122 * in the array.
123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124 * Added PowerManagementCapabilities to IO Unit Page 7.
125 * Added PortWidthModGroup field to
126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131 * define.
132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
135 * defines.
136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138 * the Pinout field.
139 * Added BoardTemperature and BoardTemperatureUnits fields
140 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144 * Added IO Unit Page 8, IO Unit Page 9,
145 * and IO Unit Page 10.
146 * Added SASNotifyPrimitiveMasks field to
147 * MPI2_CONFIG_PAGE_IOC_7.
148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
149 * 05-25-11 02.00.20 Cleaned up a few comments.
150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
151 * for PCIe link as obsolete.
152 * Added SpinupFlags field containing a Disable Spin-up bit
153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154 * Unit Page 4.
155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156 * Added UEFIVersion field to BIOS Page 1 and defined new
157 * BiosOptions bits.
158 * Incorporating additions for MPI v2.5.
159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162 * obsolete for MPI v2.5 and later.
163 * Added some defines for 12G SAS speeds.
164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166 * match the specification.
167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168 * future use.
169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170 * MPI2_CONFIG_PAGE_MAN_7.
171 * Added EnclosureLevel and ConnectorName fields to
172 * MPI2_CONFIG_PAGE_SAS_DEV_0.
173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174 * MPI2_CONFIG_PAGE_SAS_DEV_0.
175 * Added EnclosureLevel field to
176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
180 * MPI2_CONFIG_PAGE_BIOS_1.
181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182 * more defines for the BiosOptions field.
183 * 11-18-14 02.00.30 Updated copyright information.
184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185 * Added AdapterOrderAux fields to BIOS Page 3.
186 * 03-16-15 02.00.31 Updated for MPI v2.6.
187 * Added Flags field to IO Unit Page 7.
188 * Added new SAS Phy Event codes
189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of
190 * MPI2_CONFIG_PAGE_BIOS_1.
191 * 08-25-15 02.00.34 Bumped Header Version.
192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4.
193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
194 * Added Link field to PCIe Link Pages
195 * Added EnclosureLevel and ConnectorName to PCIe
196 * Device Page 0.
197 * Added define for PCIE IoUnit page 1 max rate shift.
198 * Added comment for reserved ExtPageTypes.
199 * Added SAS 4 22.5 gbs speed support.
200 * Added PCIe 4 16.0 GT/sec speec support.
201 * Removed AHCI support.
202 * Removed SOP support.
203 * Added NegotiatedLinkRate and NegotiatedPortWidth to
204 * PCIe device page 0.
205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types.
207 * Changed declaration of ConnectorName in PCIe DevicePage0
208 * to match SAS DevicePage 0.
209 * Added SATADeviceWaitTime to IO Unit Page 11.
210 * Added MPI26_MFGPAGE_DEVID_SAS4008
211 * Added x16 PCIe width to IO Unit Page 7
212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
213 * phy data.
214 * Added InitStatus to PCIe IO Unit Page 1 header.
215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN.
219 * Added ChassisSlot field to SAS Enclosure Page 0.
220 * Added ChassisSlot Valid bit (bit 5) to the Flags field
221 * in SAS Enclosure Page 0.
222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and
223 * MPI26_MFGPAGE_DEVID_SAS3916 defines.
224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define.
225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define.
226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to
227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN.
228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to
229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK.
230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2.
231 * Added NOIOB field to PCIe Device Page 2.
232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233 * the Capabilities field of PCIe Device Page 2.
234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816.
235 * Added WRiteCache defines to IO Unit Page 1.
236 * Added MaxEnclosureLevel to BIOS Page 1.
237 * Added OEMRD to SAS Enclosure Page 1.
238 * Added DMDReportPCIe to PCIe IO Unit Page 1.
239 * Added Flags field and flags for Retimers to
240 * PCIe Switch Page 1.
241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
244 * Added DMDReport Delay Time defines to
245 * PCIeIOUnitPage1
246 * --------------------------------------------------------------------------
247 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
248 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
249 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
250 * Added DMDReport Delay Time defines to PCIeIOUnitPage1
251 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7.
252 */
253
254#ifndef MPI2_CNFG_H
255#define MPI2_CNFG_H
256
257/*****************************************************************************
258* Configuration Page Header and defines
259*****************************************************************************/
260
261/*Config Page Header */
262typedef struct _MPI2_CONFIG_PAGE_HEADER {
263 U8 PageVersion; /*0x00 */
264 U8 PageLength; /*0x01 */
265 U8 PageNumber; /*0x02 */
266 U8 PageType; /*0x03 */
267} MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
268 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
269
270typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
271 MPI2_CONFIG_PAGE_HEADER Struct;
272 U8 Bytes[4];
273 U16 Word16[2];
274 U32 Word32;
275} MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
276 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
277
278/*Extended Config Page Header */
279typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
280 U8 PageVersion; /*0x00 */
281 U8 Reserved1; /*0x01 */
282 U8 PageNumber; /*0x02 */
283 U8 PageType; /*0x03 */
284 U16 ExtPageLength; /*0x04 */
285 U8 ExtPageType; /*0x06 */
286 U8 Reserved2; /*0x07 */
287} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
288 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
289 Mpi2ConfigExtendedPageHeader_t,
290 *pMpi2ConfigExtendedPageHeader_t;
291
292typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
293 MPI2_CONFIG_PAGE_HEADER Struct;
294 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
295 U8 Bytes[8];
296 U16 Word16[4];
297 U32 Word32[2];
298} MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
299 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
300 Mpi2ConfigPageExtendedHeaderUnion,
301 *pMpi2ConfigPageExtendedHeaderUnion;
302
303
304/*PageType field values */
305#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
306#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
307#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
308#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
309
310#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
311#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
312#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
313#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
314#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
315#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
316#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
317#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
318
319#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
320
321
322/*ExtPageType field values */
323#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
324#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
325#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
326#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
327#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
328#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
329#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
330#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
331#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
332#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
333#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
334#define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B)
335#define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C)
336#define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D)
337#define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E)
338
339
340/*****************************************************************************
341* PageAddress defines
342*****************************************************************************/
343
344/*RAID Volume PageAddress format */
345#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
346#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
347#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
348
349#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
350
351
352/*RAID Physical Disk PageAddress format */
353#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
354#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
355#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
356#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
357
358#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
359#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
360
361
362/*SAS Expander PageAddress format */
363#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
364#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
365#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
366#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
367
368#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
369#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
370#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
371
372
373/*SAS Device PageAddress format */
374#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
375#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
376#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
377
378#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
379
380
381/*SAS PHY PageAddress format */
382#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
383#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
384#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
385
386#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
387#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
388
389
390/*SAS Port PageAddress format */
391#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
392#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
393#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
394
395#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
396
397
398/*SAS Enclosure PageAddress format */
399#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
400#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
401#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
402
403#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
404
405/*Enclosure PageAddress format */
406#define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000)
407#define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
408#define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
409
410#define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
411
412/*RAID Configuration PageAddress format */
413#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
414#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
415#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
416#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
417
418#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
419
420
421/*Driver Persistent Mapping PageAddress format */
422#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
423#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
424
425#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
426#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
427#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
428
429
430/*Ethernet PageAddress format */
431#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
432#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
433
434#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
435
436
437/*PCIe Switch PageAddress format */
438#define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000)
439#define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
440#define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000)
441#define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000)
442
443#define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF)
444#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000)
445#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
446
447
448/*PCIe Device PageAddress format */
449#define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000)
450#define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
451#define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000)
452
453#define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
454
455/*PCIe Link PageAddress format */
456#define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000)
457#define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
458#define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
459
460#define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF)
461
462
463
464/****************************************************************************
465* Configuration messages
466****************************************************************************/
467
468/*Configuration Request Message */
469typedef struct _MPI2_CONFIG_REQUEST {
470 U8 Action; /*0x00 */
471 U8 SGLFlags; /*0x01 */
472 U8 ChainOffset; /*0x02 */
473 U8 Function; /*0x03 */
474 U16 ExtPageLength; /*0x04 */
475 U8 ExtPageType; /*0x06 */
476 U8 MsgFlags; /*0x07 */
477 U8 VP_ID; /*0x08 */
478 U8 VF_ID; /*0x09 */
479 U16 Reserved1; /*0x0A */
480 U8 Reserved2; /*0x0C */
481 U8 ProxyVF_ID; /*0x0D */
482 U16 Reserved4; /*0x0E */
483 U32 Reserved3; /*0x10 */
484 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
485 U32 PageAddress; /*0x18 */
486 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
487} MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
488 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
489
490/*values for the Action field */
491#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
492#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
493#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
494#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
495#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
496#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
497#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
498#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
499
500/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
501
502
503/*Config Reply Message */
504typedef struct _MPI2_CONFIG_REPLY {
505 U8 Action; /*0x00 */
506 U8 SGLFlags; /*0x01 */
507 U8 MsgLength; /*0x02 */
508 U8 Function; /*0x03 */
509 U16 ExtPageLength; /*0x04 */
510 U8 ExtPageType; /*0x06 */
511 U8 MsgFlags; /*0x07 */
512 U8 VP_ID; /*0x08 */
513 U8 VF_ID; /*0x09 */
514 U16 Reserved1; /*0x0A */
515 U16 Reserved2; /*0x0C */
516 U16 IOCStatus; /*0x0E */
517 U32 IOCLogInfo; /*0x10 */
518 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
519} MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
520 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
521
522
523
524/*****************************************************************************
525*
526* C o n f i g u r a t i o n P a g e s
527*
528*****************************************************************************/
529
530/****************************************************************************
531* Manufacturing Config pages
532****************************************************************************/
533
534#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
535
536/*MPI v2.0 SAS products */
537#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
538#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
539#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
540#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
541#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
542#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
543#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
544
545#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
546
547#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
548#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
549#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
550#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
551#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
552#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
553#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
554#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
555#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
556#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP (0x02B0)
557#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 (0x02B1)
558
559/*MPI v2.5 SAS products */
560#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
561#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
562#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
563#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
564#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
565#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
566
567/* MPI v2.6 SAS Products */
568#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9)
569#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4)
570#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5)
571#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6)
572#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7)
573#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8)
574#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0)
575#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1)
576#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2)
577#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3)
578
579#define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA)
580#define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB)
581#define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC)
582#define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD)
583#define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE)
584#define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF)
585#define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0)
586#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1)
587#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2)
588
589#define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003)
590#define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0)
591#define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1)
592#define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2)
593#define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3)
594
595#define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003)
596#define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4)
597#define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5)
598#define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6)
599#define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7)
600
601
602/*Manufacturing Page 0 */
603
604typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
605 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
606 U8 ChipName[16]; /*0x04 */
607 U8 ChipRevision[8]; /*0x14 */
608 U8 BoardName[16]; /*0x1C */
609 U8 BoardAssembly[16]; /*0x2C */
610 U8 BoardTracerNumber[16]; /*0x3C */
611} MPI2_CONFIG_PAGE_MAN_0,
612 *PTR_MPI2_CONFIG_PAGE_MAN_0,
613 Mpi2ManufacturingPage0_t,
614 *pMpi2ManufacturingPage0_t;
615
616#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
617
618
619/*Manufacturing Page 1 */
620
621typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
622 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
623 U8 VPD[256]; /*0x04 */
624} MPI2_CONFIG_PAGE_MAN_1,
625 *PTR_MPI2_CONFIG_PAGE_MAN_1,
626 Mpi2ManufacturingPage1_t,
627 *pMpi2ManufacturingPage1_t;
628
629#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
630
631
632typedef struct _MPI2_CHIP_REVISION_ID {
633 U16 DeviceID; /*0x00 */
634 U8 PCIRevisionID; /*0x02 */
635 U8 Reserved; /*0x03 */
636} MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
637 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
638
639
640/*Manufacturing Page 2 */
641
642/*
643 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
644 *one and check Header.PageLength at runtime.
645 */
646#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
647#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
648#endif
649
650typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
651 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
652 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
653 U32
654 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
655} MPI2_CONFIG_PAGE_MAN_2,
656 *PTR_MPI2_CONFIG_PAGE_MAN_2,
657 Mpi2ManufacturingPage2_t,
658 *pMpi2ManufacturingPage2_t;
659
660#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
661
662
663/*Manufacturing Page 3 */
664
665/*
666 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
667 *one and check Header.PageLength at runtime.
668 */
669#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
670#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
671#endif
672
673typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
674 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
675 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
676 U32
677 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
678} MPI2_CONFIG_PAGE_MAN_3,
679 *PTR_MPI2_CONFIG_PAGE_MAN_3,
680 Mpi2ManufacturingPage3_t,
681 *pMpi2ManufacturingPage3_t;
682
683#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
684
685
686/*Manufacturing Page 4 */
687
688typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
689 U8 PowerSaveFlags; /*0x00 */
690 U8 InternalOperationsSleepTime; /*0x01 */
691 U8 InternalOperationsRunTime; /*0x02 */
692 U8 HostIdleTime; /*0x03 */
693} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
694 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
695 Mpi2ManPage4PwrSaveSettings_t,
696 *pMpi2ManPage4PwrSaveSettings_t;
697
698/*defines for the PowerSaveFlags field */
699#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
700#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
701#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
702#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
703
704typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
705 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
706 U32 Reserved1; /*0x04 */
707 U32 Flags; /*0x08 */
708 U8 InquirySize; /*0x0C */
709 U8 Reserved2; /*0x0D */
710 U16 Reserved3; /*0x0E */
711 U8 InquiryData[56]; /*0x10 */
712 U32 RAID0VolumeSettings; /*0x48 */
713 U32 RAID1EVolumeSettings; /*0x4C */
714 U32 RAID1VolumeSettings; /*0x50 */
715 U32 RAID10VolumeSettings; /*0x54 */
716 U32 Reserved4; /*0x58 */
717 U32 Reserved5; /*0x5C */
718 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
719 U8 MaxOCEDisks; /*0x64 */
720 U8 ResyncRate; /*0x65 */
721 U16 DataScrubDuration; /*0x66 */
722 U8 MaxHotSpares; /*0x68 */
723 U8 MaxPhysDisksPerVol; /*0x69 */
724 U8 MaxPhysDisks; /*0x6A */
725 U8 MaxVolumes; /*0x6B */
726} MPI2_CONFIG_PAGE_MAN_4,
727 *PTR_MPI2_CONFIG_PAGE_MAN_4,
728 Mpi2ManufacturingPage4_t,
729 *pMpi2ManufacturingPage4_t;
730
731#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
732
733/*Manufacturing Page 4 Flags field */
734#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
735#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
736
737#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
738#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
739#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
740
741#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
742#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
743#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
744#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
745#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
746
747#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
748#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
749#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
750#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
751
752#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
753#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
754#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
755#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
756#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
757#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
758#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
759#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
760
761
762/*Manufacturing Page 5 */
763
764/*
765 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
766 *one and check the value returned for NumPhys at runtime.
767 */
768#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
769#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
770#endif
771
772typedef struct _MPI2_MANUFACTURING5_ENTRY {
773 U64 WWID; /*0x00 */
774 U64 DeviceName; /*0x08 */
775} MPI2_MANUFACTURING5_ENTRY,
776 *PTR_MPI2_MANUFACTURING5_ENTRY,
777 Mpi2Manufacturing5Entry_t,
778 *pMpi2Manufacturing5Entry_t;
779
780typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
781 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
782 U8 NumPhys; /*0x04 */
783 U8 Reserved1; /*0x05 */
784 U16 Reserved2; /*0x06 */
785 U32 Reserved3; /*0x08 */
786 U32 Reserved4; /*0x0C */
787 MPI2_MANUFACTURING5_ENTRY
788 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
789} MPI2_CONFIG_PAGE_MAN_5,
790 *PTR_MPI2_CONFIG_PAGE_MAN_5,
791 Mpi2ManufacturingPage5_t,
792 *pMpi2ManufacturingPage5_t;
793
794#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
795
796
797/*Manufacturing Page 6 */
798
799typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
800 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
801 U32 ProductSpecificInfo;/*0x04 */
802} MPI2_CONFIG_PAGE_MAN_6,
803 *PTR_MPI2_CONFIG_PAGE_MAN_6,
804 Mpi2ManufacturingPage6_t,
805 *pMpi2ManufacturingPage6_t;
806
807#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
808
809
810/*Manufacturing Page 7 */
811
812typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
813 U32 Pinout; /*0x00 */
814 U8 Connector[16]; /*0x04 */
815 U8 Location; /*0x14 */
816 U8 ReceptacleID; /*0x15 */
817 U16 Slot; /*0x16 */
818 U16 Slotx2; /*0x18 */
819 U16 Slotx4; /*0x1A */
820} MPI2_MANPAGE7_CONNECTOR_INFO,
821 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
822 Mpi2ManPage7ConnectorInfo_t,
823 *pMpi2ManPage7ConnectorInfo_t;
824
825/*defines for the Pinout field */
826#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
827#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
828
829#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
830#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
831#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
832#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
833#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
834#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
835#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
836#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
837#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
838#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
839#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
840#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
841#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
842#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
843#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
844#define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E)
845#define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F)
846#define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10)
847#define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11)
848#define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12)
849#define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13)
850
851/*defines for the Location field */
852#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
853#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
854#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
855#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
856#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
857#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
858#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
859
860/*defines for the Slot field */
861#define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF)
862
863/*
864 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
865 *one and check the value returned for NumPhys at runtime.
866 */
867#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
868#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
869#endif
870
871typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
872 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
873 U32 Reserved1; /*0x04 */
874 U32 Reserved2; /*0x08 */
875 U32 Flags; /*0x0C */
876 U8 EnclosureName[16]; /*0x10 */
877 U8 NumPhys; /*0x20 */
878 U8 Reserved3; /*0x21 */
879 U16 Reserved4; /*0x22 */
880 MPI2_MANPAGE7_CONNECTOR_INFO
881 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
882} MPI2_CONFIG_PAGE_MAN_7,
883 *PTR_MPI2_CONFIG_PAGE_MAN_7,
884 Mpi2ManufacturingPage7_t,
885 *pMpi2ManufacturingPage7_t;
886
887#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
888
889/*defines for the Flags field */
890#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
891#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
892#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
893
894
895/*
896 *Generic structure to use for product-specific manufacturing pages
897 *(currently Manufacturing Page 8 through Manufacturing Page 31).
898 */
899
900typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
901 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
902 U32 ProductSpecificInfo;/*0x04 */
903} MPI2_CONFIG_PAGE_MAN_PS,
904 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
905 Mpi2ManufacturingPagePS_t,
906 *pMpi2ManufacturingPagePS_t;
907
908#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
909#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
910#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
911#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
912#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
913#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
914#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
915#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
916#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
917#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
918#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
919#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
920#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
921#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
922#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
923#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
924#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
925#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
926#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
927#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
928#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
929#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
930#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
931#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
932
933
934/****************************************************************************
935* IO Unit Config Pages
936****************************************************************************/
937
938/*IO Unit Page 0 */
939
940typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
941 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
942 U64 UniqueValue; /*0x04 */
943 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
944 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
945} MPI2_CONFIG_PAGE_IO_UNIT_0,
946 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
947 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
948
949#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
950
951
952/*IO Unit Page 1 */
953
954typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
955 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
956 U32 Flags; /*0x04 */
957} MPI2_CONFIG_PAGE_IO_UNIT_1,
958 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
959 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
960
961#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
962
963/* IO Unit Page 1 Flags defines */
964#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000)
965#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00000000)
966#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00010000)
967#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00020000)
968#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
969#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
970#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
971#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
972#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
973#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
974#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
975#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
976#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
977#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
978#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
979#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
980#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
981
982
983/*IO Unit Page 3 */
984
985/*
986 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
987 *one and check the value returned for GPIOCount at runtime.
988 */
989#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
990#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
991#endif
992
993typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
994 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
995 U8 GPIOCount; /*0x04 */
996 U8 Reserved1; /*0x05 */
997 U16 Reserved2; /*0x06 */
998 U16
999 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
1000} MPI2_CONFIG_PAGE_IO_UNIT_3,
1001 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
1002 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
1003
1004#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
1005
1006/*defines for IO Unit Page 3 GPIOVal field */
1007#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
1008#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
1009#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
1010#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
1011
1012
1013/*IO Unit Page 5 */
1014
1015/*
1016 *Upper layer code (drivers, utilities, etc.) should leave this define set to
1017 *one and check the value returned for NumDmaEngines at runtime.
1018 */
1019#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
1020#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
1021#endif
1022
1023typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
1024 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1025 U64
1026 RaidAcceleratorBufferBaseAddress; /*0x04 */
1027 U64
1028 RaidAcceleratorBufferSize; /*0x0C */
1029 U64
1030 RaidAcceleratorControlBaseAddress; /*0x14 */
1031 U8 RAControlSize; /*0x1C */
1032 U8 NumDmaEngines; /*0x1D */
1033 U8 RAMinControlSize; /*0x1E */
1034 U8 RAMaxControlSize; /*0x1F */
1035 U32 Reserved1; /*0x20 */
1036 U32 Reserved2; /*0x24 */
1037 U32 Reserved3; /*0x28 */
1038 U32
1039 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
1040} MPI2_CONFIG_PAGE_IO_UNIT_5,
1041 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
1042 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
1043
1044#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
1045
1046/*defines for IO Unit Page 5 DmaEngineCapabilities field */
1047#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
1048#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
1049
1050#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
1051#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
1052#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
1053#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
1054
1055
1056/*IO Unit Page 6 */
1057
1058typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
1059 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1060 U16 Flags; /*0x04 */
1061 U8 RAHostControlSize; /*0x06 */
1062 U8 Reserved0; /*0x07 */
1063 U64
1064 RaidAcceleratorHostControlBaseAddress; /*0x08 */
1065 U32 Reserved1; /*0x10 */
1066 U32 Reserved2; /*0x14 */
1067 U32 Reserved3; /*0x18 */
1068} MPI2_CONFIG_PAGE_IO_UNIT_6,
1069 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1070 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
1071
1072#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
1073
1074/*defines for IO Unit Page 6 Flags field */
1075#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
1076
1077
1078/*IO Unit Page 7 */
1079
1080typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
1081 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1082 U8 CurrentPowerMode; /*0x04 */
1083 U8 PreviousPowerMode; /*0x05 */
1084 U8 PCIeWidth; /*0x06 */
1085 U8 PCIeSpeed; /*0x07 */
1086 U32 ProcessorState; /*0x08 */
1087 U32
1088 PowerManagementCapabilities; /*0x0C */
1089 U16 IOCTemperature; /*0x10 */
1090 U8
1091 IOCTemperatureUnits; /*0x12 */
1092 U8 IOCSpeed; /*0x13 */
1093 U16 BoardTemperature; /*0x14 */
1094 U8
1095 BoardTemperatureUnits; /*0x16 */
1096 U8 Reserved3; /*0x17 */
1097 U32 BoardPowerRequirement; /*0x18 */
1098 U32 PCISlotPowerAllocation; /*0x1C */
1099/* reserved prior to MPI v2.6 */
1100 U8 Flags; /* 0x20 */
1101 U8 Reserved6; /* 0x21 */
1102 U16 Reserved7; /* 0x22 */
1103 U32 Reserved8; /* 0x24 */
1104} MPI2_CONFIG_PAGE_IO_UNIT_7,
1105 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1106 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
1107
1108#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05)
1109
1110/*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1111#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
1112#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
1113#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
1114#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
1115#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
1116
1117#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
1118#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
1119#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
1120#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
1121#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
1122#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
1123
1124
1125/*defines for IO Unit Page 7 PCIeWidth field */
1126#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
1127#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
1128#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
1129#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
1130#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10)
1131
1132/*defines for IO Unit Page 7 PCIeSpeed field */
1133#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
1134#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
1135#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
1136#define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03)
1137
1138/*defines for IO Unit Page 7 ProcessorState field */
1139#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
1140#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
1141
1142#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
1143#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
1144#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
1145
1146/*defines for IO Unit Page 7 PowerManagementCapabilities field */
1147#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
1148#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
1149#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
1150#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
1151#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
1152#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
1153#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
1154#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
1155#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
1156#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
1157#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1158#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1159#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1160#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1161#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1162#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
1163#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
1164#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
1165#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
1166
1167/*obsolete names for the PowerManagementCapabilities bits (above) */
1168#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1169#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1170#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1171#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
1172#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
1173
1174
1175/*defines for IO Unit Page 7 IOCTemperatureUnits field */
1176#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1177#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1178#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1179
1180/*defines for IO Unit Page 7 IOCSpeed field */
1181#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1182#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1183#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1184#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1185
1186/*defines for IO Unit Page 7 BoardTemperatureUnits field */
1187#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1188#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1189#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1190
1191/* defines for IO Unit Page 7 Flags field */
1192#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01)
1193
1194/*IO Unit Page 8 */
1195
1196#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1197
1198typedef struct _MPI2_IOUNIT8_SENSOR {
1199 U16 Flags; /*0x00 */
1200 U16 Reserved1; /*0x02 */
1201 U16
1202 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1203 U32 Reserved2; /*0x0C */
1204 U32 Reserved3; /*0x10 */
1205 U32 Reserved4; /*0x14 */
1206} MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1207 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1208
1209/*defines for IO Unit Page 8 Sensor Flags field */
1210#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1211#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1212#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1213#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1214
1215/*
1216 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1217 *one and check the value returned for NumSensors at runtime.
1218 */
1219#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1220#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
1221#endif
1222
1223typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1224 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1225 U32 Reserved1; /*0x04 */
1226 U32 Reserved2; /*0x08 */
1227 U8 NumSensors; /*0x0C */
1228 U8 PollingInterval; /*0x0D */
1229 U16 Reserved3; /*0x0E */
1230 MPI2_IOUNIT8_SENSOR
1231 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1232} MPI2_CONFIG_PAGE_IO_UNIT_8,
1233 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1234 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1235
1236#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1237
1238
1239/*IO Unit Page 9 */
1240
1241typedef struct _MPI2_IOUNIT9_SENSOR {
1242 U16 CurrentTemperature; /*0x00 */
1243 U16 Reserved1; /*0x02 */
1244 U8 Flags; /*0x04 */
1245 U8 Reserved2; /*0x05 */
1246 U16 Reserved3; /*0x06 */
1247 U32 Reserved4; /*0x08 */
1248 U32 Reserved5; /*0x0C */
1249} MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1250 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1251
1252/*defines for IO Unit Page 9 Sensor Flags field */
1253#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1254
1255/*
1256 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1257 *one and check the value returned for NumSensors at runtime.
1258 */
1259#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1260#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1261#endif
1262
1263typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1264 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1265 U32 Reserved1; /*0x04 */
1266 U32 Reserved2; /*0x08 */
1267 U8 NumSensors; /*0x0C */
1268 U8 Reserved4; /*0x0D */
1269 U16 Reserved3; /*0x0E */
1270 MPI2_IOUNIT9_SENSOR
1271 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1272} MPI2_CONFIG_PAGE_IO_UNIT_9,
1273 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1274 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1275
1276#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1277
1278
1279/*IO Unit Page 10 */
1280
1281typedef struct _MPI2_IOUNIT10_FUNCTION {
1282 U8 CreditPercent; /*0x00 */
1283 U8 Reserved1; /*0x01 */
1284 U16 Reserved2; /*0x02 */
1285} MPI2_IOUNIT10_FUNCTION,
1286 *PTR_MPI2_IOUNIT10_FUNCTION,
1287 Mpi2IOUnit10Function_t,
1288 *pMpi2IOUnit10Function_t;
1289
1290/*
1291 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1292 *one and check the value returned for NumFunctions at runtime.
1293 */
1294#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1295#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1296#endif
1297
1298typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1299 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1300 U8 NumFunctions; /*0x04 */
1301 U8 Reserved1; /*0x05 */
1302 U16 Reserved2; /*0x06 */
1303 U32 Reserved3; /*0x08 */
1304 U32 Reserved4; /*0x0C */
1305 MPI2_IOUNIT10_FUNCTION
1306 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1307} MPI2_CONFIG_PAGE_IO_UNIT_10,
1308 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1309 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1310
1311#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1312
1313
1314/* IO Unit Page 11 (for MPI v2.6 and later) */
1315
1316typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1317 U8 MaxTargetSpinup; /* 0x00 */
1318 U8 SpinupDelay; /* 0x01 */
1319 U8 SpinupFlags; /* 0x02 */
1320 U8 Reserved1; /* 0x03 */
1321} MPI26_IOUNIT11_SPINUP_GROUP,
1322 *PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1323 Mpi26IOUnit11SpinupGroup_t,
1324 *pMpi26IOUnit11SpinupGroup_t;
1325
1326/* defines for IO Unit Page 11 SpinupFlags */
1327#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01)
1328
1329
1330/*
1331 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1332 * four and check the value returned for NumPhys at runtime.
1333 */
1334#ifndef MPI26_IOUNITPAGE11_PHY_MAX
1335#define MPI26_IOUNITPAGE11_PHY_MAX (4)
1336#endif
1337
1338typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1339 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1340 U32 Reserved1; /*0x04 */
1341 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */
1342 U32 Reserved2; /*0x18 */
1343 U32 Reserved3; /*0x1C */
1344 U32 Reserved4; /*0x20 */
1345 U8 BootDeviceWaitTime; /*0x24 */
1346 U8 Reserved5; /*0x25 */
1347 U16 Reserved6; /*0x26 */
1348 U8 NumPhys; /*0x28 */
1349 U8 PEInitialSpinupDelay; /*0x29 */
1350 U8 PEReplyDelay; /*0x2A */
1351 U8 Flags; /*0x2B */
1352 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1353} MPI26_CONFIG_PAGE_IO_UNIT_11,
1354 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1355 Mpi26IOUnitPage11_t,
1356 *pMpi26IOUnitPage11_t;
1357
1358#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00)
1359
1360/* defines for Flags field */
1361#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01)
1362
1363/* defines for PHY field */
1364#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03)
1365
1366
1367
1368
1369
1370
1371/****************************************************************************
1372* IOC Config Pages
1373****************************************************************************/
1374
1375/*IOC Page 0 */
1376
1377typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1378 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1379 U32 Reserved1; /*0x04 */
1380 U32 Reserved2; /*0x08 */
1381 U16 VendorID; /*0x0C */
1382 U16 DeviceID; /*0x0E */
1383 U8 RevisionID; /*0x10 */
1384 U8 Reserved3; /*0x11 */
1385 U16 Reserved4; /*0x12 */
1386 U32 ClassCode; /*0x14 */
1387 U16 SubsystemVendorID; /*0x18 */
1388 U16 SubsystemID; /*0x1A */
1389} MPI2_CONFIG_PAGE_IOC_0,
1390 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1391 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1392
1393#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1394
1395
1396/*IOC Page 1 */
1397
1398typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1399 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1400 U32 Flags; /*0x04 */
1401 U32 CoalescingTimeout; /*0x08 */
1402 U8 CoalescingDepth; /*0x0C */
1403 U8 PCISlotNum; /*0x0D */
1404 U8 PCIBusNum; /*0x0E */
1405 U8 PCIDomainSegment; /*0x0F */
1406 U32 Reserved1; /*0x10 */
1407 U32 ProductSpecific; /* 0x14 */
1408} MPI2_CONFIG_PAGE_IOC_1,
1409 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1410 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1411
1412#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1413
1414/*defines for IOC Page 1 Flags field */
1415#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1416
1417#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1418#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1419#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1420
1421/*IOC Page 6 */
1422
1423typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1424 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1425 U32
1426 CapabilitiesFlags; /*0x04 */
1427 U8 MaxDrivesRAID0; /*0x08 */
1428 U8 MaxDrivesRAID1; /*0x09 */
1429 U8
1430 MaxDrivesRAID1E; /*0x0A */
1431 U8
1432 MaxDrivesRAID10; /*0x0B */
1433 U8 MinDrivesRAID0; /*0x0C */
1434 U8 MinDrivesRAID1; /*0x0D */
1435 U8
1436 MinDrivesRAID1E; /*0x0E */
1437 U8
1438 MinDrivesRAID10; /*0x0F */
1439 U32 Reserved1; /*0x10 */
1440 U8
1441 MaxGlobalHotSpares; /*0x14 */
1442 U8 MaxPhysDisks; /*0x15 */
1443 U8 MaxVolumes; /*0x16 */
1444 U8 MaxConfigs; /*0x17 */
1445 U8 MaxOCEDisks; /*0x18 */
1446 U8 Reserved2; /*0x19 */
1447 U16 Reserved3; /*0x1A */
1448 U32
1449 SupportedStripeSizeMapRAID0; /*0x1C */
1450 U32
1451 SupportedStripeSizeMapRAID1E; /*0x20 */
1452 U32
1453 SupportedStripeSizeMapRAID10; /*0x24 */
1454 U32 Reserved4; /*0x28 */
1455 U32 Reserved5; /*0x2C */
1456 U16
1457 DefaultMetadataSize; /*0x30 */
1458 U16 Reserved6; /*0x32 */
1459 U16
1460 MaxBadBlockTableEntries; /*0x34 */
1461 U16 Reserved7; /*0x36 */
1462 U32
1463 IRNvsramVersion; /*0x38 */
1464} MPI2_CONFIG_PAGE_IOC_6,
1465 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1466 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1467
1468#define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1469
1470/*defines for IOC Page 6 CapabilitiesFlags */
1471#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1472#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1473#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1474#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1475#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1476#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1477
1478
1479/*IOC Page 7 */
1480
1481#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1482
1483typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1484 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1485 U32 Reserved1; /*0x04 */
1486 U32
1487 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1488 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1489 U16 SASNotifyPrimitiveMasks; /*0x1A */
1490 U32 Reserved3; /*0x1C */
1491} MPI2_CONFIG_PAGE_IOC_7,
1492 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1493 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1494
1495#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1496
1497
1498/*IOC Page 8 */
1499
1500typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1501 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1502 U8 NumDevsPerEnclosure; /*0x04 */
1503 U8 Reserved1; /*0x05 */
1504 U16 Reserved2; /*0x06 */
1505 U16 MaxPersistentEntries; /*0x08 */
1506 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1507 U16 Flags; /*0x0C */
1508 U16 Reserved3; /*0x0E */
1509 U16 IRVolumeMappingFlags; /*0x10 */
1510 U16 Reserved4; /*0x12 */
1511 U32 Reserved5; /*0x14 */
1512} MPI2_CONFIG_PAGE_IOC_8,
1513 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1514 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1515
1516#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1517
1518/*defines for IOC Page 8 Flags field */
1519#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1520#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1521
1522#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1523#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1524#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1525
1526#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1527#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1528
1529/*defines for IOC Page 8 IRVolumeMappingFlags */
1530#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1531#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1532#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1533
1534
1535/****************************************************************************
1536* BIOS Config Pages
1537****************************************************************************/
1538
1539/*BIOS Page 1 */
1540
1541typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1542 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1543 U32 BiosOptions; /*0x04 */
1544 U32 IOCSettings; /*0x08 */
1545 U8 SSUTimeout; /*0x0C */
1546 U8 MaxEnclosureLevel; /*0x0D */
1547 U16 Reserved2; /*0x0E */
1548 U32 DeviceSettings; /*0x10 */
1549 U16 NumberOfDevices; /*0x14 */
1550 U16 UEFIVersion; /*0x16 */
1551 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1552 U16 IOTimeoutSequential; /*0x1A */
1553 U16 IOTimeoutOther; /*0x1C */
1554 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1555} MPI2_CONFIG_PAGE_BIOS_1,
1556 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1557 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1558
1559#define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1560
1561/*values for BIOS Page 1 BiosOptions field */
1562#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000)
1563#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000)
1564
1565#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1566#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1567#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1568#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1569#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1570#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1571
1572#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1573
1574#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1575#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1576#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1577#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1578#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1579
1580#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1581#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1582
1583#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1584#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1585#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1586#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1587
1588#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1589
1590/*values for BIOS Page 1 IOCSettings field */
1591#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1592#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1593#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1594
1595#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1596#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1597#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1598#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1599
1600#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1601#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1602#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1603#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1604#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1605
1606#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1607
1608/*values for BIOS Page 1 DeviceSettings field */
1609#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1610#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1611#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1612#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1613#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1614
1615/*defines for BIOS Page 1 UEFIVersion field */
1616#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1617#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1618#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1619#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1620
1621
1622
1623/*BIOS Page 2 */
1624
1625typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1626 U32 Reserved1; /*0x00 */
1627 U32 Reserved2; /*0x04 */
1628 U32 Reserved3; /*0x08 */
1629 U32 Reserved4; /*0x0C */
1630 U32 Reserved5; /*0x10 */
1631 U32 Reserved6; /*0x14 */
1632} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1633 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1634 Mpi2BootDeviceAdapterOrder_t,
1635 *pMpi2BootDeviceAdapterOrder_t;
1636
1637typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1638 U64 SASAddress; /*0x00 */
1639 U8 LUN[8]; /*0x08 */
1640 U32 Reserved1; /*0x10 */
1641 U32 Reserved2; /*0x14 */
1642} MPI2_BOOT_DEVICE_SAS_WWID,
1643 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1644 Mpi2BootDeviceSasWwid_t,
1645 *pMpi2BootDeviceSasWwid_t;
1646
1647typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1648 U64 EnclosureLogicalID; /*0x00 */
1649 U32 Reserved1; /*0x08 */
1650 U32 Reserved2; /*0x0C */
1651 U16 SlotNumber; /*0x10 */
1652 U16 Reserved3; /*0x12 */
1653 U32 Reserved4; /*0x14 */
1654} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1655 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1656 Mpi2BootDeviceEnclosureSlot_t,
1657 *pMpi2BootDeviceEnclosureSlot_t;
1658
1659typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1660 U64 DeviceName; /*0x00 */
1661 U8 LUN[8]; /*0x08 */
1662 U32 Reserved1; /*0x10 */
1663 U32 Reserved2; /*0x14 */
1664} MPI2_BOOT_DEVICE_DEVICE_NAME,
1665 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1666 Mpi2BootDeviceDeviceName_t,
1667 *pMpi2BootDeviceDeviceName_t;
1668
1669typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1670 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1671 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1672 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1673 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1674} MPI2_BIOSPAGE2_BOOT_DEVICE,
1675 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1676 Mpi2BiosPage2BootDevice_t,
1677 *pMpi2BiosPage2BootDevice_t;
1678
1679typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1680 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1681 U32 Reserved1; /*0x04 */
1682 U32 Reserved2; /*0x08 */
1683 U32 Reserved3; /*0x0C */
1684 U32 Reserved4; /*0x10 */
1685 U32 Reserved5; /*0x14 */
1686 U32 Reserved6; /*0x18 */
1687 U8 ReqBootDeviceForm; /*0x1C */
1688 U8 Reserved7; /*0x1D */
1689 U16 Reserved8; /*0x1E */
1690 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1691 U8 ReqAltBootDeviceForm; /*0x38 */
1692 U8 Reserved9; /*0x39 */
1693 U16 Reserved10; /*0x3A */
1694 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1695 U8 CurrentBootDeviceForm; /*0x58 */
1696 U8 Reserved11; /*0x59 */
1697 U16 Reserved12; /*0x5A */
1698 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1699} MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1700 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1701
1702#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1703
1704/*values for BIOS Page 2 BootDeviceForm fields */
1705#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1706#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1707#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1708#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1709#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1710
1711
1712/*BIOS Page 3 */
1713
1714#define MPI2_BIOSPAGE3_NUM_ADAPTER (4)
1715
1716typedef struct _MPI2_ADAPTER_INFO {
1717 U8 PciBusNumber; /*0x00 */
1718 U8 PciDeviceAndFunctionNumber; /*0x01 */
1719 U16 AdapterFlags; /*0x02 */
1720} MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1721 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1722
1723#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1724#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1725
1726typedef struct _MPI2_ADAPTER_ORDER_AUX {
1727 U64 WWID; /* 0x00 */
1728 U32 Reserved1; /* 0x08 */
1729 U32 Reserved2; /* 0x0C */
1730} MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1731 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1732
1733
1734typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1735 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1736 U32 GlobalFlags; /*0x04 */
1737 U32 BiosVersion; /*0x08 */
1738 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1739 U32 Reserved1; /*0x1C */
1740 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1741} MPI2_CONFIG_PAGE_BIOS_3,
1742 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1743 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1744
1745#define MPI2_BIOSPAGE3_PAGEVERSION (0x01)
1746
1747/*values for BIOS Page 3 GlobalFlags */
1748#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1749#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1750#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1751
1752#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1753#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1754#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1755#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1756
1757
1758/*BIOS Page 4 */
1759
1760/*
1761 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1762 *one and check the value returned for NumPhys at runtime.
1763 */
1764#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1765#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1766#endif
1767
1768typedef struct _MPI2_BIOS4_ENTRY {
1769 U64 ReassignmentWWID; /*0x00 */
1770 U64 ReassignmentDeviceName; /*0x08 */
1771} MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1772 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1773
1774typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1775 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1776 U8 NumPhys; /*0x04 */
1777 U8 Reserved1; /*0x05 */
1778 U16 Reserved2; /*0x06 */
1779 MPI2_BIOS4_ENTRY
1780 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */
1781} MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1782 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1783
1784#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1785
1786
1787/****************************************************************************
1788* RAID Volume Config Pages
1789****************************************************************************/
1790
1791/*RAID Volume Page 0 */
1792
1793typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1794 U8 RAIDSetNum; /*0x00 */
1795 U8 PhysDiskMap; /*0x01 */
1796 U8 PhysDiskNum; /*0x02 */
1797 U8 Reserved; /*0x03 */
1798} MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1799 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1800
1801/*defines for the PhysDiskMap field */
1802#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1803#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1804
1805typedef struct _MPI2_RAIDVOL0_SETTINGS {
1806 U16 Settings; /*0x00 */
1807 U8 HotSparePool; /*0x01 */
1808 U8 Reserved; /*0x02 */
1809} MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1810 Mpi2RaidVol0Settings_t,
1811 *pMpi2RaidVol0Settings_t;
1812
1813/*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1814#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1815#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1816#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1817#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1818#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1819#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1820#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1821#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1822
1823/*RAID Volume Page 0 VolumeSettings defines */
1824#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1825#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1826
1827#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1828#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1829#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1830#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1831
1832/*
1833 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1834 *one and check the value returned for NumPhysDisks at runtime.
1835 */
1836#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1837#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1838#endif
1839
1840typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1841 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1842 U16 DevHandle; /*0x04 */
1843 U8 VolumeState; /*0x06 */
1844 U8 VolumeType; /*0x07 */
1845 U32 VolumeStatusFlags; /*0x08 */
1846 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1847 U64 MaxLBA; /*0x10 */
1848 U32 StripeSize; /*0x18 */
1849 U16 BlockSize; /*0x1C */
1850 U16 Reserved1; /*0x1E */
1851 U8 SupportedPhysDisks;/*0x20 */
1852 U8 ResyncRate; /*0x21 */
1853 U16 DataScrubDuration; /*0x22 */
1854 U8 NumPhysDisks; /*0x24 */
1855 U8 Reserved2; /*0x25 */
1856 U8 Reserved3; /*0x26 */
1857 U8 InactiveStatus; /*0x27 */
1858 MPI2_RAIDVOL0_PHYS_DISK
1859 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1860} MPI2_CONFIG_PAGE_RAID_VOL_0,
1861 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1862 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1863
1864#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1865
1866/*values for RAID VolumeState */
1867#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1868#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1869#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1870#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1871#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1872#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1873
1874/*values for RAID VolumeType */
1875#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1876#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1877#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1878#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1879#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1880
1881/*values for RAID Volume Page 0 VolumeStatusFlags field */
1882#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1883#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1884#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1885#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1886#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1887#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1888#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1889#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1890#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1891#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1892#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1893#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1894#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1895#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1896#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1897#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1898#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1899#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1900#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1901
1902/*values for RAID Volume Page 0 SupportedPhysDisks field */
1903#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1904#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1905#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1906#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1907
1908/*values for RAID Volume Page 0 InactiveStatus field */
1909#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1910#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1911#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1912#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1913#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1914#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1915#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1916
1917
1918/*RAID Volume Page 1 */
1919
1920typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1921 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1922 U16 DevHandle; /*0x04 */
1923 U16 Reserved0; /*0x06 */
1924 U8 GUID[24]; /*0x08 */
1925 U8 Name[16]; /*0x20 */
1926 U64 WWID; /*0x30 */
1927 U32 Reserved1; /*0x38 */
1928 U32 Reserved2; /*0x3C */
1929} MPI2_CONFIG_PAGE_RAID_VOL_1,
1930 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1931 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1932
1933#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1934
1935
1936/****************************************************************************
1937* RAID Physical Disk Config Pages
1938****************************************************************************/
1939
1940/*RAID Physical Disk Page 0 */
1941
1942typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1943 U16 Reserved1; /*0x00 */
1944 U8 HotSparePool; /*0x02 */
1945 U8 Reserved2; /*0x03 */
1946} MPI2_RAIDPHYSDISK0_SETTINGS,
1947 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1948 Mpi2RaidPhysDisk0Settings_t,
1949 *pMpi2RaidPhysDisk0Settings_t;
1950
1951/*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1952
1953typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1954 U8 VendorID[8]; /*0x00 */
1955 U8 ProductID[16]; /*0x08 */
1956 U8 ProductRevLevel[4]; /*0x18 */
1957 U8 SerialNum[32]; /*0x1C */
1958} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1959 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1960 Mpi2RaidPhysDisk0InquiryData_t,
1961 *pMpi2RaidPhysDisk0InquiryData_t;
1962
1963typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1964 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1965 U16 DevHandle; /*0x04 */
1966 U8 Reserved1; /*0x06 */
1967 U8 PhysDiskNum; /*0x07 */
1968 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1969 U32 Reserved2; /*0x0C */
1970 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1971 U32 Reserved3; /*0x4C */
1972 U8 PhysDiskState; /*0x50 */
1973 U8 OfflineReason; /*0x51 */
1974 U8 IncompatibleReason; /*0x52 */
1975 U8 PhysDiskAttributes; /*0x53 */
1976 U32 PhysDiskStatusFlags;/*0x54 */
1977 U64 DeviceMaxLBA; /*0x58 */
1978 U64 HostMaxLBA; /*0x60 */
1979 U64 CoercedMaxLBA; /*0x68 */
1980 U16 BlockSize; /*0x70 */
1981 U16 Reserved5; /*0x72 */
1982 U32 Reserved6; /*0x74 */
1983} MPI2_CONFIG_PAGE_RD_PDISK_0,
1984 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1985 Mpi2RaidPhysDiskPage0_t,
1986 *pMpi2RaidPhysDiskPage0_t;
1987
1988#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1989
1990/*PhysDiskState defines */
1991#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1992#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1993#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1994#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1995#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1996#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1997#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1998#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1999
2000/*OfflineReason defines */
2001#define MPI2_PHYSDISK0_ONLINE (0x00)
2002#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
2003#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
2004#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
2005#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
2006#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
2007#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
2008
2009/*IncompatibleReason defines */
2010#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
2011#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
2012#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
2013#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
2014#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
2015#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
2016#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
2017#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
2018
2019/*PhysDiskAttributes defines */
2020#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
2021#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
2022#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
2023
2024#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
2025#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
2026#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
2027
2028/*PhysDiskStatusFlags defines */
2029#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
2030#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
2031#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
2032#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
2033#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
2034#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
2035#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
2036#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
2037
2038
2039/*RAID Physical Disk Page 1 */
2040
2041/*
2042 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2043 *one and check the value returned for NumPhysDiskPaths at runtime.
2044 */
2045#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
2046#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
2047#endif
2048
2049typedef struct _MPI2_RAIDPHYSDISK1_PATH {
2050 U16 DevHandle; /*0x00 */
2051 U16 Reserved1; /*0x02 */
2052 U64 WWID; /*0x04 */
2053 U64 OwnerWWID; /*0x0C */
2054 U8 OwnerIdentifier; /*0x14 */
2055 U8 Reserved2; /*0x15 */
2056 U16 Flags; /*0x16 */
2057} MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
2058 Mpi2RaidPhysDisk1Path_t,
2059 *pMpi2RaidPhysDisk1Path_t;
2060
2061/*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2062#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
2063#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2064#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2065
2066typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
2067 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
2068 U8 NumPhysDiskPaths; /*0x04 */
2069 U8 PhysDiskNum; /*0x05 */
2070 U16 Reserved1; /*0x06 */
2071 U32 Reserved2; /*0x08 */
2072 MPI2_RAIDPHYSDISK1_PATH
2073 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
2074} MPI2_CONFIG_PAGE_RD_PDISK_1,
2075 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2076 Mpi2RaidPhysDiskPage1_t,
2077 *pMpi2RaidPhysDiskPage1_t;
2078
2079#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
2080
2081
2082/****************************************************************************
2083* values for fields used by several types of SAS Config Pages
2084****************************************************************************/
2085
2086/*values for NegotiatedLinkRates fields */
2087#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
2088#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
2089#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
2090/*link rates used for Negotiated Physical and Logical Link Rate */
2091#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
2092#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
2093#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
2094#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
2095#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
2096#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
2097#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
2098#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
2099#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
2100#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
2101#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
2102#define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C)
2103
2104
2105/*values for AttachedPhyInfo fields */
2106#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
2107#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
2108#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
2109
2110#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
2111#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
2112#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
2113#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
2114#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
2115#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
2116#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
2117#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
2118#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
2119#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
2120
2121
2122/*values for PhyInfo fields */
2123#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
2124
2125#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
2126#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
2127#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
2128#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
2129#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
2130
2131#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
2132#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
2133#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
2134#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
2135#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
2136#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
2137
2138#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
2139#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
2140#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
2141#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
2142#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
2143#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
2144#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
2145#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
2146#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
2147#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
2148
2149#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
2150#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2151#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
2152#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
2153
2154#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2155#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2156
2157#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2158#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
2159#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2160#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
2161
2162
2163/*values for SAS ProgrammedLinkRate fields */
2164#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
2165#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2166#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
2167#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
2168#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
2169#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
2170#define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0)
2171#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
2172#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2173#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
2174#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
2175#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
2176#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
2177#define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C)
2178
2179
2180/*values for SAS HwLinkRate fields */
2181#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
2182#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
2183#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
2184#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
2185#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
2186#define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0)
2187#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
2188#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
2189#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
2190#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
2191#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
2192#define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C)
2193
2194
2195
2196/****************************************************************************
2197* SAS IO Unit Config Pages
2198****************************************************************************/
2199
2200/*SAS IO Unit Page 0 */
2201
2202typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2203 U8 Port; /*0x00 */
2204 U8 PortFlags; /*0x01 */
2205 U8 PhyFlags; /*0x02 */
2206 U8 NegotiatedLinkRate; /*0x03 */
2207 U32 ControllerPhyDeviceInfo;/*0x04 */
2208 U16 AttachedDevHandle; /*0x08 */
2209 U16 ControllerDevHandle; /*0x0A */
2210 U32 DiscoveryStatus; /*0x0C */
2211 U32 Reserved; /*0x10 */
2212} MPI2_SAS_IO_UNIT0_PHY_DATA,
2213 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2214 Mpi2SasIOUnit0PhyData_t,
2215 *pMpi2SasIOUnit0PhyData_t;
2216
2217/*
2218 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2219 *one and check the value returned for NumPhys at runtime.
2220 */
2221#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
2222#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
2223#endif
2224
2225typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2226 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2227 U32 Reserved1;/*0x08 */
2228 U8 NumPhys; /*0x0C */
2229 U8 Reserved2;/*0x0D */
2230 U16 Reserved3;/*0x0E */
2231 MPI2_SAS_IO_UNIT0_PHY_DATA
2232 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */
2233} MPI2_CONFIG_PAGE_SASIOUNIT_0,
2234 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2235 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2236
2237#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
2238
2239/*values for SAS IO Unit Page 0 PortFlags */
2240#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
2241#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
2242
2243/*values for SAS IO Unit Page 0 PhyFlags */
2244#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2245#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2246#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
2247#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2248
2249/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2250
2251/*see mpi2_sas.h for values for
2252 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2253
2254/*values for SAS IO Unit Page 0 DiscoveryStatus */
2255#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2256#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2257#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2258#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2259#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2260#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2261#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2262#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2263#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2264#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2265#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2266#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2267#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2268#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2269#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2270#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2271#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2272#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2273#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2274#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2275
2276
2277/*SAS IO Unit Page 1 */
2278
2279typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2280 U8 Port; /*0x00 */
2281 U8 PortFlags; /*0x01 */
2282 U8 PhyFlags; /*0x02 */
2283 U8 MaxMinLinkRate; /*0x03 */
2284 U32 ControllerPhyDeviceInfo; /*0x04 */
2285 U16 MaxTargetPortConnectTime; /*0x08 */
2286 U16 Reserved1; /*0x0A */
2287} MPI2_SAS_IO_UNIT1_PHY_DATA,
2288 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2289 Mpi2SasIOUnit1PhyData_t,
2290 *pMpi2SasIOUnit1PhyData_t;
2291
2292/*
2293 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2294 *one and check the value returned for NumPhys at runtime.
2295 */
2296#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2297#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
2298#endif
2299
2300typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2301 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2302 U16
2303 ControlFlags; /*0x08 */
2304 U16
2305 SASNarrowMaxQueueDepth; /*0x0A */
2306 U16
2307 AdditionalControlFlags; /*0x0C */
2308 U16
2309 SASWideMaxQueueDepth; /*0x0E */
2310 U8
2311 NumPhys; /*0x10 */
2312 U8
2313 SATAMaxQDepth; /*0x11 */
2314 U8
2315 ReportDeviceMissingDelay; /*0x12 */
2316 U8
2317 IODeviceMissingDelay; /*0x13 */
2318 MPI2_SAS_IO_UNIT1_PHY_DATA
2319 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */
2320} MPI2_CONFIG_PAGE_SASIOUNIT_1,
2321 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2322 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2323
2324#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2325
2326/*values for SAS IO Unit Page 1 ControlFlags */
2327#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2328#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2329#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2330#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2331
2332#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2333#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2334#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2335#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2336#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2337
2338#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2339#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2340#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2341#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2342#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2343#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2344#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2345#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2346
2347/*values for SAS IO Unit Page 1 AdditionalControlFlags */
2348#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
2349#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2350#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2351#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2352#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2353#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2354#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2355#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2356#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2357
2358/*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2359#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2360#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2361
2362/*values for SAS IO Unit Page 1 PortFlags */
2363#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2364
2365/*values for SAS IO Unit Page 1 PhyFlags */
2366#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2367#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2368#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2369#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2370
2371/*values for SAS IO Unit Page 1 MaxMinLinkRate */
2372#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2373#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2374#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2375#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2376#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2377#define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0)
2378#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2379#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2380#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2381#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2382#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2383#define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C)
2384
2385/*see mpi2_sas.h for values for
2386 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2387
2388
2389/*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2390
2391typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2392 U8 MaxTargetSpinup; /*0x00 */
2393 U8 SpinupDelay; /*0x01 */
2394 U8 SpinupFlags; /*0x02 */
2395 U8 Reserved1; /*0x03 */
2396} MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2397 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2398 Mpi2SasIOUnit4SpinupGroup_t,
2399 *pMpi2SasIOUnit4SpinupGroup_t;
2400/*defines for SAS IO Unit Page 4 SpinupFlags */
2401#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2402
2403
2404/*
2405 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2406 *one and check the value returned for NumPhys at runtime.
2407 */
2408#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2409#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2410#endif
2411
2412typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2413 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2414 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2415 SpinupGroupParameters[4]; /*0x08 */
2416 U32
2417 Reserved1; /*0x18 */
2418 U32
2419 Reserved2; /*0x1C */
2420 U32
2421 Reserved3; /*0x20 */
2422 U8
2423 BootDeviceWaitTime; /*0x24 */
2424 U8
2425 SATADeviceWaitTime; /*0x25 */
2426 U16
2427 Reserved5; /*0x26 */
2428 U8
2429 NumPhys; /*0x28 */
2430 U8
2431 PEInitialSpinupDelay; /*0x29 */
2432 U8
2433 PEReplyDelay; /*0x2A */
2434 U8
2435 Flags; /*0x2B */
2436 U8
2437 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2438} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2439 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2440 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2441
2442#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2443
2444/*defines for Flags field */
2445#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2446
2447/*defines for PHY field */
2448#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2449
2450
2451/*SAS IO Unit Page 5 */
2452
2453typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2454 U8 ControlFlags; /*0x00 */
2455 U8 PortWidthModGroup; /*0x01 */
2456 U16 InactivityTimerExponent; /*0x02 */
2457 U8 SATAPartialTimeout; /*0x04 */
2458 U8 Reserved2; /*0x05 */
2459 U8 SATASlumberTimeout; /*0x06 */
2460 U8 Reserved3; /*0x07 */
2461 U8 SASPartialTimeout; /*0x08 */
2462 U8 Reserved4; /*0x09 */
2463 U8 SASSlumberTimeout; /*0x0A */
2464 U8 Reserved5; /*0x0B */
2465} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2466 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2467 Mpi2SasIOUnit5PhyPmSettings_t,
2468 *pMpi2SasIOUnit5PhyPmSettings_t;
2469
2470/*defines for ControlFlags field */
2471#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2472#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2473#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2474#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2475
2476/*defines for PortWidthModeGroup field */
2477#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2478
2479/*defines for InactivityTimerExponent field */
2480#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2481#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2482#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2483#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2484#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2485#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2486#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2487#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2488
2489#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2490#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2491#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2492#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2493#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2494#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2495#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2496#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2497
2498/*
2499 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2500 *one and check the value returned for NumPhys at runtime.
2501 */
2502#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2503#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2504#endif
2505
2506typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2507 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2508 U8 NumPhys; /*0x08 */
2509 U8 Reserved1;/*0x09 */
2510 U16 Reserved2;/*0x0A */
2511 U32 Reserved3;/*0x0C */
2512 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2513 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2514} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2515 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2516 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2517
2518#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2519
2520
2521/*SAS IO Unit Page 6 */
2522
2523typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2524 U8 CurrentStatus; /*0x00 */
2525 U8 CurrentModulation; /*0x01 */
2526 U8 CurrentUtilization; /*0x02 */
2527 U8 Reserved1; /*0x03 */
2528 U32 Reserved2; /*0x04 */
2529} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2530 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2531 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2532 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2533
2534/*defines for CurrentStatus field */
2535#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2536#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2537#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2538#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2539#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2540#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2541#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2542#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2543
2544/*defines for CurrentModulation field */
2545#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2546#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2547#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2548#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2549
2550/*
2551 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2552 *one and check the value returned for NumGroups at runtime.
2553 */
2554#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2555#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2556#endif
2557
2558typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2559 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2560 U32 Reserved1; /*0x08 */
2561 U32 Reserved2; /*0x0C */
2562 U8 NumGroups; /*0x10 */
2563 U8 Reserved3; /*0x11 */
2564 U16 Reserved4; /*0x12 */
2565 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2566 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2567} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2568 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2569 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2570
2571#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2572
2573
2574/*SAS IO Unit Page 7 */
2575
2576typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2577 U8 Flags; /*0x00 */
2578 U8 Reserved1; /*0x01 */
2579 U16 Reserved2; /*0x02 */
2580 U8 Threshold75Pct; /*0x04 */
2581 U8 Threshold50Pct; /*0x05 */
2582 U8 Threshold25Pct; /*0x06 */
2583 U8 Reserved3; /*0x07 */
2584} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2585 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2586 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2587 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2588
2589/*defines for Flags field */
2590#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2591
2592
2593/*
2594 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2595 *one and check the value returned for NumGroups at runtime.
2596 */
2597#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2598#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2599#endif
2600
2601typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2602 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2603 U8 SamplingInterval; /*0x08 */
2604 U8 WindowLength; /*0x09 */
2605 U16 Reserved1; /*0x0A */
2606 U32 Reserved2; /*0x0C */
2607 U32 Reserved3; /*0x10 */
2608 U8 NumGroups; /*0x14 */
2609 U8 Reserved4; /*0x15 */
2610 U16 Reserved5; /*0x16 */
2611 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2612 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2613} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2614 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2615 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2616
2617#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2618
2619
2620/*SAS IO Unit Page 8 */
2621
2622typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2623 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2624 Header; /*0x00 */
2625 U32
2626 Reserved1; /*0x08 */
2627 U32
2628 PowerManagementCapabilities; /*0x0C */
2629 U8
2630 TxRxSleepStatus; /*0x10 */
2631 U8
2632 Reserved2; /*0x11 */
2633 U16
2634 Reserved3; /*0x12 */
2635} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2636 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2637 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2638
2639#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2640
2641/*defines for PowerManagementCapabilities field */
2642#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2643#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2644#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2645#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2646#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2647#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2648#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2649#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2650#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2651#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2652
2653/*defines for TxRxSleepStatus field */
2654#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2655#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2656#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2657#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2658
2659
2660
2661/*SAS IO Unit Page 16 */
2662
2663typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2664 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2665 Header; /*0x00 */
2666 U64
2667 TimeStamp; /*0x08 */
2668 U32
2669 Reserved1; /*0x10 */
2670 U32
2671 Reserved2; /*0x14 */
2672 U32
2673 FastPathPendedRequests; /*0x18 */
2674 U32
2675 FastPathUnPendedRequests; /*0x1C */
2676 U32
2677 FastPathHostRequestStarts; /*0x20 */
2678 U32
2679 FastPathFirmwareRequestStarts; /*0x24 */
2680 U32
2681 FastPathHostCompletions; /*0x28 */
2682 U32
2683 FastPathFirmwareCompletions; /*0x2C */
2684 U32
2685 NonFastPathRequestStarts; /*0x30 */
2686 U32
2687 NonFastPathHostCompletions; /*0x30 */
2688} MPI2_CONFIG_PAGE_SASIOUNIT16,
2689 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2690 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2691
2692#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2693
2694
2695/****************************************************************************
2696* SAS Expander Config Pages
2697****************************************************************************/
2698
2699/*SAS Expander Page 0 */
2700
2701typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2702 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2703 Header; /*0x00 */
2704 U8
2705 PhysicalPort; /*0x08 */
2706 U8
2707 ReportGenLength; /*0x09 */
2708 U16
2709 EnclosureHandle; /*0x0A */
2710 U64
2711 SASAddress; /*0x0C */
2712 U32
2713 DiscoveryStatus; /*0x14 */
2714 U16
2715 DevHandle; /*0x18 */
2716 U16
2717 ParentDevHandle; /*0x1A */
2718 U16
2719 ExpanderChangeCount; /*0x1C */
2720 U16
2721 ExpanderRouteIndexes; /*0x1E */
2722 U8
2723 NumPhys; /*0x20 */
2724 U8
2725 SASLevel; /*0x21 */
2726 U16
2727 Flags; /*0x22 */
2728 U16
2729 STPBusInactivityTimeLimit; /*0x24 */
2730 U16
2731 STPMaxConnectTimeLimit; /*0x26 */
2732 U16
2733 STP_SMP_NexusLossTime; /*0x28 */
2734 U16
2735 MaxNumRoutedSasAddresses; /*0x2A */
2736 U64
2737 ActiveZoneManagerSASAddress;/*0x2C */
2738 U16
2739 ZoneLockInactivityLimit; /*0x34 */
2740 U16
2741 Reserved1; /*0x36 */
2742 U8
2743 TimeToReducedFunc; /*0x38 */
2744 U8
2745 InitialTimeToReducedFunc; /*0x39 */
2746 U8
2747 MaxReducedFuncTime; /*0x3A */
2748 U8
2749 Reserved2; /*0x3B */
2750} MPI2_CONFIG_PAGE_EXPANDER_0,
2751 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2752 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2753
2754#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2755
2756/*values for SAS Expander Page 0 DiscoveryStatus field */
2757#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2758#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2759#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2760#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2761#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2762#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2763#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2764#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2765#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2766#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2767#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2768#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2769#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2770#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2771#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2772#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2773#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2774#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2775#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2776#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2777
2778/*values for SAS Expander Page 0 Flags field */
2779#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2780#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2781#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2782#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2783#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2784#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2785#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2786#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2787#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2788#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2789#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2790
2791
2792/*SAS Expander Page 1 */
2793
2794typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2795 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2796 Header; /*0x00 */
2797 U8
2798 PhysicalPort; /*0x08 */
2799 U8
2800 Reserved1; /*0x09 */
2801 U16
2802 Reserved2; /*0x0A */
2803 U8
2804 NumPhys; /*0x0C */
2805 U8
2806 Phy; /*0x0D */
2807 U16
2808 NumTableEntriesProgrammed; /*0x0E */
2809 U8
2810 ProgrammedLinkRate; /*0x10 */
2811 U8
2812 HwLinkRate; /*0x11 */
2813 U16
2814 AttachedDevHandle; /*0x12 */
2815 U32
2816 PhyInfo; /*0x14 */
2817 U32
2818 AttachedDeviceInfo; /*0x18 */
2819 U16
2820 ExpanderDevHandle; /*0x1C */
2821 U8
2822 ChangeCount; /*0x1E */
2823 U8
2824 NegotiatedLinkRate; /*0x1F */
2825 U8
2826 PhyIdentifier; /*0x20 */
2827 U8
2828 AttachedPhyIdentifier; /*0x21 */
2829 U8
2830 Reserved3; /*0x22 */
2831 U8
2832 DiscoveryInfo; /*0x23 */
2833 U32
2834 AttachedPhyInfo; /*0x24 */
2835 U8
2836 ZoneGroup; /*0x28 */
2837 U8
2838 SelfConfigStatus; /*0x29 */
2839 U16
2840 Reserved4; /*0x2A */
2841} MPI2_CONFIG_PAGE_EXPANDER_1,
2842 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2843 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2844
2845#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2846
2847/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2848
2849/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2850
2851/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2852
2853/*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2854 *used for the AttachedDeviceInfo field */
2855
2856/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2857
2858/*values for SAS Expander Page 1 DiscoveryInfo field */
2859#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2860#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2861#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2862
2863/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2864
2865
2866/****************************************************************************
2867* SAS Device Config Pages
2868****************************************************************************/
2869
2870/*SAS Device Page 0 */
2871
2872typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2873 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2874 Header; /*0x00 */
2875 U16
2876 Slot; /*0x08 */
2877 U16
2878 EnclosureHandle; /*0x0A */
2879 U64
2880 SASAddress; /*0x0C */
2881 U16
2882 ParentDevHandle; /*0x14 */
2883 U8
2884 PhyNum; /*0x16 */
2885 U8
2886 AccessStatus; /*0x17 */
2887 U16
2888 DevHandle; /*0x18 */
2889 U8
2890 AttachedPhyIdentifier; /*0x1A */
2891 U8
2892 ZoneGroup; /*0x1B */
2893 U32
2894 DeviceInfo; /*0x1C */
2895 U16
2896 Flags; /*0x20 */
2897 U8
2898 PhysicalPort; /*0x22 */
2899 U8
2900 MaxPortConnections; /*0x23 */
2901 U64
2902 DeviceName; /*0x24 */
2903 U8
2904 PortGroups; /*0x2C */
2905 U8
2906 DmaGroup; /*0x2D */
2907 U8
2908 ControlGroup; /*0x2E */
2909 U8
2910 EnclosureLevel; /*0x2F */
2911 U32
2912 ConnectorName[4]; /*0x30 */
2913 U32
2914 Reserved3; /*0x34 */
2915} MPI2_CONFIG_PAGE_SAS_DEV_0,
2916 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2917 Mpi2SasDevicePage0_t,
2918 *pMpi2SasDevicePage0_t;
2919
2920#define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2921
2922/*values for SAS Device Page 0 AccessStatus field */
2923#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2924#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2925#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2926#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2927#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2928#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2929#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2930#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2931/*specific values for SATA Init failures */
2932#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2933#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2934#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2935#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2936#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2937#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2938#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2939#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2940#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2941#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2942#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2943
2944/*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2945
2946/*values for SAS Device Page 0 Flags field */
2947#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2948#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2949#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2950#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2951#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2952#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2953#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2954#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2955#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2956#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2957#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2958#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2959#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2960#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004)
2961#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2962#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2963
2964
2965/*SAS Device Page 1 */
2966
2967typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2968 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2969 Header; /*0x00 */
2970 U32
2971 Reserved1; /*0x08 */
2972 U64
2973 SASAddress; /*0x0C */
2974 U32
2975 Reserved2; /*0x14 */
2976 U16
2977 DevHandle; /*0x18 */
2978 U16
2979 Reserved3; /*0x1A */
2980 U8
2981 InitialRegDeviceFIS[20];/*0x1C */
2982} MPI2_CONFIG_PAGE_SAS_DEV_1,
2983 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2984 Mpi2SasDevicePage1_t,
2985 *pMpi2SasDevicePage1_t;
2986
2987#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2988
2989
2990/****************************************************************************
2991* SAS PHY Config Pages
2992****************************************************************************/
2993
2994/*SAS PHY Page 0 */
2995
2996typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2997 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2998 Header; /*0x00 */
2999 U16
3000 OwnerDevHandle; /*0x08 */
3001 U16
3002 Reserved1; /*0x0A */
3003 U16
3004 AttachedDevHandle; /*0x0C */
3005 U8
3006 AttachedPhyIdentifier; /*0x0E */
3007 U8
3008 Reserved2; /*0x0F */
3009 U32
3010 AttachedPhyInfo; /*0x10 */
3011 U8
3012 ProgrammedLinkRate; /*0x14 */
3013 U8
3014 HwLinkRate; /*0x15 */
3015 U8
3016 ChangeCount; /*0x16 */
3017 U8
3018 Flags; /*0x17 */
3019 U32
3020 PhyInfo; /*0x18 */
3021 U8
3022 NegotiatedLinkRate; /*0x1C */
3023 U8
3024 Reserved3; /*0x1D */
3025 U16
3026 Reserved4; /*0x1E */
3027} MPI2_CONFIG_PAGE_SAS_PHY_0,
3028 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
3029 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
3030
3031#define MPI2_SASPHY0_PAGEVERSION (0x03)
3032
3033/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
3034
3035/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
3036
3037/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
3038
3039/*values for SAS PHY Page 0 Flags field */
3040#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
3041
3042/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
3043
3044/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3045
3046
3047/*SAS PHY Page 1 */
3048
3049typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
3050 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3051 Header; /*0x00 */
3052 U32
3053 Reserved1; /*0x08 */
3054 U32
3055 InvalidDwordCount; /*0x0C */
3056 U32
3057 RunningDisparityErrorCount; /*0x10 */
3058 U32
3059 LossDwordSynchCount; /*0x14 */
3060 U32
3061 PhyResetProblemCount; /*0x18 */
3062} MPI2_CONFIG_PAGE_SAS_PHY_1,
3063 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
3064 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
3065
3066#define MPI2_SASPHY1_PAGEVERSION (0x01)
3067
3068
3069/*SAS PHY Page 2 */
3070
3071typedef struct _MPI2_SASPHY2_PHY_EVENT {
3072 U8 PhyEventCode; /*0x00 */
3073 U8 Reserved1; /*0x01 */
3074 U16 Reserved2; /*0x02 */
3075 U32 PhyEventInfo; /*0x04 */
3076} MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
3077 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
3078
3079/*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
3080
3081
3082/*
3083 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3084 *one and check the value returned for NumPhyEvents at runtime.
3085 */
3086#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
3087#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
3088#endif
3089
3090typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
3091 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3092 Header; /*0x00 */
3093 U32
3094 Reserved1; /*0x08 */
3095 U8
3096 NumPhyEvents; /*0x0C */
3097 U8
3098 Reserved2; /*0x0D */
3099 U16
3100 Reserved3; /*0x0E */
3101 MPI2_SASPHY2_PHY_EVENT
3102 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
3103} MPI2_CONFIG_PAGE_SAS_PHY_2,
3104 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
3105 Mpi2SasPhyPage2_t,
3106 *pMpi2SasPhyPage2_t;
3107
3108#define MPI2_SASPHY2_PAGEVERSION (0x00)
3109
3110
3111/*SAS PHY Page 3 */
3112
3113typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
3114 U8 PhyEventCode; /*0x00 */
3115 U8 Reserved1; /*0x01 */
3116 U16 Reserved2; /*0x02 */
3117 U8 CounterType; /*0x04 */
3118 U8 ThresholdWindow; /*0x05 */
3119 U8 TimeUnits; /*0x06 */
3120 U8 Reserved3; /*0x07 */
3121 U32 EventThreshold; /*0x08 */
3122 U16 ThresholdFlags; /*0x0C */
3123 U16 Reserved4; /*0x0E */
3124} MPI2_SASPHY3_PHY_EVENT_CONFIG,
3125 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
3126 Mpi2SasPhy3PhyEventConfig_t,
3127 *pMpi2SasPhy3PhyEventConfig_t;
3128
3129/*values for PhyEventCode field */
3130#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
3131#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
3132#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
3133#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
3134#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
3135#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
3136#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
3137#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
3138#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
3139#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
3140#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
3141#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
3142#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
3143#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
3144#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
3145#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
3146#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
3147#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
3148#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
3149#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
3150#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
3151#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
3152#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
3153#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
3154#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
3155#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
3156#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
3157#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
3158#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
3159#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
3160#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
3161#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
3162#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
3163#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
3164#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
3165#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
3166#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
3167
3168/*Following codes are product specific and in MPI v2.6 and later */
3169#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3)
3170#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4)
3171#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5)
3172#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6)
3173#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7)
3174#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8)
3175#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9)
3176#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA)
3177#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB)
3178#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC)
3179
3180
3181/*values for the CounterType field */
3182#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
3183#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
3184#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
3185
3186/*values for the TimeUnits field */
3187#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
3188#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
3189#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
3190#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
3191
3192/*values for the ThresholdFlags field */
3193#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
3194#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
3195
3196/*
3197 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3198 *one and check the value returned for NumPhyEvents at runtime.
3199 */
3200#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
3201#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
3202#endif
3203
3204typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3205 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3206 Header; /*0x00 */
3207 U32
3208 Reserved1; /*0x08 */
3209 U8
3210 NumPhyEvents; /*0x0C */
3211 U8
3212 Reserved2; /*0x0D */
3213 U16
3214 Reserved3; /*0x0E */
3215 MPI2_SASPHY3_PHY_EVENT_CONFIG
3216 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
3217} MPI2_CONFIG_PAGE_SAS_PHY_3,
3218 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3219 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3220
3221#define MPI2_SASPHY3_PAGEVERSION (0x00)
3222
3223
3224/*SAS PHY Page 4 */
3225
3226typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3227 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3228 Header; /*0x00 */
3229 U16
3230 Reserved1; /*0x08 */
3231 U8
3232 Reserved2; /*0x0A */
3233 U8
3234 Flags; /*0x0B */
3235 U8
3236 InitialFrame[28]; /*0x0C */
3237} MPI2_CONFIG_PAGE_SAS_PHY_4,
3238 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3239 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3240
3241#define MPI2_SASPHY4_PAGEVERSION (0x00)
3242
3243/*values for the Flags field */
3244#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
3245#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
3246
3247
3248
3249
3250/****************************************************************************
3251* SAS Port Config Pages
3252****************************************************************************/
3253
3254/*SAS Port Page 0 */
3255
3256typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3257 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3258 Header; /*0x00 */
3259 U8
3260 PortNumber; /*0x08 */
3261 U8
3262 PhysicalPort; /*0x09 */
3263 U8
3264 PortWidth; /*0x0A */
3265 U8
3266 PhysicalPortWidth; /*0x0B */
3267 U8
3268 ZoneGroup; /*0x0C */
3269 U8
3270 Reserved1; /*0x0D */
3271 U16
3272 Reserved2; /*0x0E */
3273 U64
3274 SASAddress; /*0x10 */
3275 U32
3276 DeviceInfo; /*0x18 */
3277 U32
3278 Reserved3; /*0x1C */
3279 U32
3280 Reserved4; /*0x20 */
3281} MPI2_CONFIG_PAGE_SAS_PORT_0,
3282 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3283 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3284
3285#define MPI2_SASPORT0_PAGEVERSION (0x00)
3286
3287/*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3288
3289
3290/****************************************************************************
3291* SAS Enclosure Config Pages
3292****************************************************************************/
3293
3294/*SAS Enclosure Page 0 */
3295
3296typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3297 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3298 U32 Reserved1; /*0x08 */
3299 U64 EnclosureLogicalID; /*0x0C */
3300 U16 Flags; /*0x14 */
3301 U16 EnclosureHandle; /*0x16 */
3302 U16 NumSlots; /*0x18 */
3303 U16 StartSlot; /*0x1A */
3304 U8 ChassisSlot; /*0x1C */
3305 U8 EnclosureLevel; /*0x1D */
3306 U16 SEPDevHandle; /*0x1E */
3307 U8 OEMRD; /*0x20 */
3308 U8 Reserved1a; /*0x21 */
3309 U16 Reserved2; /*0x22 */
3310 U32 Reserved3; /*0x24 */
3311} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3312 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3313 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
3314 MPI26_CONFIG_PAGE_ENCLOSURE_0,
3315 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3316 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t;
3317
3318#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3319
3320/*values for SAS Enclosure Page 0 Flags field */
3321#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3322#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3323#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3324#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3325#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3326#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3327#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3328#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3329#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3330#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3331#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3332
3333#define MPI26_ENCLOSURE0_PAGEVERSION (0x04)
3334
3335/*Values for Enclosure Page 0 Flags field */
3336#define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3337#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3338#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3339#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3340#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F)
3341#define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3342#define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3343#define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3344#define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3345#define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3346#define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3347
3348/****************************************************************************
3349* Log Config Page
3350****************************************************************************/
3351
3352/*Log Page 0 */
3353
3354/*
3355 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3356 *one and check the value returned for NumLogEntries at runtime.
3357 */
3358#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3359#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
3360#endif
3361
3362#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3363
3364typedef struct _MPI2_LOG_0_ENTRY {
3365 U64 TimeStamp; /*0x00 */
3366 U32 Reserved1; /*0x08 */
3367 U16 LogSequence; /*0x0C */
3368 U16 LogEntryQualifier; /*0x0E */
3369 U8 VP_ID; /*0x10 */
3370 U8 VF_ID; /*0x11 */
3371 U16 Reserved2; /*0x12 */
3372 U8
3373 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3374} MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3375 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3376
3377/*values for Log Page 0 LogEntry LogEntryQualifier field */
3378#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3379#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3380#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3381#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3382#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3383
3384typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3385 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3386 U32 Reserved1; /*0x08 */
3387 U32 Reserved2; /*0x0C */
3388 U16 NumLogEntries;/*0x10 */
3389 U16 Reserved3; /*0x12 */
3390 MPI2_LOG_0_ENTRY
3391 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3392} MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3393 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3394
3395#define MPI2_LOG_0_PAGEVERSION (0x02)
3396
3397
3398/****************************************************************************
3399* RAID Config Page
3400****************************************************************************/
3401
3402/*RAID Page 0 */
3403
3404/*
3405 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3406 *one and check the value returned for NumElements at runtime.
3407 */
3408#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3409#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
3410#endif
3411
3412typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3413 U16 ElementFlags; /*0x00 */
3414 U16 VolDevHandle; /*0x02 */
3415 U8 HotSparePool; /*0x04 */
3416 U8 PhysDiskNum; /*0x05 */
3417 U16 PhysDiskDevHandle; /*0x06 */
3418} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3419 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3420 Mpi2RaidConfig0ConfigElement_t,
3421 *pMpi2RaidConfig0ConfigElement_t;
3422
3423/*values for the ElementFlags field */
3424#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3425#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3426#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3427#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3428#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3429
3430
3431typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3432 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3433 U8 NumHotSpares; /*0x08 */
3434 U8 NumPhysDisks; /*0x09 */
3435 U8 NumVolumes; /*0x0A */
3436 U8 ConfigNum; /*0x0B */
3437 U32 Flags; /*0x0C */
3438 U8 ConfigGUID[24]; /*0x10 */
3439 U32 Reserved1; /*0x28 */
3440 U8 NumElements; /*0x2C */
3441 U8 Reserved2; /*0x2D */
3442 U16 Reserved3; /*0x2E */
3443 MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3444 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3445} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3446 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3447 Mpi2RaidConfigurationPage0_t,
3448 *pMpi2RaidConfigurationPage0_t;
3449
3450#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3451
3452/*values for RAID Configuration Page 0 Flags field */
3453#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3454
3455
3456/****************************************************************************
3457* Driver Persistent Mapping Config Pages
3458****************************************************************************/
3459
3460/*Driver Persistent Mapping Page 0 */
3461
3462typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3463 U64 PhysicalIdentifier; /*0x00 */
3464 U16 MappingInformation; /*0x08 */
3465 U16 DeviceIndex; /*0x0A */
3466 U32 PhysicalBitsMapping; /*0x0C */
3467 U32 Reserved1; /*0x10 */
3468} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3469 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3470 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3471
3472typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3473 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3474 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3475} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3476 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3477 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3478
3479#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3480
3481/*values for Driver Persistent Mapping Page 0 MappingInformation field */
3482#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3483#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3484#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3485
3486
3487/****************************************************************************
3488* Ethernet Config Pages
3489****************************************************************************/
3490
3491/*Ethernet Page 0 */
3492
3493/*IP address (union of IPv4 and IPv6) */
3494typedef union _MPI2_ETHERNET_IP_ADDR {
3495 U32 IPv4Addr;
3496 U32 IPv6Addr[4];
3497} MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3498 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3499
3500#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3501
3502typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3503 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3504 U8 NumInterfaces; /*0x08 */
3505 U8 Reserved0; /*0x09 */
3506 U16 Reserved1; /*0x0A */
3507 U32 Status; /*0x0C */
3508 U8 MediaState; /*0x10 */
3509 U8 Reserved2; /*0x11 */
3510 U16 Reserved3; /*0x12 */
3511 U8 MacAddress[6]; /*0x14 */
3512 U8 Reserved4; /*0x1A */
3513 U8 Reserved5; /*0x1B */
3514 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3515 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3516 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3517 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3518 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3519 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3520 U8
3521 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3522} MPI2_CONFIG_PAGE_ETHERNET_0,
3523 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3524 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3525
3526#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3527
3528/*values for Ethernet Page 0 Status field */
3529#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3530#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3531#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3532#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3533#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3534#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3535#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3536#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3537#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3538#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3539#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3540#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3541
3542/*values for Ethernet Page 0 MediaState field */
3543#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3544#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3545#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3546
3547#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3548#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3549#define MPI2_ETHPG0_MS_10MBIT (0x01)
3550#define MPI2_ETHPG0_MS_100MBIT (0x02)
3551#define MPI2_ETHPG0_MS_1GBIT (0x03)
3552
3553
3554/*Ethernet Page 1 */
3555
3556typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3557 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3558 Header; /*0x00 */
3559 U32
3560 Reserved0; /*0x08 */
3561 U32
3562 Flags; /*0x0C */
3563 U8
3564 MediaState; /*0x10 */
3565 U8
3566 Reserved1; /*0x11 */
3567 U16
3568 Reserved2; /*0x12 */
3569 U8
3570 MacAddress[6]; /*0x14 */
3571 U8
3572 Reserved3; /*0x1A */
3573 U8
3574 Reserved4; /*0x1B */
3575 MPI2_ETHERNET_IP_ADDR
3576 StaticIpAddress; /*0x1C */
3577 MPI2_ETHERNET_IP_ADDR
3578 StaticSubnetMask; /*0x2C */
3579 MPI2_ETHERNET_IP_ADDR
3580 StaticGatewayIpAddress; /*0x3C */
3581 MPI2_ETHERNET_IP_ADDR
3582 StaticDNS1IpAddress; /*0x4C */
3583 MPI2_ETHERNET_IP_ADDR
3584 StaticDNS2IpAddress; /*0x5C */
3585 U32
3586 Reserved5; /*0x6C */
3587 U32
3588 Reserved6; /*0x70 */
3589 U32
3590 Reserved7; /*0x74 */
3591 U32
3592 Reserved8; /*0x78 */
3593 U8
3594 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3595} MPI2_CONFIG_PAGE_ETHERNET_1,
3596 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3597 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3598
3599#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3600
3601/*values for Ethernet Page 1 Flags field */
3602#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3603#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3604#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3605#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3606#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3607#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3608#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3609#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3610#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3611
3612/*values for Ethernet Page 1 MediaState field */
3613#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3614#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3615#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3616
3617#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3618#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3619#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3620#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3621#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3622
3623
3624/****************************************************************************
3625* Extended Manufacturing Config Pages
3626****************************************************************************/
3627
3628/*
3629 *Generic structure to use for product-specific extended manufacturing pages
3630 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3631 *Page 60).
3632 */
3633
3634typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3635 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3636 Header; /*0x00 */
3637 U32
3638 ProductSpecificInfo; /*0x08 */
3639} MPI2_CONFIG_PAGE_EXT_MAN_PS,
3640 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3641 Mpi2ExtManufacturingPagePS_t,
3642 *pMpi2ExtManufacturingPagePS_t;
3643
3644/*PageVersion should be provided by product-specific code */
3645
3646
3647
3648/****************************************************************************
3649* values for fields used by several types of PCIe Config Pages
3650****************************************************************************/
3651
3652/*values for NegotiatedLinkRates fields */
3653#define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
3654/*link rates used for Negotiated Physical Link Rate */
3655#define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
3656#define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
3657#define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02)
3658#define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03)
3659#define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04)
3660#define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05)
3661
3662
3663/****************************************************************************
3664* PCIe IO Unit Config Pages (MPI v2.6 and later)
3665****************************************************************************/
3666
3667/*PCIe IO Unit Page 0 */
3668
3669typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA {
3670 U8 Link; /*0x00 */
3671 U8 LinkFlags; /*0x01 */
3672 U8 PhyFlags; /*0x02 */
3673 U8 NegotiatedLinkRate; /*0x03 */
3674 U32 ControllerPhyDeviceInfo;/*0x04 */
3675 U16 AttachedDevHandle; /*0x08 */
3676 U16 ControllerDevHandle; /*0x0A */
3677 U32 EnumerationStatus; /*0x0C */
3678 U32 Reserved1; /*0x10 */
3679} MPI26_PCIE_IO_UNIT0_PHY_DATA,
3680 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3681 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t;
3682
3683/*
3684 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3685 *one and check the value returned for NumPhys at runtime.
3686 */
3687#ifndef MPI26_PCIE_IOUNIT0_PHY_MAX
3688#define MPI26_PCIE_IOUNIT0_PHY_MAX (1)
3689#endif
3690
3691typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 {
3692 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3693 U32 Reserved1; /*0x08 */
3694 U8 NumPhys; /*0x0C */
3695 U8 InitStatus; /*0x0D */
3696 U16 Reserved3; /*0x0E */
3697 MPI26_PCIE_IO_UNIT0_PHY_DATA
3698 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /*0x10 */
3699} MPI26_CONFIG_PAGE_PIOUNIT_0,
3700 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3701 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t;
3702
3703#define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00)
3704
3705/*values for PCIe IO Unit Page 0 LinkFlags */
3706#define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3707
3708/*values for PCIe IO Unit Page 0 PhyFlags */
3709#define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
3710
3711/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3712
3713/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3714 *values
3715 */
3716
3717/*values for PCIe IO Unit Page 0 EnumerationStatus */
3718#define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
3719#define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000)
3720
3721
3722/*PCIe IO Unit Page 1 */
3723
3724typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3725 U8 Link; /*0x00 */
3726 U8 LinkFlags; /*0x01 */
3727 U8 PhyFlags; /*0x02 */
3728 U8 MaxMinLinkRate; /*0x03 */
3729 U32 ControllerPhyDeviceInfo; /*0x04 */
3730 U32 Reserved1; /*0x08 */
3731} MPI26_PCIE_IO_UNIT1_PHY_DATA,
3732 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3733 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3734
3735/*values for LinkFlags */
3736#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00)
3737#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01)
3738#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02)
3739
3740/*
3741 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3742 *one and check the value returned for NumPhys at runtime.
3743 */
3744#ifndef MPI26_PCIE_IOUNIT1_PHY_MAX
3745#define MPI26_PCIE_IOUNIT1_PHY_MAX (1)
3746#endif
3747
3748typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3749 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3750 U16 ControlFlags; /*0x08 */
3751 U16 Reserved; /*0x0A */
3752 U16 AdditionalControlFlags; /*0x0C */
3753 U16 NVMeMaxQueueDepth; /*0x0E */
3754 U8 NumPhys; /*0x10 */
3755 U8 DMDReportPCIe; /*0x11 */
3756 U16 Reserved2; /*0x12 */
3757 MPI26_PCIE_IO_UNIT1_PHY_DATA
3758 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */
3759} MPI26_CONFIG_PAGE_PIOUNIT_1,
3760 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3761 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t;
3762
3763#define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00)
3764
3765/*values for PCIe IO Unit Page 1 PhyFlags */
3766#define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
3767#define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01)
3768
3769/*values for PCIe IO Unit Page 1 MaxMinLinkRate */
3770#define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0)
3771#define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4)
3772#define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20)
3773#define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30)
3774#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40)
3775#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50)
3776
3777/*values for PCIe IO Unit Page 1 DMDReportPCIe */
3778#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80)
3779#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00)
3780#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80)
3781#define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F)
3782
3783/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3784 *values
3785 */
3786
3787
3788/****************************************************************************
3789* PCIe Switch Config Pages (MPI v2.6 and later)
3790****************************************************************************/
3791
3792/*PCIe Switch Page 0 */
3793
3794typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 {
3795 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3796 U8 PhysicalPort; /*0x08 */
3797 U8 Reserved1; /*0x09 */
3798 U16 Reserved2; /*0x0A */
3799 U16 DevHandle; /*0x0C */
3800 U16 ParentDevHandle; /*0x0E */
3801 U8 NumPorts; /*0x10 */
3802 U8 PCIeLevel; /*0x11 */
3803 U16 Reserved3; /*0x12 */
3804 U32 Reserved4; /*0x14 */
3805 U32 Reserved5; /*0x18 */
3806 U32 Reserved6; /*0x1C */
3807} MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3808 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t;
3809
3810#define MPI26_PCIESWITCH0_PAGEVERSION (0x00)
3811
3812
3813/*PCIe Switch Page 1 */
3814
3815typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3816 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3817 U8 PhysicalPort; /*0x08 */
3818 U8 Reserved1; /*0x09 */
3819 U16 Reserved2; /*0x0A */
3820 U8 NumPorts; /*0x0C */
3821 U8 PortNum; /*0x0D */
3822 U16 AttachedDevHandle; /*0x0E */
3823 U16 SwitchDevHandle; /*0x10 */
3824 U8 NegotiatedPortWidth; /*0x12 */
3825 U8 NegotiatedLinkRate; /*0x13 */
3826 U32 Reserved4; /*0x14 */
3827 U32 Reserved5; /*0x18 */
3828} MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3829 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t;
3830
3831#define MPI26_PCIESWITCH1_PAGEVERSION (0x00)
3832
3833/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3834
3835/* defines for the Flags field */
3836#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002)
3837#define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001)
3838
3839/****************************************************************************
3840* PCIe Device Config Pages (MPI v2.6 and later)
3841****************************************************************************/
3842
3843/*PCIe Device Page 0 */
3844
3845typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3846 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3847 U16 Slot; /*0x08 */
3848 U16 EnclosureHandle; /*0x0A */
3849 U64 WWID; /*0x0C */
3850 U16 ParentDevHandle; /*0x14 */
3851 U8 PortNum; /*0x16 */
3852 U8 AccessStatus; /*0x17 */
3853 U16 DevHandle; /*0x18 */
3854 U8 PhysicalPort; /*0x1A */
3855 U8 Reserved1; /*0x1B */
3856 U32 DeviceInfo; /*0x1C */
3857 U32 Flags; /*0x20 */
3858 U8 SupportedLinkRates; /*0x24 */
3859 U8 MaxPortWidth; /*0x25 */
3860 U8 NegotiatedPortWidth; /*0x26 */
3861 U8 NegotiatedLinkRate; /*0x27 */
3862 U8 EnclosureLevel; /*0x28 */
3863 U8 Reserved2; /*0x29 */
3864 U16 Reserved3; /*0x2A */
3865 U8 ConnectorName[4]; /*0x2C */
3866 U32 Reserved4; /*0x30 */
3867 U32 Reserved5; /*0x34 */
3868} MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3869 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t;
3870
3871#define MPI26_PCIEDEVICE0_PAGEVERSION (0x01)
3872
3873/*values for PCIe Device Page 0 AccessStatus field */
3874#define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00)
3875#define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04)
3876#define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02)
3877#define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07)
3878#define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08)
3879#define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09)
3880#define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A)
3881#define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10)
3882
3883#define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30)
3884#define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31)
3885#define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32)
3886#define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33)
3887#define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34)
3888#define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35)
3889#define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3890#define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37)
3891#define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38)
3892
3893#define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F)
3894
3895/*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo
3896 *field
3897 */
3898
3899/*values for PCIe Device Page 0 Flags field*/
3900#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000)
3901#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000)
3902#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000)
3903#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000)
3904#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000)
3905#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400)
3906#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200)
3907#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100)
3908#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080)
3909#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040)
3910#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020)
3911#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010)
3912#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002)
3913#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001)
3914
3915/* values for PCIe Device Page 0 SupportedLinkRates field */
3916#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08)
3917#define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04)
3918#define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02)
3919#define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01)
3920
3921/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3922
3923
3924/*PCIe Device Page 2 */
3925
3926typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
3927 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3928 U16 DevHandle; /*0x08 */
3929 U8 ControllerResetTO; /* 0x0A */
3930 U8 Reserved1; /* 0x0B */
3931 U32 MaximumDataTransferSize; /*0x0C */
3932 U32 Capabilities; /*0x10 */
3933 U16 NOIOB; /* 0x14 */
3934 U16 Reserved2; /* 0x16 */
3935} MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3936 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
3937
3938#define MPI26_PCIEDEVICE2_PAGEVERSION (0x01)
3939
3940/*defines for PCIe Device Page 2 Capabilities field */
3941#define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008)
3942#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004)
3943#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002)
3944#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001)
3945
3946/* Defines for the NOIOB field */
3947#define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000)
3948
3949/****************************************************************************
3950* PCIe Link Config Pages (MPI v2.6 and later)
3951****************************************************************************/
3952
3953/*PCIe Link Page 1 */
3954
3955typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 {
3956 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3957 U8 Link; /*0x08 */
3958 U8 Reserved1; /*0x09 */
3959 U16 Reserved2; /*0x0A */
3960 U32 CorrectableErrorCount; /*0x0C */
3961 U16 NonFatalErrorCount; /*0x10 */
3962 U16 Reserved3; /*0x12 */
3963 U16 FatalErrorCount; /*0x14 */
3964 U16 Reserved4; /*0x16 */
3965} MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3966 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t;
3967
3968#define MPI26_PCIELINK1_PAGEVERSION (0x00)
3969
3970/*PCIe Link Page 2 */
3971
3972typedef struct _MPI26_PCIELINK2_LINK_EVENT {
3973 U8 LinkEventCode; /*0x00 */
3974 U8 Reserved1; /*0x01 */
3975 U16 Reserved2; /*0x02 */
3976 U32 LinkEventInfo; /*0x04 */
3977} MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT,
3978 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t;
3979
3980/*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3981
3982
3983/*
3984 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3985 *one and check the value returned for NumLinkEvents at runtime.
3986 */
3987#ifndef MPI26_PCIELINK2_LINK_EVENT_MAX
3988#define MPI26_PCIELINK2_LINK_EVENT_MAX (1)
3989#endif
3990
3991typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 {
3992 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3993 U8 Link; /*0x08 */
3994 U8 Reserved1; /*0x09 */
3995 U16 Reserved2; /*0x0A */
3996 U8 NumLinkEvents; /*0x0C */
3997 U8 Reserved3; /*0x0D */
3998 U16 Reserved4; /*0x0E */
3999 MPI26_PCIELINK2_LINK_EVENT
4000 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /*0x10 */
4001} MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
4002 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t;
4003
4004#define MPI26_PCIELINK2_PAGEVERSION (0x00)
4005
4006/*PCIe Link Page 3 */
4007
4008typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG {
4009 U8 LinkEventCode; /*0x00 */
4010 U8 Reserved1; /*0x01 */
4011 U16 Reserved2; /*0x02 */
4012 U8 CounterType; /*0x04 */
4013 U8 ThresholdWindow; /*0x05 */
4014 U8 TimeUnits; /*0x06 */
4015 U8 Reserved3; /*0x07 */
4016 U32 EventThreshold; /*0x08 */
4017 U16 ThresholdFlags; /*0x0C */
4018 U16 Reserved4; /*0x0E */
4019} MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
4020 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t;
4021
4022/*values for LinkEventCode field */
4023#define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00)
4024#define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01)
4025#define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02)
4026#define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03)
4027#define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04)
4028#define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05)
4029#define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06)
4030#define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07)
4031#define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08)
4032#define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09)
4033#define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A)
4034#define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B)
4035#define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C)
4036#define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D)
4037#define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E)
4038#define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F)
4039#define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10)
4040#define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11)
4041#define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12)
4042
4043/*values for the CounterType field */
4044#define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00)
4045#define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01)
4046#define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02)
4047
4048/*values for the TimeUnits field */
4049#define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00)
4050#define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01)
4051#define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02)
4052#define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03)
4053
4054/*values for the ThresholdFlags field */
4055#define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001)
4056
4057/*
4058 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
4059 *one and check the value returned for NumLinkEvents at runtime.
4060 */
4061#ifndef MPI26_PCIELINK3_LINK_EVENT_MAX
4062#define MPI26_PCIELINK3_LINK_EVENT_MAX (1)
4063#endif
4064
4065typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 {
4066 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
4067 U8 Link; /*0x08 */
4068 U8 Reserved1; /*0x09 */
4069 U16 Reserved2; /*0x0A */
4070 U8 NumLinkEvents; /*0x0C */
4071 U8 Reserved3; /*0x0D */
4072 U16 Reserved4; /*0x0E */
4073 MPI26_PCIELINK3_LINK_EVENT_CONFIG
4074 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */
4075} MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
4076 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t;
4077
4078#define MPI26_PCIELINK3_PAGEVERSION (0x00)
4079
4080
4081#endif