blob: cba30618e8fed571e39867460c6158d281664c12 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46/**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
50static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
51{
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
54 pm8001_mr32(address, 0x00);
55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
56 pm8001_mr32(address, 0x04);
57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
58 pm8001_mr32(address, 0x08);
59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
60 pm8001_mr32(address, 0x0C);
61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
62 pm8001_mr32(address, 0x10);
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
64 pm8001_mr32(address, 0x14);
65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
66 pm8001_mr32(address, 0x18);
67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
68 pm8001_mr32(address, MAIN_IBQ_OFFSET);
69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
70 pm8001_mr32(address, MAIN_OBQ_OFFSET);
71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
73
74 /* read analog Setting offset from the configuration table */
75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
77
78 /* read Error Dump Offset and Length */
79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
87}
88
89/**
90 * read_general_status_table - read the general status table and save it.
91 * @pm8001_ha: our hba card information
92 */
93static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
94{
95 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
97 pm8001_mr32(address, 0x00);
98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
99 pm8001_mr32(address, 0x04);
100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
101 pm8001_mr32(address, 0x08);
102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
103 pm8001_mr32(address, 0x0C);
104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
105 pm8001_mr32(address, 0x10);
106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
107 pm8001_mr32(address, 0x14);
108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
109 pm8001_mr32(address, 0x18);
110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
111 pm8001_mr32(address, 0x1C);
112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
113 pm8001_mr32(address, 0x20);
114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
115 pm8001_mr32(address, 0x24);
116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
117 pm8001_mr32(address, 0x28);
118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
119 pm8001_mr32(address, 0x2C);
120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
121 pm8001_mr32(address, 0x30);
122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
123 pm8001_mr32(address, 0x34);
124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
125 pm8001_mr32(address, 0x38);
126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
127 pm8001_mr32(address, 0x3C);
128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
129 pm8001_mr32(address, 0x40);
130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
131 pm8001_mr32(address, 0x44);
132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
133 pm8001_mr32(address, 0x48);
134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
135 pm8001_mr32(address, 0x4C);
136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
137 pm8001_mr32(address, 0x50);
138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
139 pm8001_mr32(address, 0x54);
140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
141 pm8001_mr32(address, 0x58);
142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
143 pm8001_mr32(address, 0x5C);
144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
145 pm8001_mr32(address, 0x60);
146}
147
148/**
149 * read_inbnd_queue_table - read the inbound queue table and save it.
150 * @pm8001_ha: our hba card information
151 */
152static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
153{
154 int i;
155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
157 u32 offset = i * 0x20;
158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
160 pm8001_ha->inbnd_q_tbl[i].pi_offset =
161 pm8001_mr32(address, (offset + 0x18));
162 }
163}
164
165/**
166 * read_outbnd_queue_table - read the outbound queue table and save it.
167 * @pm8001_ha: our hba card information
168 */
169static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
170{
171 int i;
172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
174 u32 offset = i * 0x24;
175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
177 pm8001_ha->outbnd_q_tbl[i].ci_offset =
178 pm8001_mr32(address, (offset + 0x18));
179 }
180}
181
182/**
183 * init_default_table_values - init the default table.
184 * @pm8001_ha: our hba card information
185 */
186static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
187{
188 int i;
189 u32 offsetib, offsetob;
190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
192
193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
199 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
201 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
206
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
212 PM8001_EVENT_LOG_SIZE;
213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
219 PM8001_EVENT_LOG_SIZE;
220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
224 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
229 pm8001_ha->inbnd_q_tbl[i].base_virt =
230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
231 pm8001_ha->inbnd_q_tbl[i].total_length =
232 pm8001_ha->memoryMap.region[IB + i].total_len;
233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
237 pm8001_ha->inbnd_q_tbl[i].ci_virt =
238 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
239 offsetib = i * 0x20;
240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
241 get_pci_bar_index(pm8001_mr32(addressib,
242 (offsetib + 0x14)));
243 pm8001_ha->inbnd_q_tbl[i].pi_offset =
244 pm8001_mr32(addressib, (offsetib + 0x18));
245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
247 }
248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
250 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
255 pm8001_ha->outbnd_q_tbl[i].base_virt =
256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
257 pm8001_ha->outbnd_q_tbl[i].total_length =
258 pm8001_ha->memoryMap.region[OB + i].total_len;
259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
264 0 | (10 << 16) | (i << 24);
265 pm8001_ha->outbnd_q_tbl[i].pi_virt =
266 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
267 offsetob = i * 0x24;
268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
269 get_pci_bar_index(pm8001_mr32(addressob,
270 offsetob + 0x14));
271 pm8001_ha->outbnd_q_tbl[i].ci_offset =
272 pm8001_mr32(addressob, (offsetob + 0x18));
273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
275 }
276}
277
278/**
279 * update_main_config_table - update the main default table to the HBA.
280 * @pm8001_ha: our hba card information
281 */
282static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
283{
284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
285 pm8001_mw32(address, 0x24,
286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
287 pm8001_mw32(address, 0x28,
288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
289 pm8001_mw32(address, 0x2C,
290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
291 pm8001_mw32(address, 0x30,
292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
293 pm8001_mw32(address, 0x34,
294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
295 pm8001_mw32(address, 0x38,
296 pm8001_ha->main_cfg_tbl.pm8001_tbl.
297 outbound_tgt_ITNexus_event_pid0_3);
298 pm8001_mw32(address, 0x3C,
299 pm8001_ha->main_cfg_tbl.pm8001_tbl.
300 outbound_tgt_ITNexus_event_pid4_7);
301 pm8001_mw32(address, 0x40,
302 pm8001_ha->main_cfg_tbl.pm8001_tbl.
303 outbound_tgt_ssp_event_pid0_3);
304 pm8001_mw32(address, 0x44,
305 pm8001_ha->main_cfg_tbl.pm8001_tbl.
306 outbound_tgt_ssp_event_pid4_7);
307 pm8001_mw32(address, 0x48,
308 pm8001_ha->main_cfg_tbl.pm8001_tbl.
309 outbound_tgt_smp_event_pid0_3);
310 pm8001_mw32(address, 0x4C,
311 pm8001_ha->main_cfg_tbl.pm8001_tbl.
312 outbound_tgt_smp_event_pid4_7);
313 pm8001_mw32(address, 0x50,
314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
315 pm8001_mw32(address, 0x54,
316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
317 pm8001_mw32(address, 0x58,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
319 pm8001_mw32(address, 0x5C,
320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
321 pm8001_mw32(address, 0x60,
322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
323 pm8001_mw32(address, 0x64,
324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
325 pm8001_mw32(address, 0x68,
326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
327 pm8001_mw32(address, 0x6C,
328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
329 pm8001_mw32(address, 0x70,
330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
331}
332
333/**
334 * update_inbnd_queue_table - update the inbound queue table to the HBA.
335 * @pm8001_ha: our hba card information
336 */
337static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
338 int number)
339{
340 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
341 u16 offset = number * 0x20;
342 pm8001_mw32(address, offset + 0x00,
343 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
344 pm8001_mw32(address, offset + 0x04,
345 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
346 pm8001_mw32(address, offset + 0x08,
347 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
348 pm8001_mw32(address, offset + 0x0C,
349 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
350 pm8001_mw32(address, offset + 0x10,
351 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
352}
353
354/**
355 * update_outbnd_queue_table - update the outbound queue table to the HBA.
356 * @pm8001_ha: our hba card information
357 */
358static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
359 int number)
360{
361 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
362 u16 offset = number * 0x24;
363 pm8001_mw32(address, offset + 0x00,
364 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
365 pm8001_mw32(address, offset + 0x04,
366 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
367 pm8001_mw32(address, offset + 0x08,
368 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
369 pm8001_mw32(address, offset + 0x0C,
370 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
371 pm8001_mw32(address, offset + 0x10,
372 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
373 pm8001_mw32(address, offset + 0x1C,
374 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
375}
376
377/**
378 * pm8001_bar4_shift - function is called to shift BAR base address
379 * @pm8001_ha : our hba card infomation
380 * @shiftValue : shifting value in memory bar.
381 */
382int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
383{
384 u32 regVal;
385 unsigned long start;
386
387 /* program the inbound AXI translation Lower Address */
388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
389
390 /* confirm the setting is written */
391 start = jiffies + HZ; /* 1 sec */
392 do {
393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
394 } while ((regVal != shiftValue) && time_before(jiffies, start));
395
396 if (regVal != shiftValue) {
397 PM8001_INIT_DBG(pm8001_ha,
398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
399 " = 0x%x\n", regVal));
400 return -1;
401 }
402 return 0;
403}
404
405/**
406 * mpi_set_phys_g3_with_ssc
407 * @pm8001_ha: our hba card information
408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
409 */
410static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
411 u32 SSCbit)
412{
413 u32 value, offset, i;
414 unsigned long flags;
415
416#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
417#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
418#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
419#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
420#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
421#define PHY_G3_WITH_SSC_BIT_SHIFT 13
422#define SNW3_PHY_CAPABILITIES_PARITY 31
423
424 /*
425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
427 */
428 spin_lock_irqsave(&pm8001_ha->lock, flags);
429 if (-1 == pm8001_bar4_shift(pm8001_ha,
430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
431 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
432 return;
433 }
434
435 for (i = 0; i < 4; i++) {
436 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
438 }
439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
440 if (-1 == pm8001_bar4_shift(pm8001_ha,
441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
442 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
443 return;
444 }
445 for (i = 4; i < 8; i++) {
446 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
448 }
449 /*************************************************************
450 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
451 Device MABC SMOD0 Controls
452 Address: (via MEMBASE-III):
453 Using shifted destination address 0x0_0000: with Offset 0xD8
454
455 31:28 R/W Reserved Do not change
456 27:24 R/W SAS_SMOD_SPRDUP 0000
457 23:20 R/W SAS_SMOD_SPRDDN 0000
458 19:0 R/W Reserved Do not change
459 Upon power-up this register will read as 0x8990c016,
460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
461 so that the written value will be 0x8090c016.
462 This will ensure only down-spreading SSC is enabled on the SPC.
463 *************************************************************/
464 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
466
467 /*set the shifted destination address to 0x0 to avoid error operation */
468 pm8001_bar4_shift(pm8001_ha, 0x0);
469 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
470 return;
471}
472
473/**
474 * mpi_set_open_retry_interval_reg
475 * @pm8001_ha: our hba card information
476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
477 */
478static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
479 u32 interval)
480{
481 u32 offset;
482 u32 value;
483 u32 i;
484 unsigned long flags;
485
486#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
487#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
488#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
489#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
490#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
491
492 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
493 spin_lock_irqsave(&pm8001_ha->lock, flags);
494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
495 if (-1 == pm8001_bar4_shift(pm8001_ha,
496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
497 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
498 return;
499 }
500 for (i = 0; i < 4; i++) {
501 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
502 pm8001_cw32(pm8001_ha, 2, offset, value);
503 }
504
505 if (-1 == pm8001_bar4_shift(pm8001_ha,
506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
507 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
508 return;
509 }
510 for (i = 4; i < 8; i++) {
511 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
512 pm8001_cw32(pm8001_ha, 2, offset, value);
513 }
514 /*set the shifted destination address to 0x0 to avoid error operation */
515 pm8001_bar4_shift(pm8001_ha, 0x0);
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
517 return;
518}
519
520/**
521 * mpi_init_check - check firmware initialization status.
522 * @pm8001_ha: our hba card information
523 */
524static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
525{
526 u32 max_wait_count;
527 u32 value;
528 u32 gst_len_mpistate;
529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
530 table is updated */
531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
532 /* wait until Inbound DoorBell Clear Register toggled */
533 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
534 do {
535 udelay(1);
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
537 value &= SPC_MSGU_CFG_TABLE_UPDATE;
538 } while ((value != 0) && (--max_wait_count));
539
540 if (!max_wait_count)
541 return -1;
542 /* check the MPI-State for initialization */
543 gst_len_mpistate =
544 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
545 GST_GSTLEN_MPIS_OFFSET);
546 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
547 return -1;
548 /* check MPI Initialization error */
549 gst_len_mpistate = gst_len_mpistate >> 16;
550 if (0x0000 != gst_len_mpistate)
551 return -1;
552 return 0;
553}
554
555/**
556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
557 * @pm8001_ha: our hba card information
558 */
559static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
560{
561 u32 value, value1;
562 u32 max_wait_count;
563 /* check error state */
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
566 /* check AAP error */
567 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
568 /* error state */
569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
570 return -1;
571 }
572
573 /* check IOP error */
574 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
575 /* error state */
576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
577 return -1;
578 }
579
580 /* bit 4-31 of scratch pad1 should be zeros if it is not
581 in error state*/
582 if (value & SCRATCH_PAD1_STATE_MASK) {
583 /* error case */
584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
585 return -1;
586 }
587
588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
589 in error state */
590 if (value1 & SCRATCH_PAD2_STATE_MASK) {
591 /* error case */
592 return -1;
593 }
594
595 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
596
597 /* wait until scratch pad 1 and 2 registers in ready state */
598 do {
599 udelay(1);
600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
601 & SCRATCH_PAD1_RDY;
602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
603 & SCRATCH_PAD2_RDY;
604 if ((--max_wait_count) == 0)
605 return -1;
606 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
607 return 0;
608}
609
610static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
611{
612 void __iomem *base_addr;
613 u32 value;
614 u32 offset;
615 u32 pcibar;
616 u32 pcilogic;
617
618 value = pm8001_cr32(pm8001_ha, 0, 0x44);
619 offset = value & 0x03FFFFFF;
620 PM8001_INIT_DBG(pm8001_ha,
621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
622 pcilogic = (value & 0xFC000000) >> 26;
623 pcibar = get_pci_bar_index(pcilogic);
624 PM8001_INIT_DBG(pm8001_ha,
625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
626 pm8001_ha->main_cfg_tbl_addr = base_addr =
627 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
628 pm8001_ha->general_stat_tbl_addr =
629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
630 pm8001_ha->inbnd_q_tbl_addr =
631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
632 pm8001_ha->outbnd_q_tbl_addr =
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
634}
635
636/**
637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
638 * @pm8001_ha: our hba card information
639 */
640static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
641{
642 u8 i = 0;
643 u16 deviceid;
644 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
645 /* 8081 controllers need BAR shift to access MPI space
646 * as this is shared with BIOS data */
647 if (deviceid == 0x8081 || deviceid == 0x0042) {
648 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
649 PM8001_FAIL_DBG(pm8001_ha,
650 pm8001_printk("Shift Bar4 to 0x%x failed\n",
651 GSM_SM_BASE));
652 return -1;
653 }
654 }
655 /* check the firmware status */
656 if (-1 == check_fw_ready(pm8001_ha)) {
657 PM8001_FAIL_DBG(pm8001_ha,
658 pm8001_printk("Firmware is not ready!\n"));
659 return -EBUSY;
660 }
661
662 /* Initialize pci space address eg: mpi offset */
663 init_pci_device_addresses(pm8001_ha);
664 init_default_table_values(pm8001_ha);
665 read_main_config_table(pm8001_ha);
666 read_general_status_table(pm8001_ha);
667 read_inbnd_queue_table(pm8001_ha);
668 read_outbnd_queue_table(pm8001_ha);
669 /* update main config table ,inbound table and outbound table */
670 update_main_config_table(pm8001_ha);
671 for (i = 0; i < PM8001_MAX_INB_NUM; i++)
672 update_inbnd_queue_table(pm8001_ha, i);
673 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
674 update_outbnd_queue_table(pm8001_ha, i);
675 /* 8081 controller donot require these operations */
676 if (deviceid != 0x8081 && deviceid != 0x0042) {
677 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
678 /* 7->130ms, 34->500ms, 119->1.5s */
679 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
680 }
681 /* notify firmware update finished and check initialization status */
682 if (0 == mpi_init_check(pm8001_ha)) {
683 PM8001_INIT_DBG(pm8001_ha,
684 pm8001_printk("MPI initialize successful!\n"));
685 } else
686 return -EBUSY;
687 /*This register is a 16-bit timer with a resolution of 1us. This is the
688 timer used for interrupt delay/coalescing in the PCIe Application Layer.
689 Zero is not a valid value. A value of 1 in the register will cause the
690 interrupts to be normal. A value greater than 1 will cause coalescing
691 delays.*/
692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
694 return 0;
695}
696
697static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
698{
699 u32 max_wait_count;
700 u32 value;
701 u32 gst_len_mpistate;
702 u16 deviceid;
703 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
704 if (deviceid == 0x8081 || deviceid == 0x0042) {
705 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
706 PM8001_FAIL_DBG(pm8001_ha,
707 pm8001_printk("Shift Bar4 to 0x%x failed\n",
708 GSM_SM_BASE));
709 return -1;
710 }
711 }
712 init_pci_device_addresses(pm8001_ha);
713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
714 table is stop */
715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
716
717 /* wait until Inbound DoorBell Clear Register toggled */
718 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
719 do {
720 udelay(1);
721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
722 value &= SPC_MSGU_CFG_TABLE_RESET;
723 } while ((value != 0) && (--max_wait_count));
724
725 if (!max_wait_count) {
726 PM8001_FAIL_DBG(pm8001_ha,
727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
728 return -1;
729 }
730
731 /* check the MPI-State for termination in progress */
732 /* wait until Inbound DoorBell Clear Register toggled */
733 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
734 do {
735 udelay(1);
736 gst_len_mpistate =
737 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
738 GST_GSTLEN_MPIS_OFFSET);
739 if (GST_MPI_STATE_UNINIT ==
740 (gst_len_mpistate & GST_MPI_STATE_MASK))
741 break;
742 } while (--max_wait_count);
743 if (!max_wait_count) {
744 PM8001_FAIL_DBG(pm8001_ha,
745 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
746 gst_len_mpistate & GST_MPI_STATE_MASK));
747 return -1;
748 }
749 return 0;
750}
751
752/**
753 * soft_reset_ready_check - Function to check FW is ready for soft reset.
754 * @pm8001_ha: our hba card information
755 */
756static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
757{
758 u32 regVal, regVal1, regVal2;
759 if (mpi_uninit_check(pm8001_ha) != 0) {
760 PM8001_FAIL_DBG(pm8001_ha,
761 pm8001_printk("MPI state is not ready\n"));
762 return -1;
763 }
764 /* read the scratch pad 2 register bit 2 */
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
766 & SCRATCH_PAD2_FWRDY_RST;
767 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
768 PM8001_INIT_DBG(pm8001_ha,
769 pm8001_printk("Firmware is ready for reset .\n"));
770 } else {
771 unsigned long flags;
772 /* Trigger NMI twice via RB6 */
773 spin_lock_irqsave(&pm8001_ha->lock, flags);
774 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
775 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
776 PM8001_FAIL_DBG(pm8001_ha,
777 pm8001_printk("Shift Bar4 to 0x%x failed\n",
778 RB6_ACCESS_REG));
779 return -1;
780 }
781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
782 RB6_MAGIC_NUMBER_RST);
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
784 /* wait for 100 ms */
785 mdelay(100);
786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
787 SCRATCH_PAD2_FWRDY_RST;
788 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
791 PM8001_FAIL_DBG(pm8001_ha,
792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
794 regVal1, regVal2));
795 PM8001_FAIL_DBG(pm8001_ha,
796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
798 PM8001_FAIL_DBG(pm8001_ha,
799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
801 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
802 return -1;
803 }
804 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
805 }
806 return 0;
807}
808
809/**
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
813 */
814static int
815pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
816{
817 u32 regVal, toggleVal;
818 u32 max_wait_count;
819 u32 regVal1, regVal2, regVal3;
820 u32 signature = 0x252acbcd; /* for host scratch pad0 */
821 unsigned long flags;
822
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha) != 0) {
825 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
826 return -1;
827 }
828
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
830 value to clear */
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
832 spin_lock_irqsave(&pm8001_ha->lock, flags);
833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
835 PM8001_FAIL_DBG(pm8001_ha,
836 pm8001_printk("Shift Bar4 to 0x%x failed\n",
837 MBIC_AAP1_ADDR_BASE));
838 return -1;
839 }
840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
841 PM8001_INIT_DBG(pm8001_ha,
842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
844 /* map 0x70000 to BAR4(0x20), BAR2(win) */
845 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
846 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
847 PM8001_FAIL_DBG(pm8001_ha,
848 pm8001_printk("Shift Bar4 to 0x%x failed\n",
849 MBIC_IOP_ADDR_BASE));
850 return -1;
851 }
852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
856
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
858 PM8001_INIT_DBG(pm8001_ha,
859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
861
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
863 PM8001_INIT_DBG(pm8001_ha,
864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
866
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
871
872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
873 PM8001_INIT_DBG(pm8001_ha,
874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
876
877 /* read the scratch pad 1 register bit 2 */
878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
879 & SCRATCH_PAD1_RST;
880 toggleVal = regVal ^ SCRATCH_PAD1_RST;
881
882 /* set signature in host scratch pad0 register to tell SPC that the
883 host performs the soft reset */
884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
885
886 /* read required registers for confirmming */
887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
888 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
889 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
890 PM8001_FAIL_DBG(pm8001_ha,
891 pm8001_printk("Shift Bar4 to 0x%x failed\n",
892 GSM_ADDR_BASE));
893 return -1;
894 }
895 PM8001_INIT_DBG(pm8001_ha,
896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
897 " Reset = 0x%x\n",
898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
899
900 /* step 3: host read GSM Configuration and Reset register */
901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
902 /* Put those bits to low */
903 /* GSM XCBI offset = 0x70 0000
904 0x00 Bit 13 COM_SLV_SW_RSTB 1
905 0x00 Bit 12 QSSP_SW_RSTB 1
906 0x00 Bit 11 RAAE_SW_RSTB 1
907 0x00 Bit 9 RB_1_SW_RSTB 1
908 0x00 Bit 8 SM_SW_RSTB 1
909 */
910 regVal &= ~(0x00003b00);
911 /* host write GSM Configuration and Reset register */
912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
913 PM8001_INIT_DBG(pm8001_ha,
914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
915 "Configuration and Reset is set to = 0x%x\n",
916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
917
918 /* step 4: */
919 /* disable GSM - Read Address Parity Check */
920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
921 PM8001_INIT_DBG(pm8001_ha,
922 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
923 "Enable = 0x%x\n", regVal1));
924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
925 PM8001_INIT_DBG(pm8001_ha,
926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
927 "is set to = 0x%x\n",
928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
929
930 /* disable GSM - Write Address Parity Check */
931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
932 PM8001_INIT_DBG(pm8001_ha,
933 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
934 " Enable = 0x%x\n", regVal2));
935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
936 PM8001_INIT_DBG(pm8001_ha,
937 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
938 "Enable is set to = 0x%x\n",
939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
940
941 /* disable GSM - Write Data Parity Check */
942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
943 PM8001_INIT_DBG(pm8001_ha,
944 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
945 " Enable = 0x%x\n", regVal3));
946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
947 PM8001_INIT_DBG(pm8001_ha,
948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
949 "is set to = 0x%x\n",
950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
951
952 /* step 5: delay 10 usec */
953 udelay(10);
954 /* step 5-b: set GPIO-0 output control to tristate anyway */
955 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
956 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("Shift Bar4 to 0x%x failed\n",
959 GPIO_ADDR_BASE));
960 return -1;
961 }
962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
963 PM8001_INIT_DBG(pm8001_ha,
964 pm8001_printk("GPIO Output Control Register:"
965 " = 0x%x\n", regVal));
966 /* set GPIO-0 output control to tri-state */
967 regVal &= 0xFFFFFFFC;
968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
969
970 /* Step 6: Reset the IOP and AAP1 */
971 /* map 0x00000 to BAR4(0x20), BAR2(win) */
972 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
973 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
974 PM8001_FAIL_DBG(pm8001_ha,
975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
976 SPC_TOP_LEVEL_ADDR_BASE));
977 return -1;
978 }
979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
980 PM8001_INIT_DBG(pm8001_ha,
981 pm8001_printk("Top Register before resetting IOP/AAP1"
982 ":= 0x%x\n", regVal));
983 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
985
986 /* step 7: Reset the BDMA/OSSP */
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
988 PM8001_INIT_DBG(pm8001_ha,
989 pm8001_printk("Top Register before resetting BDMA/OSSP"
990 ": = 0x%x\n", regVal));
991 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
993
994 /* step 8: delay 10 usec */
995 udelay(10);
996
997 /* step 9: bring the BDMA and OSSP out of reset */
998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
999 PM8001_INIT_DBG(pm8001_ha,
1000 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001 ":= 0x%x\n", regVal));
1002 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005 /* step 10: delay 10 usec */
1006 udelay(10);
1007
1008 /* step 11: reads and sets the GSM Configuration and Reset Register */
1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012 PM8001_FAIL_DBG(pm8001_ha,
1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014 GSM_ADDR_BASE));
1015 return -1;
1016 }
1017 PM8001_INIT_DBG(pm8001_ha,
1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021 /* Put those bits to high */
1022 /* GSM XCBI offset = 0x70 0000
1023 0x00 Bit 13 COM_SLV_SW_RSTB 1
1024 0x00 Bit 12 QSSP_SW_RSTB 1
1025 0x00 Bit 11 RAAE_SW_RSTB 1
1026 0x00 Bit 9 RB_1_SW_RSTB 1
1027 0x00 Bit 8 SM_SW_RSTB 1
1028 */
1029 regVal |= (GSM_CONFIG_RESET_VALUE);
1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033 " Configuration and Reset is set to = 0x%x\n",
1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036 /* step 12: Restore GSM - Read Address Parity Check */
1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038 /* just for debugging */
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041 " = 0x%x\n", regVal));
1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043 PM8001_INIT_DBG(pm8001_ha,
1044 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045 " Check Enable is set to = 0x%x\n",
1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047 /* Restore GSM - Write Address Parity Check */
1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050 PM8001_INIT_DBG(pm8001_ha,
1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052 " Enable is set to = 0x%x\n",
1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054 /* Restore GSM - Write Data Parity Check */
1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059 "is set to = 0x%x\n",
1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062 /* step 13: bring the IOP and AAP1 out of reset */
1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066 PM8001_FAIL_DBG(pm8001_ha,
1067 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068 SPC_TOP_LEVEL_ADDR_BASE));
1069 return -1;
1070 }
1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075 /* step 14: delay 10 usec - Normal Mode */
1076 udelay(10);
1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079 /* step 15 (Normal Mode): wait until scratch pad1 register
1080 bit 2 toggled */
1081 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082 do {
1083 udelay(1);
1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085 SCRATCH_PAD1_RST;
1086 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088 if (!max_wait_count) {
1089 regVal = pm8001_cr32(pm8001_ha, 0,
1090 MSGU_SCRATCH_PAD_1);
1091 PM8001_FAIL_DBG(pm8001_ha,
1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094 toggleVal, regVal));
1095 PM8001_FAIL_DBG(pm8001_ha,
1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097 pm8001_cr32(pm8001_ha, 0,
1098 MSGU_SCRATCH_PAD_0)));
1099 PM8001_FAIL_DBG(pm8001_ha,
1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101 pm8001_cr32(pm8001_ha, 0,
1102 MSGU_SCRATCH_PAD_2)));
1103 PM8001_FAIL_DBG(pm8001_ha,
1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105 pm8001_cr32(pm8001_ha, 0,
1106 MSGU_SCRATCH_PAD_3)));
1107 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108 return -1;
1109 }
1110
1111 /* step 16 (Normal) - Clear ODMR and ODCR */
1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116 ready - 1 sec timeout */
1117 /* Wait for the SPC Configuration Table to be ready */
1118 if (check_fw_ready(pm8001_ha) == -1) {
1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120 /* return error if MPI Configuration Table not ready */
1121 PM8001_INIT_DBG(pm8001_ha,
1122 pm8001_printk("FW not ready SCRATCH_PAD1"
1123 " = 0x%x\n", regVal));
1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125 /* return error if MPI Configuration Table not ready */
1126 PM8001_INIT_DBG(pm8001_ha,
1127 pm8001_printk("FW not ready SCRATCH_PAD2"
1128 " = 0x%x\n", regVal));
1129 PM8001_INIT_DBG(pm8001_ha,
1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131 pm8001_cr32(pm8001_ha, 0,
1132 MSGU_SCRATCH_PAD_0)));
1133 PM8001_INIT_DBG(pm8001_ha,
1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135 pm8001_cr32(pm8001_ha, 0,
1136 MSGU_SCRATCH_PAD_3)));
1137 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138 return -1;
1139 }
1140 }
1141 pm8001_bar4_shift(pm8001_ha, 0);
1142 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144 PM8001_INIT_DBG(pm8001_ha,
1145 pm8001_printk("SPC soft reset Complete\n"));
1146 return 0;
1147}
1148
1149static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150{
1151 u32 i;
1152 u32 regVal;
1153 PM8001_INIT_DBG(pm8001_ha,
1154 pm8001_printk("chip reset start\n"));
1155
1156 /* do SPC chip reset. */
1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158 regVal &= ~(SPC_REG_RESET_DEVICE);
1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161 /* delay 10 usec */
1162 udelay(10);
1163
1164 /* bring chip reset out of reset */
1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166 regVal |= SPC_REG_RESET_DEVICE;
1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169 /* delay 10 usec */
1170 udelay(10);
1171
1172 /* wait for 20 msec until the firmware gets reloaded */
1173 i = 20;
1174 do {
1175 mdelay(1);
1176 } while ((--i) != 0);
1177
1178 PM8001_INIT_DBG(pm8001_ha,
1179 pm8001_printk("chip reset finished\n"));
1180}
1181
1182/**
1183 * pm8001_chip_iounmap - which maped when initialized.
1184 * @pm8001_ha: our hba card information
1185 */
1186void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187{
1188 s8 bar, logical = 0;
1189 for (bar = 0; bar < 6; bar++) {
1190 /*
1191 ** logical BARs for SPC:
1192 ** bar 0 and 1 - logical BAR0
1193 ** bar 2 and 3 - logical BAR1
1194 ** bar4 - logical BAR2
1195 ** bar5 - logical BAR3
1196 ** Skip the appropriate assignments:
1197 */
1198 if ((bar == 1) || (bar == 3))
1199 continue;
1200 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202 logical++;
1203 }
1204 }
1205}
1206
1207#ifndef PM8001_USE_MSIX
1208/**
1209 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1210 * @pm8001_ha: our hba card information
1211 */
1212static void
1213pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1214{
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1216 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1217}
1218
1219 /**
1220 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1221 * @pm8001_ha: our hba card information
1222 */
1223static void
1224pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1225{
1226 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1227}
1228
1229#else
1230
1231/**
1232 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1233 * @pm8001_ha: our hba card information
1234 */
1235static void
1236pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1237 u32 int_vec_idx)
1238{
1239 u32 msi_index;
1240 u32 value;
1241 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1242 msi_index += MSIX_TABLE_BASE;
1243 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1244 value = (1 << int_vec_idx);
1245 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1246
1247}
1248
1249/**
1250 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1251 * @pm8001_ha: our hba card information
1252 */
1253static void
1254pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1255 u32 int_vec_idx)
1256{
1257 u32 msi_index;
1258 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1259 msi_index += MSIX_TABLE_BASE;
1260 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1261}
1262#endif
1263
1264/**
1265 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1266 * @pm8001_ha: our hba card information
1267 */
1268static void
1269pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1270{
1271#ifdef PM8001_USE_MSIX
1272 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1273#else
1274 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1275#endif
1276}
1277
1278/**
1279 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1280 * @pm8001_ha: our hba card information
1281 */
1282static void
1283pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1284{
1285#ifdef PM8001_USE_MSIX
1286 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1287#else
1288 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1289#endif
1290}
1291
1292/**
1293 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1294 * inbound queue.
1295 * @circularQ: the inbound queue we want to transfer to HBA.
1296 * @messageSize: the message size of this transfer, normally it is 64 bytes
1297 * @messagePtr: the pointer to message.
1298 */
1299int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1300 u16 messageSize, void **messagePtr)
1301{
1302 u32 offset, consumer_index;
1303 struct mpi_msg_hdr *msgHeader;
1304 u8 bcCount = 1; /* only support single buffer */
1305
1306 /* Checks is the requested message size can be allocated in this queue*/
1307 if (messageSize > IOMB_SIZE_SPCV) {
1308 *messagePtr = NULL;
1309 return -1;
1310 }
1311
1312 /* Stores the new consumer index */
1313 consumer_index = pm8001_read_32(circularQ->ci_virt);
1314 circularQ->consumer_index = cpu_to_le32(consumer_index);
1315 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1316 le32_to_cpu(circularQ->consumer_index)) {
1317 *messagePtr = NULL;
1318 return -1;
1319 }
1320 /* get memory IOMB buffer address */
1321 offset = circularQ->producer_idx * messageSize;
1322 /* increment to next bcCount element */
1323 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1324 % PM8001_MPI_QUEUE;
1325 /* Adds that distance to the base of the region virtual address plus
1326 the message header size*/
1327 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1328 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1329 return 0;
1330}
1331
1332/**
1333 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1334 * FW to tell the fw to get this message from IOMB.
1335 * @pm8001_ha: our hba card information
1336 * @circularQ: the inbound queue we want to transfer to HBA.
1337 * @opCode: the operation code represents commands which LLDD and fw recognized.
1338 * @payload: the command payload of each operation command.
1339 */
1340int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1341 struct inbound_queue_table *circularQ,
1342 u32 opCode, void *payload, u32 responseQueue)
1343{
1344 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1345 void *pMessage;
1346
1347 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1348 &pMessage) < 0) {
1349 PM8001_IO_DBG(pm8001_ha,
1350 pm8001_printk("No free mpi buffer\n"));
1351 return -ENOMEM;
1352 }
1353 BUG_ON(!payload);
1354 /*Copy to the payload*/
1355 memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1356 sizeof(struct mpi_msg_hdr)));
1357
1358 /*Build the header*/
1359 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1360 | ((responseQueue & 0x3F) << 16)
1361 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1362
1363 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1364 /*Update the PI to the firmware*/
1365 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1366 circularQ->pi_offset, circularQ->producer_idx);
1367 PM8001_IO_DBG(pm8001_ha,
1368 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1369 responseQueue, opCode, circularQ->producer_idx,
1370 circularQ->consumer_index));
1371 return 0;
1372}
1373
1374u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1375 struct outbound_queue_table *circularQ, u8 bc)
1376{
1377 u32 producer_index;
1378 struct mpi_msg_hdr *msgHeader;
1379 struct mpi_msg_hdr *pOutBoundMsgHeader;
1380
1381 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1382 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1383 circularQ->consumer_idx * pm8001_ha->iomb_size);
1384 if (pOutBoundMsgHeader != msgHeader) {
1385 PM8001_FAIL_DBG(pm8001_ha,
1386 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1387 circularQ->consumer_idx, msgHeader));
1388
1389 /* Update the producer index from SPC */
1390 producer_index = pm8001_read_32(circularQ->pi_virt);
1391 circularQ->producer_index = cpu_to_le32(producer_index);
1392 PM8001_FAIL_DBG(pm8001_ha,
1393 pm8001_printk("consumer_idx = %d producer_index = %d"
1394 "msgHeader = %p\n", circularQ->consumer_idx,
1395 circularQ->producer_index, msgHeader));
1396 return 0;
1397 }
1398 /* free the circular queue buffer elements associated with the message*/
1399 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1400 % PM8001_MPI_QUEUE;
1401 /* update the CI of outbound queue */
1402 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1403 circularQ->consumer_idx);
1404 /* Update the producer index from SPC*/
1405 producer_index = pm8001_read_32(circularQ->pi_virt);
1406 circularQ->producer_index = cpu_to_le32(producer_index);
1407 PM8001_IO_DBG(pm8001_ha,
1408 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1409 circularQ->producer_index));
1410 return 0;
1411}
1412
1413/**
1414 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1415 * message table.
1416 * @pm8001_ha: our hba card information
1417 * @circularQ: the outbound queue table.
1418 * @messagePtr1: the message contents of this outbound message.
1419 * @pBC: the message size.
1420 */
1421u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1422 struct outbound_queue_table *circularQ,
1423 void **messagePtr1, u8 *pBC)
1424{
1425 struct mpi_msg_hdr *msgHeader;
1426 __le32 msgHeader_tmp;
1427 u32 header_tmp;
1428 do {
1429 /* If there are not-yet-delivered messages ... */
1430 if (le32_to_cpu(circularQ->producer_index)
1431 != circularQ->consumer_idx) {
1432 /*Get the pointer to the circular queue buffer element*/
1433 msgHeader = (struct mpi_msg_hdr *)
1434 (circularQ->base_virt +
1435 circularQ->consumer_idx * pm8001_ha->iomb_size);
1436 /* read header */
1437 header_tmp = pm8001_read_32(msgHeader);
1438 msgHeader_tmp = cpu_to_le32(header_tmp);
1439 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1440 if (OPC_OUB_SKIP_ENTRY !=
1441 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1442 *messagePtr1 =
1443 ((u8 *)msgHeader) +
1444 sizeof(struct mpi_msg_hdr);
1445 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1446 >> 24) & 0x1f);
1447 PM8001_IO_DBG(pm8001_ha,
1448 pm8001_printk(": CI=%d PI=%d "
1449 "msgHeader=%x\n",
1450 circularQ->consumer_idx,
1451 circularQ->producer_index,
1452 msgHeader_tmp));
1453 return MPI_IO_STATUS_SUCCESS;
1454 } else {
1455 circularQ->consumer_idx =
1456 (circularQ->consumer_idx +
1457 ((le32_to_cpu(msgHeader_tmp)
1458 >> 24) & 0x1f))
1459 % PM8001_MPI_QUEUE;
1460 msgHeader_tmp = 0;
1461 pm8001_write_32(msgHeader, 0, 0);
1462 /* update the CI of outbound queue */
1463 pm8001_cw32(pm8001_ha,
1464 circularQ->ci_pci_bar,
1465 circularQ->ci_offset,
1466 circularQ->consumer_idx);
1467 }
1468 } else {
1469 circularQ->consumer_idx =
1470 (circularQ->consumer_idx +
1471 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1472 0x1f)) % PM8001_MPI_QUEUE;
1473 msgHeader_tmp = 0;
1474 pm8001_write_32(msgHeader, 0, 0);
1475 /* update the CI of outbound queue */
1476 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1477 circularQ->ci_offset,
1478 circularQ->consumer_idx);
1479 return MPI_IO_STATUS_FAIL;
1480 }
1481 } else {
1482 u32 producer_index;
1483 void *pi_virt = circularQ->pi_virt;
1484 /* spurious interrupt during setup if
1485 * kexec-ing and driver doing a doorbell access
1486 * with the pre-kexec oq interrupt setup
1487 */
1488 if (!pi_virt)
1489 break;
1490 /* Update the producer index from SPC */
1491 producer_index = pm8001_read_32(pi_virt);
1492 circularQ->producer_index = cpu_to_le32(producer_index);
1493 }
1494 } while (le32_to_cpu(circularQ->producer_index) !=
1495 circularQ->consumer_idx);
1496 /* while we don't have any more not-yet-delivered message */
1497 /* report empty */
1498 return MPI_IO_STATUS_BUSY;
1499}
1500
1501void pm8001_work_fn(struct work_struct *work)
1502{
1503 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1504 struct pm8001_device *pm8001_dev;
1505 struct domain_device *dev;
1506
1507 /*
1508 * So far, all users of this stash an associated structure here.
1509 * If we get here, and this pointer is null, then the action
1510 * was cancelled. This nullification happens when the device
1511 * goes away.
1512 */
1513 pm8001_dev = pw->data; /* Most stash device structure */
1514 if ((pm8001_dev == NULL)
1515 || ((pw->handler != IO_XFER_ERROR_BREAK)
1516 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1517 kfree(pw);
1518 return;
1519 }
1520
1521 switch (pw->handler) {
1522 case IO_XFER_ERROR_BREAK:
1523 { /* This one stashes the sas_task instead */
1524 struct sas_task *t = (struct sas_task *)pm8001_dev;
1525 u32 tag;
1526 struct pm8001_ccb_info *ccb;
1527 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1528 unsigned long flags, flags1;
1529 struct task_status_struct *ts;
1530 int i;
1531
1532 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1533 break; /* Task still on lu */
1534 spin_lock_irqsave(&pm8001_ha->lock, flags);
1535
1536 spin_lock_irqsave(&t->task_state_lock, flags1);
1537 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1538 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1539 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1540 break; /* Task got completed by another */
1541 }
1542 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1543
1544 /* Search for a possible ccb that matches the task */
1545 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1546 ccb = &pm8001_ha->ccb_info[i];
1547 tag = ccb->ccb_tag;
1548 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1549 break;
1550 }
1551 if (!ccb) {
1552 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1553 break; /* Task got freed by another */
1554 }
1555 ts = &t->task_status;
1556 ts->resp = SAS_TASK_COMPLETE;
1557 /* Force the midlayer to retry */
1558 ts->stat = SAS_QUEUE_FULL;
1559 pm8001_dev = ccb->device;
1560 if (pm8001_dev)
1561 pm8001_dev->running_req--;
1562 spin_lock_irqsave(&t->task_state_lock, flags1);
1563 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1564 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1565 t->task_state_flags |= SAS_TASK_STATE_DONE;
1566 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1567 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1569 " done with event 0x%x resp 0x%x stat 0x%x but"
1570 " aborted by upper layer!\n",
1571 t, pw->handler, ts->resp, ts->stat));
1572 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1573 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1574 } else {
1575 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1576 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1577 mb();/* in order to force CPU ordering */
1578 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1579 t->task_done(t);
1580 }
1581 } break;
1582 case IO_XFER_OPEN_RETRY_TIMEOUT:
1583 { /* This one stashes the sas_task instead */
1584 struct sas_task *t = (struct sas_task *)pm8001_dev;
1585 u32 tag;
1586 struct pm8001_ccb_info *ccb;
1587 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1588 unsigned long flags, flags1;
1589 int i, ret = 0;
1590
1591 PM8001_IO_DBG(pm8001_ha,
1592 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1593
1594 ret = pm8001_query_task(t);
1595
1596 PM8001_IO_DBG(pm8001_ha,
1597 switch (ret) {
1598 case TMF_RESP_FUNC_SUCC:
1599 pm8001_printk("...Task on lu\n");
1600 break;
1601
1602 case TMF_RESP_FUNC_COMPLETE:
1603 pm8001_printk("...Task NOT on lu\n");
1604 break;
1605
1606 default:
1607 pm8001_printk("...query task failed!!!\n");
1608 break;
1609 });
1610
1611 spin_lock_irqsave(&pm8001_ha->lock, flags);
1612
1613 spin_lock_irqsave(&t->task_state_lock, flags1);
1614
1615 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1616 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1617 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1618 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1619 (void)pm8001_abort_task(t);
1620 break; /* Task got completed by another */
1621 }
1622
1623 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1624
1625 /* Search for a possible ccb that matches the task */
1626 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1627 ccb = &pm8001_ha->ccb_info[i];
1628 tag = ccb->ccb_tag;
1629 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1630 break;
1631 }
1632 if (!ccb) {
1633 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1634 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1635 (void)pm8001_abort_task(t);
1636 break; /* Task got freed by another */
1637 }
1638
1639 pm8001_dev = ccb->device;
1640 dev = pm8001_dev->sas_device;
1641
1642 switch (ret) {
1643 case TMF_RESP_FUNC_SUCC: /* task on lu */
1644 ccb->open_retry = 1; /* Snub completion */
1645 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1646 ret = pm8001_abort_task(t);
1647 ccb->open_retry = 0;
1648 switch (ret) {
1649 case TMF_RESP_FUNC_SUCC:
1650 case TMF_RESP_FUNC_COMPLETE:
1651 break;
1652 default: /* device misbehavior */
1653 ret = TMF_RESP_FUNC_FAILED;
1654 PM8001_IO_DBG(pm8001_ha,
1655 pm8001_printk("...Reset phy\n"));
1656 pm8001_I_T_nexus_reset(dev);
1657 break;
1658 }
1659 break;
1660
1661 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1662 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1663 /* Do we need to abort the task locally? */
1664 break;
1665
1666 default: /* device misbehavior */
1667 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1668 ret = TMF_RESP_FUNC_FAILED;
1669 PM8001_IO_DBG(pm8001_ha,
1670 pm8001_printk("...Reset phy\n"));
1671 pm8001_I_T_nexus_reset(dev);
1672 }
1673
1674 if (ret == TMF_RESP_FUNC_FAILED)
1675 t = NULL;
1676 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1677 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1678 } break;
1679 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1680 dev = pm8001_dev->sas_device;
1681 pm8001_I_T_nexus_event_handler(dev);
1682 break;
1683 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1684 dev = pm8001_dev->sas_device;
1685 pm8001_I_T_nexus_reset(dev);
1686 break;
1687 case IO_DS_IN_ERROR:
1688 dev = pm8001_dev->sas_device;
1689 pm8001_I_T_nexus_reset(dev);
1690 break;
1691 case IO_DS_NON_OPERATIONAL:
1692 dev = pm8001_dev->sas_device;
1693 pm8001_I_T_nexus_reset(dev);
1694 break;
1695 }
1696 kfree(pw);
1697}
1698
1699int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1700 int handler)
1701{
1702 struct pm8001_work *pw;
1703 int ret = 0;
1704
1705 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1706 if (pw) {
1707 pw->pm8001_ha = pm8001_ha;
1708 pw->data = data;
1709 pw->handler = handler;
1710 INIT_WORK(&pw->work, pm8001_work_fn);
1711 queue_work(pm8001_wq, &pw->work);
1712 } else
1713 ret = -ENOMEM;
1714
1715 return ret;
1716}
1717
1718static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1719 struct pm8001_device *pm8001_ha_dev)
1720{
1721 int res;
1722 u32 ccb_tag;
1723 struct pm8001_ccb_info *ccb;
1724 struct sas_task *task = NULL;
1725 struct task_abort_req task_abort;
1726 struct inbound_queue_table *circularQ;
1727 u32 opc = OPC_INB_SATA_ABORT;
1728 int ret;
1729
1730 if (!pm8001_ha_dev) {
1731 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1732 return;
1733 }
1734
1735 task = sas_alloc_slow_task(GFP_ATOMIC);
1736
1737 if (!task) {
1738 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1739 "allocate task\n"));
1740 return;
1741 }
1742
1743 task->task_done = pm8001_task_done;
1744
1745 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1746 if (res)
1747 return;
1748
1749 ccb = &pm8001_ha->ccb_info[ccb_tag];
1750 ccb->device = pm8001_ha_dev;
1751 ccb->ccb_tag = ccb_tag;
1752 ccb->task = task;
1753 ccb->n_elem = 0;
1754
1755 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1756
1757 memset(&task_abort, 0, sizeof(task_abort));
1758 task_abort.abort_all = cpu_to_le32(1);
1759 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1760 task_abort.tag = cpu_to_le32(ccb_tag);
1761
1762 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1763 if (ret)
1764 pm8001_tag_free(pm8001_ha, ccb_tag);
1765
1766}
1767
1768static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1769 struct pm8001_device *pm8001_ha_dev)
1770{
1771 struct sata_start_req sata_cmd;
1772 int res;
1773 u32 ccb_tag;
1774 struct pm8001_ccb_info *ccb;
1775 struct sas_task *task = NULL;
1776 struct host_to_dev_fis fis;
1777 struct domain_device *dev;
1778 struct inbound_queue_table *circularQ;
1779 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1780
1781 task = sas_alloc_slow_task(GFP_ATOMIC);
1782
1783 if (!task) {
1784 PM8001_FAIL_DBG(pm8001_ha,
1785 pm8001_printk("cannot allocate task !!!\n"));
1786 return;
1787 }
1788 task->task_done = pm8001_task_done;
1789
1790 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1791 if (res) {
1792 sas_free_task(task);
1793 PM8001_FAIL_DBG(pm8001_ha,
1794 pm8001_printk("cannot allocate tag !!!\n"));
1795 return;
1796 }
1797
1798 /* allocate domain device by ourselves as libsas
1799 * is not going to provide any
1800 */
1801 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1802 if (!dev) {
1803 sas_free_task(task);
1804 pm8001_tag_free(pm8001_ha, ccb_tag);
1805 PM8001_FAIL_DBG(pm8001_ha,
1806 pm8001_printk("Domain device cannot be allocated\n"));
1807 return;
1808 }
1809 task->dev = dev;
1810 task->dev->lldd_dev = pm8001_ha_dev;
1811
1812 ccb = &pm8001_ha->ccb_info[ccb_tag];
1813 ccb->device = pm8001_ha_dev;
1814 ccb->ccb_tag = ccb_tag;
1815 ccb->task = task;
1816 ccb->n_elem = 0;
1817 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1818 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1819
1820 memset(&sata_cmd, 0, sizeof(sata_cmd));
1821 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1822
1823 /* construct read log FIS */
1824 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1825 fis.fis_type = 0x27;
1826 fis.flags = 0x80;
1827 fis.command = ATA_CMD_READ_LOG_EXT;
1828 fis.lbal = 0x10;
1829 fis.sector_count = 0x1;
1830
1831 sata_cmd.tag = cpu_to_le32(ccb_tag);
1832 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1833 sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1834 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1835
1836 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1837 if (res) {
1838 sas_free_task(task);
1839 pm8001_tag_free(pm8001_ha, ccb_tag);
1840 kfree(dev);
1841 }
1842}
1843
1844/**
1845 * mpi_ssp_completion- process the event that FW response to the SSP request.
1846 * @pm8001_ha: our hba card information
1847 * @piomb: the message contents of this outbound message.
1848 *
1849 * When FW has completed a ssp request for example a IO request, after it has
1850 * filled the SG data with the data, it will trigger this event represent
1851 * that he has finished the job,please check the coresponding buffer.
1852 * So we will tell the caller who maybe waiting the result to tell upper layer
1853 * that the task has been finished.
1854 */
1855static void
1856mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1857{
1858 struct sas_task *t;
1859 struct pm8001_ccb_info *ccb;
1860 unsigned long flags;
1861 u32 status;
1862 u32 param;
1863 u32 tag;
1864 struct ssp_completion_resp *psspPayload;
1865 struct task_status_struct *ts;
1866 struct ssp_response_iu *iu;
1867 struct pm8001_device *pm8001_dev;
1868 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1869 status = le32_to_cpu(psspPayload->status);
1870 tag = le32_to_cpu(psspPayload->tag);
1871 ccb = &pm8001_ha->ccb_info[tag];
1872 if ((status == IO_ABORTED) && ccb->open_retry) {
1873 /* Being completed by another */
1874 ccb->open_retry = 0;
1875 return;
1876 }
1877 pm8001_dev = ccb->device;
1878 param = le32_to_cpu(psspPayload->param);
1879
1880 t = ccb->task;
1881
1882 if (status && status != IO_UNDERFLOW)
1883 PM8001_FAIL_DBG(pm8001_ha,
1884 pm8001_printk("sas IO status 0x%x\n", status));
1885 if (unlikely(!t || !t->lldd_task || !t->dev))
1886 return;
1887 ts = &t->task_status;
1888 /* Print sas address of IO failed device */
1889 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1890 (status != IO_UNDERFLOW))
1891 PM8001_FAIL_DBG(pm8001_ha,
1892 pm8001_printk("SAS Address of IO Failure Drive:"
1893 "%016llx", SAS_ADDR(t->dev->sas_addr)));
1894
1895 switch (status) {
1896 case IO_SUCCESS:
1897 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1898 ",param = %d\n", param));
1899 if (param == 0) {
1900 ts->resp = SAS_TASK_COMPLETE;
1901 ts->stat = SAM_STAT_GOOD;
1902 } else {
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAS_PROTO_RESPONSE;
1905 ts->residual = param;
1906 iu = &psspPayload->ssp_resp_iu;
1907 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1908 }
1909 if (pm8001_dev)
1910 pm8001_dev->running_req--;
1911 break;
1912 case IO_ABORTED:
1913 PM8001_IO_DBG(pm8001_ha,
1914 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1915 ts->resp = SAS_TASK_COMPLETE;
1916 ts->stat = SAS_ABORTED_TASK;
1917 break;
1918 case IO_UNDERFLOW:
1919 /* SSP Completion with error */
1920 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1921 ",param = %d\n", param));
1922 ts->resp = SAS_TASK_COMPLETE;
1923 ts->stat = SAS_DATA_UNDERRUN;
1924 ts->residual = param;
1925 if (pm8001_dev)
1926 pm8001_dev->running_req--;
1927 break;
1928 case IO_NO_DEVICE:
1929 PM8001_IO_DBG(pm8001_ha,
1930 pm8001_printk("IO_NO_DEVICE\n"));
1931 ts->resp = SAS_TASK_UNDELIVERED;
1932 ts->stat = SAS_PHY_DOWN;
1933 break;
1934 case IO_XFER_ERROR_BREAK:
1935 PM8001_IO_DBG(pm8001_ha,
1936 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1937 ts->resp = SAS_TASK_COMPLETE;
1938 ts->stat = SAS_OPEN_REJECT;
1939 /* Force the midlayer to retry */
1940 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1941 break;
1942 case IO_XFER_ERROR_PHY_NOT_READY:
1943 PM8001_IO_DBG(pm8001_ha,
1944 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1945 ts->resp = SAS_TASK_COMPLETE;
1946 ts->stat = SAS_OPEN_REJECT;
1947 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1948 break;
1949 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1950 PM8001_IO_DBG(pm8001_ha,
1951 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1952 ts->resp = SAS_TASK_COMPLETE;
1953 ts->stat = SAS_OPEN_REJECT;
1954 ts->open_rej_reason = SAS_OREJ_EPROTO;
1955 break;
1956 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1957 PM8001_IO_DBG(pm8001_ha,
1958 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1959 ts->resp = SAS_TASK_COMPLETE;
1960 ts->stat = SAS_OPEN_REJECT;
1961 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1962 break;
1963 case IO_OPEN_CNX_ERROR_BREAK:
1964 PM8001_IO_DBG(pm8001_ha,
1965 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1966 ts->resp = SAS_TASK_COMPLETE;
1967 ts->stat = SAS_OPEN_REJECT;
1968 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1969 break;
1970 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1971 PM8001_IO_DBG(pm8001_ha,
1972 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1973 ts->resp = SAS_TASK_COMPLETE;
1974 ts->stat = SAS_OPEN_REJECT;
1975 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1976 if (!t->uldd_task)
1977 pm8001_handle_event(pm8001_ha,
1978 pm8001_dev,
1979 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1980 break;
1981 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1982 PM8001_IO_DBG(pm8001_ha,
1983 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1984 ts->resp = SAS_TASK_COMPLETE;
1985 ts->stat = SAS_OPEN_REJECT;
1986 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1987 break;
1988 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1989 PM8001_IO_DBG(pm8001_ha,
1990 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1991 "NOT_SUPPORTED\n"));
1992 ts->resp = SAS_TASK_COMPLETE;
1993 ts->stat = SAS_OPEN_REJECT;
1994 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1995 break;
1996 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1997 PM8001_IO_DBG(pm8001_ha,
1998 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1999 ts->resp = SAS_TASK_UNDELIVERED;
2000 ts->stat = SAS_OPEN_REJECT;
2001 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2002 break;
2003 case IO_XFER_ERROR_NAK_RECEIVED:
2004 PM8001_IO_DBG(pm8001_ha,
2005 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2006 ts->resp = SAS_TASK_COMPLETE;
2007 ts->stat = SAS_OPEN_REJECT;
2008 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2009 break;
2010 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2011 PM8001_IO_DBG(pm8001_ha,
2012 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2013 ts->resp = SAS_TASK_COMPLETE;
2014 ts->stat = SAS_NAK_R_ERR;
2015 break;
2016 case IO_XFER_ERROR_DMA:
2017 PM8001_IO_DBG(pm8001_ha,
2018 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2019 ts->resp = SAS_TASK_COMPLETE;
2020 ts->stat = SAS_OPEN_REJECT;
2021 break;
2022 case IO_XFER_OPEN_RETRY_TIMEOUT:
2023 PM8001_IO_DBG(pm8001_ha,
2024 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2025 ts->resp = SAS_TASK_COMPLETE;
2026 ts->stat = SAS_OPEN_REJECT;
2027 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2028 break;
2029 case IO_XFER_ERROR_OFFSET_MISMATCH:
2030 PM8001_IO_DBG(pm8001_ha,
2031 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2032 ts->resp = SAS_TASK_COMPLETE;
2033 ts->stat = SAS_OPEN_REJECT;
2034 break;
2035 case IO_PORT_IN_RESET:
2036 PM8001_IO_DBG(pm8001_ha,
2037 pm8001_printk("IO_PORT_IN_RESET\n"));
2038 ts->resp = SAS_TASK_COMPLETE;
2039 ts->stat = SAS_OPEN_REJECT;
2040 break;
2041 case IO_DS_NON_OPERATIONAL:
2042 PM8001_IO_DBG(pm8001_ha,
2043 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2044 ts->resp = SAS_TASK_COMPLETE;
2045 ts->stat = SAS_OPEN_REJECT;
2046 if (!t->uldd_task)
2047 pm8001_handle_event(pm8001_ha,
2048 pm8001_dev,
2049 IO_DS_NON_OPERATIONAL);
2050 break;
2051 case IO_DS_IN_RECOVERY:
2052 PM8001_IO_DBG(pm8001_ha,
2053 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2054 ts->resp = SAS_TASK_COMPLETE;
2055 ts->stat = SAS_OPEN_REJECT;
2056 break;
2057 case IO_TM_TAG_NOT_FOUND:
2058 PM8001_IO_DBG(pm8001_ha,
2059 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2060 ts->resp = SAS_TASK_COMPLETE;
2061 ts->stat = SAS_OPEN_REJECT;
2062 break;
2063 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2064 PM8001_IO_DBG(pm8001_ha,
2065 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2066 ts->resp = SAS_TASK_COMPLETE;
2067 ts->stat = SAS_OPEN_REJECT;
2068 break;
2069 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2070 PM8001_IO_DBG(pm8001_ha,
2071 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2072 ts->resp = SAS_TASK_COMPLETE;
2073 ts->stat = SAS_OPEN_REJECT;
2074 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2075 break;
2076 default:
2077 PM8001_IO_DBG(pm8001_ha,
2078 pm8001_printk("Unknown status 0x%x\n", status));
2079 /* not allowed case. Therefore, return failed status */
2080 ts->resp = SAS_TASK_COMPLETE;
2081 ts->stat = SAS_OPEN_REJECT;
2082 break;
2083 }
2084 PM8001_IO_DBG(pm8001_ha,
2085 pm8001_printk("scsi_status = %x\n ",
2086 psspPayload->ssp_resp_iu.status));
2087 spin_lock_irqsave(&t->task_state_lock, flags);
2088 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2089 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2090 t->task_state_flags |= SAS_TASK_STATE_DONE;
2091 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2092 spin_unlock_irqrestore(&t->task_state_lock, flags);
2093 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2094 " io_status 0x%x resp 0x%x "
2095 "stat 0x%x but aborted by upper layer!\n",
2096 t, status, ts->resp, ts->stat));
2097 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2098 } else {
2099 spin_unlock_irqrestore(&t->task_state_lock, flags);
2100 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2101 mb();/* in order to force CPU ordering */
2102 t->task_done(t);
2103 }
2104}
2105
2106/*See the comments for mpi_ssp_completion */
2107static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2108{
2109 struct sas_task *t;
2110 unsigned long flags;
2111 struct task_status_struct *ts;
2112 struct pm8001_ccb_info *ccb;
2113 struct pm8001_device *pm8001_dev;
2114 struct ssp_event_resp *psspPayload =
2115 (struct ssp_event_resp *)(piomb + 4);
2116 u32 event = le32_to_cpu(psspPayload->event);
2117 u32 tag = le32_to_cpu(psspPayload->tag);
2118 u32 port_id = le32_to_cpu(psspPayload->port_id);
2119 u32 dev_id = le32_to_cpu(psspPayload->device_id);
2120
2121 ccb = &pm8001_ha->ccb_info[tag];
2122 t = ccb->task;
2123 pm8001_dev = ccb->device;
2124 if (event)
2125 PM8001_FAIL_DBG(pm8001_ha,
2126 pm8001_printk("sas IO status 0x%x\n", event));
2127 if (unlikely(!t || !t->lldd_task || !t->dev))
2128 return;
2129 ts = &t->task_status;
2130 PM8001_IO_DBG(pm8001_ha,
2131 pm8001_printk("port_id = %x,device_id = %x\n",
2132 port_id, dev_id));
2133 switch (event) {
2134 case IO_OVERFLOW:
2135 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2136 ts->resp = SAS_TASK_COMPLETE;
2137 ts->stat = SAS_DATA_OVERRUN;
2138 ts->residual = 0;
2139 if (pm8001_dev)
2140 pm8001_dev->running_req--;
2141 break;
2142 case IO_XFER_ERROR_BREAK:
2143 PM8001_IO_DBG(pm8001_ha,
2144 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2145 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2146 return;
2147 case IO_XFER_ERROR_PHY_NOT_READY:
2148 PM8001_IO_DBG(pm8001_ha,
2149 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2150 ts->resp = SAS_TASK_COMPLETE;
2151 ts->stat = SAS_OPEN_REJECT;
2152 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2153 break;
2154 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2155 PM8001_IO_DBG(pm8001_ha,
2156 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2157 "_SUPPORTED\n"));
2158 ts->resp = SAS_TASK_COMPLETE;
2159 ts->stat = SAS_OPEN_REJECT;
2160 ts->open_rej_reason = SAS_OREJ_EPROTO;
2161 break;
2162 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2163 PM8001_IO_DBG(pm8001_ha,
2164 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2165 ts->resp = SAS_TASK_COMPLETE;
2166 ts->stat = SAS_OPEN_REJECT;
2167 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2168 break;
2169 case IO_OPEN_CNX_ERROR_BREAK:
2170 PM8001_IO_DBG(pm8001_ha,
2171 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2172 ts->resp = SAS_TASK_COMPLETE;
2173 ts->stat = SAS_OPEN_REJECT;
2174 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2175 break;
2176 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2177 PM8001_IO_DBG(pm8001_ha,
2178 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2179 ts->resp = SAS_TASK_COMPLETE;
2180 ts->stat = SAS_OPEN_REJECT;
2181 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2182 if (!t->uldd_task)
2183 pm8001_handle_event(pm8001_ha,
2184 pm8001_dev,
2185 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2186 break;
2187 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2188 PM8001_IO_DBG(pm8001_ha,
2189 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2190 ts->resp = SAS_TASK_COMPLETE;
2191 ts->stat = SAS_OPEN_REJECT;
2192 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2193 break;
2194 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2195 PM8001_IO_DBG(pm8001_ha,
2196 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2197 "NOT_SUPPORTED\n"));
2198 ts->resp = SAS_TASK_COMPLETE;
2199 ts->stat = SAS_OPEN_REJECT;
2200 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2201 break;
2202 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2203 PM8001_IO_DBG(pm8001_ha,
2204 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2205 ts->resp = SAS_TASK_COMPLETE;
2206 ts->stat = SAS_OPEN_REJECT;
2207 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2208 break;
2209 case IO_XFER_ERROR_NAK_RECEIVED:
2210 PM8001_IO_DBG(pm8001_ha,
2211 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_OPEN_REJECT;
2214 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2215 break;
2216 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2217 PM8001_IO_DBG(pm8001_ha,
2218 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2219 ts->resp = SAS_TASK_COMPLETE;
2220 ts->stat = SAS_NAK_R_ERR;
2221 break;
2222 case IO_XFER_OPEN_RETRY_TIMEOUT:
2223 PM8001_IO_DBG(pm8001_ha,
2224 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2225 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2226 return;
2227 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2228 PM8001_IO_DBG(pm8001_ha,
2229 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2230 ts->resp = SAS_TASK_COMPLETE;
2231 ts->stat = SAS_DATA_OVERRUN;
2232 break;
2233 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2234 PM8001_IO_DBG(pm8001_ha,
2235 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2236 ts->resp = SAS_TASK_COMPLETE;
2237 ts->stat = SAS_DATA_OVERRUN;
2238 break;
2239 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2240 PM8001_IO_DBG(pm8001_ha,
2241 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2242 ts->resp = SAS_TASK_COMPLETE;
2243 ts->stat = SAS_DATA_OVERRUN;
2244 break;
2245 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2246 PM8001_IO_DBG(pm8001_ha,
2247 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2248 ts->resp = SAS_TASK_COMPLETE;
2249 ts->stat = SAS_DATA_OVERRUN;
2250 break;
2251 case IO_XFER_ERROR_OFFSET_MISMATCH:
2252 PM8001_IO_DBG(pm8001_ha,
2253 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2254 ts->resp = SAS_TASK_COMPLETE;
2255 ts->stat = SAS_DATA_OVERRUN;
2256 break;
2257 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2260 ts->resp = SAS_TASK_COMPLETE;
2261 ts->stat = SAS_DATA_OVERRUN;
2262 break;
2263 case IO_XFER_CMD_FRAME_ISSUED:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
2266 return;
2267 default:
2268 PM8001_IO_DBG(pm8001_ha,
2269 pm8001_printk("Unknown status 0x%x\n", event));
2270 /* not allowed case. Therefore, return failed status */
2271 ts->resp = SAS_TASK_COMPLETE;
2272 ts->stat = SAS_DATA_OVERRUN;
2273 break;
2274 }
2275 spin_lock_irqsave(&t->task_state_lock, flags);
2276 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2277 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2278 t->task_state_flags |= SAS_TASK_STATE_DONE;
2279 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2280 spin_unlock_irqrestore(&t->task_state_lock, flags);
2281 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2282 " event 0x%x resp 0x%x "
2283 "stat 0x%x but aborted by upper layer!\n",
2284 t, event, ts->resp, ts->stat));
2285 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2286 } else {
2287 spin_unlock_irqrestore(&t->task_state_lock, flags);
2288 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2289 mb();/* in order to force CPU ordering */
2290 t->task_done(t);
2291 }
2292}
2293
2294/*See the comments for mpi_ssp_completion */
2295static void
2296mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2297{
2298 struct sas_task *t;
2299 struct pm8001_ccb_info *ccb;
2300 u32 param;
2301 u32 status;
2302 u32 tag;
2303 int i, j;
2304 u8 sata_addr_low[4];
2305 u32 temp_sata_addr_low;
2306 u8 sata_addr_hi[4];
2307 u32 temp_sata_addr_hi;
2308 struct sata_completion_resp *psataPayload;
2309 struct task_status_struct *ts;
2310 struct ata_task_resp *resp ;
2311 u32 *sata_resp;
2312 struct pm8001_device *pm8001_dev;
2313 unsigned long flags;
2314
2315 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2316 status = le32_to_cpu(psataPayload->status);
2317 tag = le32_to_cpu(psataPayload->tag);
2318
2319 if (!tag) {
2320 PM8001_FAIL_DBG(pm8001_ha,
2321 pm8001_printk("tag null\n"));
2322 return;
2323 }
2324 ccb = &pm8001_ha->ccb_info[tag];
2325 param = le32_to_cpu(psataPayload->param);
2326 if (ccb) {
2327 t = ccb->task;
2328 pm8001_dev = ccb->device;
2329 } else {
2330 PM8001_FAIL_DBG(pm8001_ha,
2331 pm8001_printk("ccb null\n"));
2332 return;
2333 }
2334
2335 if (t) {
2336 if (t->dev && (t->dev->lldd_dev))
2337 pm8001_dev = t->dev->lldd_dev;
2338 } else {
2339 PM8001_FAIL_DBG(pm8001_ha,
2340 pm8001_printk("task null\n"));
2341 return;
2342 }
2343
2344 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2345 && unlikely(!t || !t->lldd_task || !t->dev)) {
2346 PM8001_FAIL_DBG(pm8001_ha,
2347 pm8001_printk("task or dev null\n"));
2348 return;
2349 }
2350
2351 ts = &t->task_status;
2352 if (!ts) {
2353 PM8001_FAIL_DBG(pm8001_ha,
2354 pm8001_printk("ts null\n"));
2355 return;
2356 }
2357 /* Print sas address of IO failed device */
2358 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2359 (status != IO_UNDERFLOW)) {
2360 if (!((t->dev->parent) &&
2361 (dev_is_expander(t->dev->parent->dev_type)))) {
2362 for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2363 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2364 for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2365 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2366 memcpy(&temp_sata_addr_low, sata_addr_low,
2367 sizeof(sata_addr_low));
2368 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2369 sizeof(sata_addr_hi));
2370 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2371 |((temp_sata_addr_hi << 8) &
2372 0xff0000) |
2373 ((temp_sata_addr_hi >> 8)
2374 & 0xff00) |
2375 ((temp_sata_addr_hi << 24) &
2376 0xff000000));
2377 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2378 & 0xff) |
2379 ((temp_sata_addr_low << 8)
2380 & 0xff0000) |
2381 ((temp_sata_addr_low >> 8)
2382 & 0xff00) |
2383 ((temp_sata_addr_low << 24)
2384 & 0xff000000)) +
2385 pm8001_dev->attached_phy +
2386 0x10);
2387 PM8001_FAIL_DBG(pm8001_ha,
2388 pm8001_printk("SAS Address of IO Failure Drive:"
2389 "%08x%08x", temp_sata_addr_hi,
2390 temp_sata_addr_low));
2391 } else {
2392 PM8001_FAIL_DBG(pm8001_ha,
2393 pm8001_printk("SAS Address of IO Failure Drive:"
2394 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2395 }
2396 }
2397 switch (status) {
2398 case IO_SUCCESS:
2399 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2400 if (param == 0) {
2401 ts->resp = SAS_TASK_COMPLETE;
2402 ts->stat = SAM_STAT_GOOD;
2403 /* check if response is for SEND READ LOG */
2404 if (pm8001_dev &&
2405 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2406 /* set new bit for abort_all */
2407 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2408 /* clear bit for read log */
2409 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2410 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2411 /* Free the tag */
2412 pm8001_tag_free(pm8001_ha, tag);
2413 sas_free_task(t);
2414 return;
2415 }
2416 } else {
2417 u8 len;
2418 ts->resp = SAS_TASK_COMPLETE;
2419 ts->stat = SAS_PROTO_RESPONSE;
2420 ts->residual = param;
2421 PM8001_IO_DBG(pm8001_ha,
2422 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2423 param));
2424 sata_resp = &psataPayload->sata_resp[0];
2425 resp = (struct ata_task_resp *)ts->buf;
2426 if (t->ata_task.dma_xfer == 0 &&
2427 t->data_dir == DMA_FROM_DEVICE) {
2428 len = sizeof(struct pio_setup_fis);
2429 PM8001_IO_DBG(pm8001_ha,
2430 pm8001_printk("PIO read len = %d\n", len));
2431 } else if (t->ata_task.use_ncq) {
2432 len = sizeof(struct set_dev_bits_fis);
2433 PM8001_IO_DBG(pm8001_ha,
2434 pm8001_printk("FPDMA len = %d\n", len));
2435 } else {
2436 len = sizeof(struct dev_to_host_fis);
2437 PM8001_IO_DBG(pm8001_ha,
2438 pm8001_printk("other len = %d\n", len));
2439 }
2440 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2441 resp->frame_len = len;
2442 memcpy(&resp->ending_fis[0], sata_resp, len);
2443 ts->buf_valid_size = sizeof(*resp);
2444 } else
2445 PM8001_IO_DBG(pm8001_ha,
2446 pm8001_printk("response to large\n"));
2447 }
2448 if (pm8001_dev)
2449 pm8001_dev->running_req--;
2450 break;
2451 case IO_ABORTED:
2452 PM8001_IO_DBG(pm8001_ha,
2453 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2454 ts->resp = SAS_TASK_COMPLETE;
2455 ts->stat = SAS_ABORTED_TASK;
2456 if (pm8001_dev)
2457 pm8001_dev->running_req--;
2458 break;
2459 /* following cases are to do cases */
2460 case IO_UNDERFLOW:
2461 /* SATA Completion with error */
2462 PM8001_IO_DBG(pm8001_ha,
2463 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2464 ts->resp = SAS_TASK_COMPLETE;
2465 ts->stat = SAS_DATA_UNDERRUN;
2466 ts->residual = param;
2467 if (pm8001_dev)
2468 pm8001_dev->running_req--;
2469 break;
2470 case IO_NO_DEVICE:
2471 PM8001_IO_DBG(pm8001_ha,
2472 pm8001_printk("IO_NO_DEVICE\n"));
2473 ts->resp = SAS_TASK_UNDELIVERED;
2474 ts->stat = SAS_PHY_DOWN;
2475 break;
2476 case IO_XFER_ERROR_BREAK:
2477 PM8001_IO_DBG(pm8001_ha,
2478 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2479 ts->resp = SAS_TASK_COMPLETE;
2480 ts->stat = SAS_INTERRUPTED;
2481 break;
2482 case IO_XFER_ERROR_PHY_NOT_READY:
2483 PM8001_IO_DBG(pm8001_ha,
2484 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2485 ts->resp = SAS_TASK_COMPLETE;
2486 ts->stat = SAS_OPEN_REJECT;
2487 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2488 break;
2489 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2490 PM8001_IO_DBG(pm8001_ha,
2491 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2492 "_SUPPORTED\n"));
2493 ts->resp = SAS_TASK_COMPLETE;
2494 ts->stat = SAS_OPEN_REJECT;
2495 ts->open_rej_reason = SAS_OREJ_EPROTO;
2496 break;
2497 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2498 PM8001_IO_DBG(pm8001_ha,
2499 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2500 ts->resp = SAS_TASK_COMPLETE;
2501 ts->stat = SAS_OPEN_REJECT;
2502 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2503 break;
2504 case IO_OPEN_CNX_ERROR_BREAK:
2505 PM8001_IO_DBG(pm8001_ha,
2506 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2507 ts->resp = SAS_TASK_COMPLETE;
2508 ts->stat = SAS_OPEN_REJECT;
2509 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2510 break;
2511 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2512 PM8001_IO_DBG(pm8001_ha,
2513 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2514 ts->resp = SAS_TASK_COMPLETE;
2515 ts->stat = SAS_DEV_NO_RESPONSE;
2516 if (!t->uldd_task) {
2517 pm8001_handle_event(pm8001_ha,
2518 pm8001_dev,
2519 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2520 ts->resp = SAS_TASK_UNDELIVERED;
2521 ts->stat = SAS_QUEUE_FULL;
2522 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2523 return;
2524 }
2525 break;
2526 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2527 PM8001_IO_DBG(pm8001_ha,
2528 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2529 ts->resp = SAS_TASK_UNDELIVERED;
2530 ts->stat = SAS_OPEN_REJECT;
2531 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2532 if (!t->uldd_task) {
2533 pm8001_handle_event(pm8001_ha,
2534 pm8001_dev,
2535 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2536 ts->resp = SAS_TASK_UNDELIVERED;
2537 ts->stat = SAS_QUEUE_FULL;
2538 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2539 return;
2540 }
2541 break;
2542 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2545 "NOT_SUPPORTED\n"));
2546 ts->resp = SAS_TASK_COMPLETE;
2547 ts->stat = SAS_OPEN_REJECT;
2548 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2549 break;
2550 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2551 PM8001_IO_DBG(pm8001_ha,
2552 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2553 "_BUSY\n"));
2554 ts->resp = SAS_TASK_COMPLETE;
2555 ts->stat = SAS_DEV_NO_RESPONSE;
2556 if (!t->uldd_task) {
2557 pm8001_handle_event(pm8001_ha,
2558 pm8001_dev,
2559 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2560 ts->resp = SAS_TASK_UNDELIVERED;
2561 ts->stat = SAS_QUEUE_FULL;
2562 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2563 return;
2564 }
2565 break;
2566 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2567 PM8001_IO_DBG(pm8001_ha,
2568 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2569 ts->resp = SAS_TASK_COMPLETE;
2570 ts->stat = SAS_OPEN_REJECT;
2571 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2572 break;
2573 case IO_XFER_ERROR_NAK_RECEIVED:
2574 PM8001_IO_DBG(pm8001_ha,
2575 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2576 ts->resp = SAS_TASK_COMPLETE;
2577 ts->stat = SAS_NAK_R_ERR;
2578 break;
2579 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2580 PM8001_IO_DBG(pm8001_ha,
2581 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_NAK_R_ERR;
2584 break;
2585 case IO_XFER_ERROR_DMA:
2586 PM8001_IO_DBG(pm8001_ha,
2587 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2588 ts->resp = SAS_TASK_COMPLETE;
2589 ts->stat = SAS_ABORTED_TASK;
2590 break;
2591 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2592 PM8001_IO_DBG(pm8001_ha,
2593 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2594 ts->resp = SAS_TASK_UNDELIVERED;
2595 ts->stat = SAS_DEV_NO_RESPONSE;
2596 break;
2597 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2598 PM8001_IO_DBG(pm8001_ha,
2599 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2600 ts->resp = SAS_TASK_COMPLETE;
2601 ts->stat = SAS_DATA_UNDERRUN;
2602 break;
2603 case IO_XFER_OPEN_RETRY_TIMEOUT:
2604 PM8001_IO_DBG(pm8001_ha,
2605 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2606 ts->resp = SAS_TASK_COMPLETE;
2607 ts->stat = SAS_OPEN_TO;
2608 break;
2609 case IO_PORT_IN_RESET:
2610 PM8001_IO_DBG(pm8001_ha,
2611 pm8001_printk("IO_PORT_IN_RESET\n"));
2612 ts->resp = SAS_TASK_COMPLETE;
2613 ts->stat = SAS_DEV_NO_RESPONSE;
2614 break;
2615 case IO_DS_NON_OPERATIONAL:
2616 PM8001_IO_DBG(pm8001_ha,
2617 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2618 ts->resp = SAS_TASK_COMPLETE;
2619 ts->stat = SAS_DEV_NO_RESPONSE;
2620 if (!t->uldd_task) {
2621 pm8001_handle_event(pm8001_ha, pm8001_dev,
2622 IO_DS_NON_OPERATIONAL);
2623 ts->resp = SAS_TASK_UNDELIVERED;
2624 ts->stat = SAS_QUEUE_FULL;
2625 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2626 return;
2627 }
2628 break;
2629 case IO_DS_IN_RECOVERY:
2630 PM8001_IO_DBG(pm8001_ha,
2631 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2632 ts->resp = SAS_TASK_COMPLETE;
2633 ts->stat = SAS_DEV_NO_RESPONSE;
2634 break;
2635 case IO_DS_IN_ERROR:
2636 PM8001_IO_DBG(pm8001_ha,
2637 pm8001_printk("IO_DS_IN_ERROR\n"));
2638 ts->resp = SAS_TASK_COMPLETE;
2639 ts->stat = SAS_DEV_NO_RESPONSE;
2640 if (!t->uldd_task) {
2641 pm8001_handle_event(pm8001_ha, pm8001_dev,
2642 IO_DS_IN_ERROR);
2643 ts->resp = SAS_TASK_UNDELIVERED;
2644 ts->stat = SAS_QUEUE_FULL;
2645 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2646 return;
2647 }
2648 break;
2649 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2650 PM8001_IO_DBG(pm8001_ha,
2651 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2652 ts->resp = SAS_TASK_COMPLETE;
2653 ts->stat = SAS_OPEN_REJECT;
2654 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2655 break;
2656 default:
2657 PM8001_IO_DBG(pm8001_ha,
2658 pm8001_printk("Unknown status 0x%x\n", status));
2659 /* not allowed case. Therefore, return failed status */
2660 ts->resp = SAS_TASK_COMPLETE;
2661 ts->stat = SAS_DEV_NO_RESPONSE;
2662 break;
2663 }
2664 spin_lock_irqsave(&t->task_state_lock, flags);
2665 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2666 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2667 t->task_state_flags |= SAS_TASK_STATE_DONE;
2668 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2669 spin_unlock_irqrestore(&t->task_state_lock, flags);
2670 PM8001_FAIL_DBG(pm8001_ha,
2671 pm8001_printk("task 0x%p done with io_status 0x%x"
2672 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2673 t, status, ts->resp, ts->stat));
2674 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2675 } else {
2676 spin_unlock_irqrestore(&t->task_state_lock, flags);
2677 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2678 }
2679}
2680
2681/*See the comments for mpi_ssp_completion */
2682static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2683{
2684 struct sas_task *t;
2685 struct task_status_struct *ts;
2686 struct pm8001_ccb_info *ccb;
2687 struct pm8001_device *pm8001_dev;
2688 struct sata_event_resp *psataPayload =
2689 (struct sata_event_resp *)(piomb + 4);
2690 u32 event = le32_to_cpu(psataPayload->event);
2691 u32 tag = le32_to_cpu(psataPayload->tag);
2692 u32 port_id = le32_to_cpu(psataPayload->port_id);
2693 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2694 unsigned long flags;
2695
2696 ccb = &pm8001_ha->ccb_info[tag];
2697
2698 if (ccb) {
2699 t = ccb->task;
2700 pm8001_dev = ccb->device;
2701 } else {
2702 PM8001_FAIL_DBG(pm8001_ha,
2703 pm8001_printk("No CCB !!!. returning\n"));
2704 }
2705 if (event)
2706 PM8001_FAIL_DBG(pm8001_ha,
2707 pm8001_printk("SATA EVENT 0x%x\n", event));
2708
2709 /* Check if this is NCQ error */
2710 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2711 /* find device using device id */
2712 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2713 /* send read log extension */
2714 if (pm8001_dev)
2715 pm8001_send_read_log(pm8001_ha, pm8001_dev);
2716 return;
2717 }
2718
2719 ccb = &pm8001_ha->ccb_info[tag];
2720 t = ccb->task;
2721 pm8001_dev = ccb->device;
2722 if (event)
2723 PM8001_FAIL_DBG(pm8001_ha,
2724 pm8001_printk("sata IO status 0x%x\n", event));
2725 if (unlikely(!t || !t->lldd_task || !t->dev))
2726 return;
2727 ts = &t->task_status;
2728 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2729 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2730 port_id, dev_id, tag, event));
2731 switch (event) {
2732 case IO_OVERFLOW:
2733 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2734 ts->resp = SAS_TASK_COMPLETE;
2735 ts->stat = SAS_DATA_OVERRUN;
2736 ts->residual = 0;
2737 if (pm8001_dev)
2738 pm8001_dev->running_req--;
2739 break;
2740 case IO_XFER_ERROR_BREAK:
2741 PM8001_IO_DBG(pm8001_ha,
2742 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2743 ts->resp = SAS_TASK_COMPLETE;
2744 ts->stat = SAS_INTERRUPTED;
2745 break;
2746 case IO_XFER_ERROR_PHY_NOT_READY:
2747 PM8001_IO_DBG(pm8001_ha,
2748 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2749 ts->resp = SAS_TASK_COMPLETE;
2750 ts->stat = SAS_OPEN_REJECT;
2751 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2752 break;
2753 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2754 PM8001_IO_DBG(pm8001_ha,
2755 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2756 "_SUPPORTED\n"));
2757 ts->resp = SAS_TASK_COMPLETE;
2758 ts->stat = SAS_OPEN_REJECT;
2759 ts->open_rej_reason = SAS_OREJ_EPROTO;
2760 break;
2761 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2762 PM8001_IO_DBG(pm8001_ha,
2763 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2764 ts->resp = SAS_TASK_COMPLETE;
2765 ts->stat = SAS_OPEN_REJECT;
2766 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2767 break;
2768 case IO_OPEN_CNX_ERROR_BREAK:
2769 PM8001_IO_DBG(pm8001_ha,
2770 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2771 ts->resp = SAS_TASK_COMPLETE;
2772 ts->stat = SAS_OPEN_REJECT;
2773 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2774 break;
2775 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2776 PM8001_IO_DBG(pm8001_ha,
2777 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2778 ts->resp = SAS_TASK_UNDELIVERED;
2779 ts->stat = SAS_DEV_NO_RESPONSE;
2780 if (!t->uldd_task) {
2781 pm8001_handle_event(pm8001_ha,
2782 pm8001_dev,
2783 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2784 ts->resp = SAS_TASK_COMPLETE;
2785 ts->stat = SAS_QUEUE_FULL;
2786 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2787 return;
2788 }
2789 break;
2790 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2791 PM8001_IO_DBG(pm8001_ha,
2792 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2793 ts->resp = SAS_TASK_UNDELIVERED;
2794 ts->stat = SAS_OPEN_REJECT;
2795 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2796 break;
2797 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2798 PM8001_IO_DBG(pm8001_ha,
2799 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2800 "NOT_SUPPORTED\n"));
2801 ts->resp = SAS_TASK_COMPLETE;
2802 ts->stat = SAS_OPEN_REJECT;
2803 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2804 break;
2805 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2806 PM8001_IO_DBG(pm8001_ha,
2807 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2808 ts->resp = SAS_TASK_COMPLETE;
2809 ts->stat = SAS_OPEN_REJECT;
2810 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2811 break;
2812 case IO_XFER_ERROR_NAK_RECEIVED:
2813 PM8001_IO_DBG(pm8001_ha,
2814 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2815 ts->resp = SAS_TASK_COMPLETE;
2816 ts->stat = SAS_NAK_R_ERR;
2817 break;
2818 case IO_XFER_ERROR_PEER_ABORTED:
2819 PM8001_IO_DBG(pm8001_ha,
2820 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2821 ts->resp = SAS_TASK_COMPLETE;
2822 ts->stat = SAS_NAK_R_ERR;
2823 break;
2824 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2825 PM8001_IO_DBG(pm8001_ha,
2826 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2827 ts->resp = SAS_TASK_COMPLETE;
2828 ts->stat = SAS_DATA_UNDERRUN;
2829 break;
2830 case IO_XFER_OPEN_RETRY_TIMEOUT:
2831 PM8001_IO_DBG(pm8001_ha,
2832 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2833 ts->resp = SAS_TASK_COMPLETE;
2834 ts->stat = SAS_OPEN_TO;
2835 break;
2836 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2837 PM8001_IO_DBG(pm8001_ha,
2838 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2839 ts->resp = SAS_TASK_COMPLETE;
2840 ts->stat = SAS_OPEN_TO;
2841 break;
2842 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2843 PM8001_IO_DBG(pm8001_ha,
2844 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2845 ts->resp = SAS_TASK_COMPLETE;
2846 ts->stat = SAS_OPEN_TO;
2847 break;
2848 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2849 PM8001_IO_DBG(pm8001_ha,
2850 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2851 ts->resp = SAS_TASK_COMPLETE;
2852 ts->stat = SAS_OPEN_TO;
2853 break;
2854 case IO_XFER_ERROR_OFFSET_MISMATCH:
2855 PM8001_IO_DBG(pm8001_ha,
2856 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2857 ts->resp = SAS_TASK_COMPLETE;
2858 ts->stat = SAS_OPEN_TO;
2859 break;
2860 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2861 PM8001_IO_DBG(pm8001_ha,
2862 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2863 ts->resp = SAS_TASK_COMPLETE;
2864 ts->stat = SAS_OPEN_TO;
2865 break;
2866 case IO_XFER_CMD_FRAME_ISSUED:
2867 PM8001_IO_DBG(pm8001_ha,
2868 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2869 break;
2870 case IO_XFER_PIO_SETUP_ERROR:
2871 PM8001_IO_DBG(pm8001_ha,
2872 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2873 ts->resp = SAS_TASK_COMPLETE;
2874 ts->stat = SAS_OPEN_TO;
2875 break;
2876 default:
2877 PM8001_IO_DBG(pm8001_ha,
2878 pm8001_printk("Unknown status 0x%x\n", event));
2879 /* not allowed case. Therefore, return failed status */
2880 ts->resp = SAS_TASK_COMPLETE;
2881 ts->stat = SAS_OPEN_TO;
2882 break;
2883 }
2884 spin_lock_irqsave(&t->task_state_lock, flags);
2885 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2886 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2887 t->task_state_flags |= SAS_TASK_STATE_DONE;
2888 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2889 spin_unlock_irqrestore(&t->task_state_lock, flags);
2890 PM8001_FAIL_DBG(pm8001_ha,
2891 pm8001_printk("task 0x%p done with io_status 0x%x"
2892 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2893 t, event, ts->resp, ts->stat));
2894 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2895 } else {
2896 spin_unlock_irqrestore(&t->task_state_lock, flags);
2897 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2898 }
2899}
2900
2901/*See the comments for mpi_ssp_completion */
2902static void
2903mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2904{
2905 struct sas_task *t;
2906 struct pm8001_ccb_info *ccb;
2907 unsigned long flags;
2908 u32 status;
2909 u32 tag;
2910 struct smp_completion_resp *psmpPayload;
2911 struct task_status_struct *ts;
2912 struct pm8001_device *pm8001_dev;
2913
2914 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2915 status = le32_to_cpu(psmpPayload->status);
2916 tag = le32_to_cpu(psmpPayload->tag);
2917
2918 ccb = &pm8001_ha->ccb_info[tag];
2919 t = ccb->task;
2920 ts = &t->task_status;
2921 pm8001_dev = ccb->device;
2922 if (status)
2923 PM8001_FAIL_DBG(pm8001_ha,
2924 pm8001_printk("smp IO status 0x%x\n", status));
2925 if (unlikely(!t || !t->lldd_task || !t->dev))
2926 return;
2927
2928 switch (status) {
2929 case IO_SUCCESS:
2930 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2931 ts->resp = SAS_TASK_COMPLETE;
2932 ts->stat = SAM_STAT_GOOD;
2933 if (pm8001_dev)
2934 pm8001_dev->running_req--;
2935 break;
2936 case IO_ABORTED:
2937 PM8001_IO_DBG(pm8001_ha,
2938 pm8001_printk("IO_ABORTED IOMB\n"));
2939 ts->resp = SAS_TASK_COMPLETE;
2940 ts->stat = SAS_ABORTED_TASK;
2941 if (pm8001_dev)
2942 pm8001_dev->running_req--;
2943 break;
2944 case IO_OVERFLOW:
2945 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2946 ts->resp = SAS_TASK_COMPLETE;
2947 ts->stat = SAS_DATA_OVERRUN;
2948 ts->residual = 0;
2949 if (pm8001_dev)
2950 pm8001_dev->running_req--;
2951 break;
2952 case IO_NO_DEVICE:
2953 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2954 ts->resp = SAS_TASK_COMPLETE;
2955 ts->stat = SAS_PHY_DOWN;
2956 break;
2957 case IO_ERROR_HW_TIMEOUT:
2958 PM8001_IO_DBG(pm8001_ha,
2959 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2960 ts->resp = SAS_TASK_COMPLETE;
2961 ts->stat = SAM_STAT_BUSY;
2962 break;
2963 case IO_XFER_ERROR_BREAK:
2964 PM8001_IO_DBG(pm8001_ha,
2965 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2966 ts->resp = SAS_TASK_COMPLETE;
2967 ts->stat = SAM_STAT_BUSY;
2968 break;
2969 case IO_XFER_ERROR_PHY_NOT_READY:
2970 PM8001_IO_DBG(pm8001_ha,
2971 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2972 ts->resp = SAS_TASK_COMPLETE;
2973 ts->stat = SAM_STAT_BUSY;
2974 break;
2975 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2976 PM8001_IO_DBG(pm8001_ha,
2977 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2978 ts->resp = SAS_TASK_COMPLETE;
2979 ts->stat = SAS_OPEN_REJECT;
2980 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2981 break;
2982 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2983 PM8001_IO_DBG(pm8001_ha,
2984 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2985 ts->resp = SAS_TASK_COMPLETE;
2986 ts->stat = SAS_OPEN_REJECT;
2987 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2988 break;
2989 case IO_OPEN_CNX_ERROR_BREAK:
2990 PM8001_IO_DBG(pm8001_ha,
2991 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2992 ts->resp = SAS_TASK_COMPLETE;
2993 ts->stat = SAS_OPEN_REJECT;
2994 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2995 break;
2996 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2997 PM8001_IO_DBG(pm8001_ha,
2998 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2999 ts->resp = SAS_TASK_COMPLETE;
3000 ts->stat = SAS_OPEN_REJECT;
3001 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3002 pm8001_handle_event(pm8001_ha,
3003 pm8001_dev,
3004 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3005 break;
3006 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3007 PM8001_IO_DBG(pm8001_ha,
3008 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3009 ts->resp = SAS_TASK_COMPLETE;
3010 ts->stat = SAS_OPEN_REJECT;
3011 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3012 break;
3013 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3014 PM8001_IO_DBG(pm8001_ha,
3015 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3016 "NOT_SUPPORTED\n"));
3017 ts->resp = SAS_TASK_COMPLETE;
3018 ts->stat = SAS_OPEN_REJECT;
3019 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3020 break;
3021 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3022 PM8001_IO_DBG(pm8001_ha,
3023 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3024 ts->resp = SAS_TASK_COMPLETE;
3025 ts->stat = SAS_OPEN_REJECT;
3026 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3027 break;
3028 case IO_XFER_ERROR_RX_FRAME:
3029 PM8001_IO_DBG(pm8001_ha,
3030 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3031 ts->resp = SAS_TASK_COMPLETE;
3032 ts->stat = SAS_DEV_NO_RESPONSE;
3033 break;
3034 case IO_XFER_OPEN_RETRY_TIMEOUT:
3035 PM8001_IO_DBG(pm8001_ha,
3036 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3037 ts->resp = SAS_TASK_COMPLETE;
3038 ts->stat = SAS_OPEN_REJECT;
3039 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3040 break;
3041 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3042 PM8001_IO_DBG(pm8001_ha,
3043 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3044 ts->resp = SAS_TASK_COMPLETE;
3045 ts->stat = SAS_QUEUE_FULL;
3046 break;
3047 case IO_PORT_IN_RESET:
3048 PM8001_IO_DBG(pm8001_ha,
3049 pm8001_printk("IO_PORT_IN_RESET\n"));
3050 ts->resp = SAS_TASK_COMPLETE;
3051 ts->stat = SAS_OPEN_REJECT;
3052 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3053 break;
3054 case IO_DS_NON_OPERATIONAL:
3055 PM8001_IO_DBG(pm8001_ha,
3056 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3057 ts->resp = SAS_TASK_COMPLETE;
3058 ts->stat = SAS_DEV_NO_RESPONSE;
3059 break;
3060 case IO_DS_IN_RECOVERY:
3061 PM8001_IO_DBG(pm8001_ha,
3062 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3063 ts->resp = SAS_TASK_COMPLETE;
3064 ts->stat = SAS_OPEN_REJECT;
3065 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3066 break;
3067 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3068 PM8001_IO_DBG(pm8001_ha,
3069 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3070 ts->resp = SAS_TASK_COMPLETE;
3071 ts->stat = SAS_OPEN_REJECT;
3072 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3073 break;
3074 default:
3075 PM8001_IO_DBG(pm8001_ha,
3076 pm8001_printk("Unknown status 0x%x\n", status));
3077 ts->resp = SAS_TASK_COMPLETE;
3078 ts->stat = SAS_DEV_NO_RESPONSE;
3079 /* not allowed case. Therefore, return failed status */
3080 break;
3081 }
3082 spin_lock_irqsave(&t->task_state_lock, flags);
3083 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3084 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3085 t->task_state_flags |= SAS_TASK_STATE_DONE;
3086 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3087 spin_unlock_irqrestore(&t->task_state_lock, flags);
3088 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3089 " io_status 0x%x resp 0x%x "
3090 "stat 0x%x but aborted by upper layer!\n",
3091 t, status, ts->resp, ts->stat));
3092 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3093 } else {
3094 spin_unlock_irqrestore(&t->task_state_lock, flags);
3095 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3096 mb();/* in order to force CPU ordering */
3097 t->task_done(t);
3098 }
3099}
3100
3101void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3102 void *piomb)
3103{
3104 struct set_dev_state_resp *pPayload =
3105 (struct set_dev_state_resp *)(piomb + 4);
3106 u32 tag = le32_to_cpu(pPayload->tag);
3107 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3108 struct pm8001_device *pm8001_dev = ccb->device;
3109 u32 status = le32_to_cpu(pPayload->status);
3110 u32 device_id = le32_to_cpu(pPayload->device_id);
3111 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3112 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3113 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3114 "from 0x%x to 0x%x status = 0x%x!\n",
3115 device_id, pds, nds, status));
3116 complete(pm8001_dev->setds_completion);
3117 ccb->task = NULL;
3118 ccb->ccb_tag = 0xFFFFFFFF;
3119 pm8001_tag_free(pm8001_ha, tag);
3120}
3121
3122void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3123{
3124 struct get_nvm_data_resp *pPayload =
3125 (struct get_nvm_data_resp *)(piomb + 4);
3126 u32 tag = le32_to_cpu(pPayload->tag);
3127 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3128 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3129 complete(pm8001_ha->nvmd_completion);
3130 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3131 if ((dlen_status & NVMD_STAT) != 0) {
3132 PM8001_FAIL_DBG(pm8001_ha,
3133 pm8001_printk("Set nvm data error!\n"));
3134 return;
3135 }
3136 ccb->task = NULL;
3137 ccb->ccb_tag = 0xFFFFFFFF;
3138 pm8001_tag_free(pm8001_ha, tag);
3139}
3140
3141void
3142pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3143{
3144 struct fw_control_ex *fw_control_context;
3145 struct get_nvm_data_resp *pPayload =
3146 (struct get_nvm_data_resp *)(piomb + 4);
3147 u32 tag = le32_to_cpu(pPayload->tag);
3148 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3149 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3150 u32 ir_tds_bn_dps_das_nvm =
3151 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3152 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3153 fw_control_context = ccb->fw_control_context;
3154
3155 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3156 if ((dlen_status & NVMD_STAT) != 0) {
3157 PM8001_FAIL_DBG(pm8001_ha,
3158 pm8001_printk("Get nvm data error!\n"));
3159 complete(pm8001_ha->nvmd_completion);
3160 return;
3161 }
3162
3163 if (ir_tds_bn_dps_das_nvm & IPMode) {
3164 /* indirect mode - IR bit set */
3165 PM8001_MSG_DBG(pm8001_ha,
3166 pm8001_printk("Get NVMD success, IR=1\n"));
3167 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3168 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3169 memcpy(pm8001_ha->sas_addr,
3170 ((u8 *)virt_addr + 4),
3171 SAS_ADDR_SIZE);
3172 PM8001_MSG_DBG(pm8001_ha,
3173 pm8001_printk("Get SAS address"
3174 " from VPD successfully!\n"));
3175 }
3176 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3177 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3178 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3179 ;
3180 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3181 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3182 ;
3183 } else {
3184 /* Should not be happened*/
3185 PM8001_MSG_DBG(pm8001_ha,
3186 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3187 ir_tds_bn_dps_das_nvm));
3188 }
3189 } else /* direct mode */{
3190 PM8001_MSG_DBG(pm8001_ha,
3191 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3192 (dlen_status & NVMD_LEN) >> 24));
3193 }
3194 /* Though fw_control_context is freed below, usrAddr still needs
3195 * to be updated as this holds the response to the request function
3196 */
3197 memcpy(fw_control_context->usrAddr,
3198 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3199 fw_control_context->len);
3200 kfree(ccb->fw_control_context);
3201 ccb->task = NULL;
3202 ccb->ccb_tag = 0xFFFFFFFF;
3203 pm8001_tag_free(pm8001_ha, tag);
3204 complete(pm8001_ha->nvmd_completion);
3205}
3206
3207int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3208{
3209 u32 tag;
3210 struct local_phy_ctl_resp *pPayload =
3211 (struct local_phy_ctl_resp *)(piomb + 4);
3212 u32 status = le32_to_cpu(pPayload->status);
3213 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3214 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3215 tag = le32_to_cpu(pPayload->tag);
3216 if (status != 0) {
3217 PM8001_MSG_DBG(pm8001_ha,
3218 pm8001_printk("%x phy execute %x phy op failed!\n",
3219 phy_id, phy_op));
3220 } else {
3221 PM8001_MSG_DBG(pm8001_ha,
3222 pm8001_printk("%x phy execute %x phy op success!\n",
3223 phy_id, phy_op));
3224 pm8001_ha->phy[phy_id].reset_success = true;
3225 }
3226 if (pm8001_ha->phy[phy_id].enable_completion) {
3227 complete(pm8001_ha->phy[phy_id].enable_completion);
3228 pm8001_ha->phy[phy_id].enable_completion = NULL;
3229 }
3230 pm8001_tag_free(pm8001_ha, tag);
3231 return 0;
3232}
3233
3234/**
3235 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3236 * @pm8001_ha: our hba card information
3237 * @i: which phy that received the event.
3238 *
3239 * when HBA driver received the identify done event or initiate FIS received
3240 * event(for SATA), it will invoke this function to notify the sas layer that
3241 * the sas toplogy has formed, please discover the the whole sas domain,
3242 * while receive a broadcast(change) primitive just tell the sas
3243 * layer to discover the changed domain rather than the whole domain.
3244 */
3245void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3246{
3247 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3248 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3249 if (!phy->phy_attached)
3250 return;
3251
3252 if (sas_phy->phy) {
3253 struct sas_phy *sphy = sas_phy->phy;
3254 sphy->negotiated_linkrate = sas_phy->linkrate;
3255 sphy->minimum_linkrate = phy->minimum_linkrate;
3256 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3257 sphy->maximum_linkrate = phy->maximum_linkrate;
3258 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3259 }
3260
3261 if (phy->phy_type & PORT_TYPE_SAS) {
3262 struct sas_identify_frame *id;
3263 id = (struct sas_identify_frame *)phy->frame_rcvd;
3264 id->dev_type = phy->identify.device_type;
3265 id->initiator_bits = SAS_PROTOCOL_ALL;
3266 id->target_bits = phy->identify.target_port_protocols;
3267 } else if (phy->phy_type & PORT_TYPE_SATA) {
3268 /*Nothing*/
3269 }
3270 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3271
3272 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3273 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3274}
3275
3276/* Get the link rate speed */
3277void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3278{
3279 struct sas_phy *sas_phy = phy->sas_phy.phy;
3280
3281 switch (link_rate) {
3282 case PHY_SPEED_120:
3283 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3284 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3285 break;
3286 case PHY_SPEED_60:
3287 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3288 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3289 break;
3290 case PHY_SPEED_30:
3291 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3292 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3293 break;
3294 case PHY_SPEED_15:
3295 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3296 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3297 break;
3298 }
3299 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3300 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3301 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3302 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3303 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3304}
3305
3306/**
3307 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3308 * @phy: pointer to asd_phy
3309 * @sas_addr: pointer to buffer where the SAS address is to be written
3310 *
3311 * This function extracts the SAS address from an IDENTIFY frame
3312 * received. If OOB is SATA, then a SAS address is generated from the
3313 * HA tables.
3314 *
3315 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3316 * buffer.
3317 */
3318void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3319 u8 *sas_addr)
3320{
3321 if (phy->sas_phy.frame_rcvd[0] == 0x34
3322 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3323 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3324 /* FIS device-to-host */
3325 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3326 addr += phy->sas_phy.id;
3327 *(__be64 *)sas_addr = cpu_to_be64(addr);
3328 } else {
3329 struct sas_identify_frame *idframe =
3330 (void *) phy->sas_phy.frame_rcvd;
3331 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3332 }
3333}
3334
3335/**
3336 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3337 * @pm8001_ha: our hba card information
3338 * @Qnum: the outbound queue message number.
3339 * @SEA: source of event to ack
3340 * @port_id: port id.
3341 * @phyId: phy id.
3342 * @param0: parameter 0.
3343 * @param1: parameter 1.
3344 */
3345static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3346 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3347{
3348 struct hw_event_ack_req payload;
3349 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3350
3351 struct inbound_queue_table *circularQ;
3352
3353 memset((u8 *)&payload, 0, sizeof(payload));
3354 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3355 payload.tag = cpu_to_le32(1);
3356 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3357 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3358 payload.param0 = cpu_to_le32(param0);
3359 payload.param1 = cpu_to_le32(param1);
3360 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3361}
3362
3363static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3364 u32 phyId, u32 phy_op);
3365
3366/**
3367 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3368 * @pm8001_ha: our hba card information
3369 * @piomb: IO message buffer
3370 */
3371static void
3372hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3373{
3374 struct hw_event_resp *pPayload =
3375 (struct hw_event_resp *)(piomb + 4);
3376 u32 lr_evt_status_phyid_portid =
3377 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3378 u8 link_rate =
3379 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3380 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3381 u8 phy_id =
3382 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3383 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3384 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3385 struct pm8001_port *port = &pm8001_ha->port[port_id];
3386 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3387 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3388 unsigned long flags;
3389 u8 deviceType = pPayload->sas_identify.dev_type;
3390 port->port_state = portstate;
3391 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3392 PM8001_MSG_DBG(pm8001_ha,
3393 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3394 port_id, phy_id));
3395
3396 switch (deviceType) {
3397 case SAS_PHY_UNUSED:
3398 PM8001_MSG_DBG(pm8001_ha,
3399 pm8001_printk("device type no device.\n"));
3400 break;
3401 case SAS_END_DEVICE:
3402 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3403 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3404 PHY_NOTIFY_ENABLE_SPINUP);
3405 port->port_attached = 1;
3406 pm8001_get_lrate_mode(phy, link_rate);
3407 break;
3408 case SAS_EDGE_EXPANDER_DEVICE:
3409 PM8001_MSG_DBG(pm8001_ha,
3410 pm8001_printk("expander device.\n"));
3411 port->port_attached = 1;
3412 pm8001_get_lrate_mode(phy, link_rate);
3413 break;
3414 case SAS_FANOUT_EXPANDER_DEVICE:
3415 PM8001_MSG_DBG(pm8001_ha,
3416 pm8001_printk("fanout expander device.\n"));
3417 port->port_attached = 1;
3418 pm8001_get_lrate_mode(phy, link_rate);
3419 break;
3420 default:
3421 PM8001_MSG_DBG(pm8001_ha,
3422 pm8001_printk("unknown device type(%x)\n", deviceType));
3423 break;
3424 }
3425 phy->phy_type |= PORT_TYPE_SAS;
3426 phy->identify.device_type = deviceType;
3427 phy->phy_attached = 1;
3428 if (phy->identify.device_type == SAS_END_DEVICE)
3429 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3430 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3431 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3432 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3433 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3434 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3435 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3436 sizeof(struct sas_identify_frame)-4);
3437 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3438 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3439 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3440 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3441 mdelay(200);/*delay a moment to wait disk to spinup*/
3442 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3443}
3444
3445/**
3446 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3447 * @pm8001_ha: our hba card information
3448 * @piomb: IO message buffer
3449 */
3450static void
3451hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3452{
3453 struct hw_event_resp *pPayload =
3454 (struct hw_event_resp *)(piomb + 4);
3455 u32 lr_evt_status_phyid_portid =
3456 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3457 u8 link_rate =
3458 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3459 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3460 u8 phy_id =
3461 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3462 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3463 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3464 struct pm8001_port *port = &pm8001_ha->port[port_id];
3465 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3466 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3467 unsigned long flags;
3468 PM8001_MSG_DBG(pm8001_ha,
3469 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3470 " phy id = %d\n", port_id, phy_id));
3471 port->port_state = portstate;
3472 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3473 port->port_attached = 1;
3474 pm8001_get_lrate_mode(phy, link_rate);
3475 phy->phy_type |= PORT_TYPE_SATA;
3476 phy->phy_attached = 1;
3477 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3478 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3479 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3480 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3481 sizeof(struct dev_to_host_fis));
3482 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3483 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3484 phy->identify.device_type = SAS_SATA_DEV;
3485 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3486 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3487 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3488}
3489
3490/**
3491 * hw_event_phy_down -we should notify the libsas the phy is down.
3492 * @pm8001_ha: our hba card information
3493 * @piomb: IO message buffer
3494 */
3495static void
3496hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3497{
3498 struct hw_event_resp *pPayload =
3499 (struct hw_event_resp *)(piomb + 4);
3500 u32 lr_evt_status_phyid_portid =
3501 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3502 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3503 u8 phy_id =
3504 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3505 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3506 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3507 struct pm8001_port *port = &pm8001_ha->port[port_id];
3508 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3509 port->port_state = portstate;
3510 phy->phy_type = 0;
3511 phy->identify.device_type = 0;
3512 phy->phy_attached = 0;
3513 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3514 switch (portstate) {
3515 case PORT_VALID:
3516 break;
3517 case PORT_INVALID:
3518 PM8001_MSG_DBG(pm8001_ha,
3519 pm8001_printk(" PortInvalid portID %d\n", port_id));
3520 PM8001_MSG_DBG(pm8001_ha,
3521 pm8001_printk(" Last phy Down and port invalid\n"));
3522 port->port_attached = 0;
3523 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3524 port_id, phy_id, 0, 0);
3525 break;
3526 case PORT_IN_RESET:
3527 PM8001_MSG_DBG(pm8001_ha,
3528 pm8001_printk(" Port In Reset portID %d\n", port_id));
3529 break;
3530 case PORT_NOT_ESTABLISHED:
3531 PM8001_MSG_DBG(pm8001_ha,
3532 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3533 port->port_attached = 0;
3534 break;
3535 case PORT_LOSTCOMM:
3536 PM8001_MSG_DBG(pm8001_ha,
3537 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3538 PM8001_MSG_DBG(pm8001_ha,
3539 pm8001_printk(" Last phy Down and port invalid\n"));
3540 port->port_attached = 0;
3541 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3542 port_id, phy_id, 0, 0);
3543 break;
3544 default:
3545 port->port_attached = 0;
3546 PM8001_MSG_DBG(pm8001_ha,
3547 pm8001_printk(" phy Down and(default) = %x\n",
3548 portstate));
3549 break;
3550
3551 }
3552}
3553
3554/**
3555 * pm8001_mpi_reg_resp -process register device ID response.
3556 * @pm8001_ha: our hba card information
3557 * @piomb: IO message buffer
3558 *
3559 * when sas layer find a device it will notify LLDD, then the driver register
3560 * the domain device to FW, this event is the return device ID which the FW
3561 * has assigned, from now,inter-communication with FW is no longer using the
3562 * SAS address, use device ID which FW assigned.
3563 */
3564int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3565{
3566 u32 status;
3567 u32 device_id;
3568 u32 htag;
3569 struct pm8001_ccb_info *ccb;
3570 struct pm8001_device *pm8001_dev;
3571 struct dev_reg_resp *registerRespPayload =
3572 (struct dev_reg_resp *)(piomb + 4);
3573
3574 htag = le32_to_cpu(registerRespPayload->tag);
3575 ccb = &pm8001_ha->ccb_info[htag];
3576 pm8001_dev = ccb->device;
3577 status = le32_to_cpu(registerRespPayload->status);
3578 device_id = le32_to_cpu(registerRespPayload->device_id);
3579 PM8001_MSG_DBG(pm8001_ha,
3580 pm8001_printk(" register device is status = %d\n", status));
3581 switch (status) {
3582 case DEVREG_SUCCESS:
3583 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3584 pm8001_dev->device_id = device_id;
3585 break;
3586 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3587 PM8001_MSG_DBG(pm8001_ha,
3588 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3589 break;
3590 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3591 PM8001_MSG_DBG(pm8001_ha,
3592 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3593 break;
3594 case DEVREG_FAILURE_INVALID_PHY_ID:
3595 PM8001_MSG_DBG(pm8001_ha,
3596 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3597 break;
3598 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3599 PM8001_MSG_DBG(pm8001_ha,
3600 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3601 break;
3602 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3603 PM8001_MSG_DBG(pm8001_ha,
3604 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3605 break;
3606 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3607 PM8001_MSG_DBG(pm8001_ha,
3608 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3609 break;
3610 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3611 PM8001_MSG_DBG(pm8001_ha,
3612 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3613 break;
3614 default:
3615 PM8001_MSG_DBG(pm8001_ha,
3616 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"));
3617 break;
3618 }
3619 complete(pm8001_dev->dcompletion);
3620 ccb->task = NULL;
3621 ccb->ccb_tag = 0xFFFFFFFF;
3622 pm8001_tag_free(pm8001_ha, htag);
3623 return 0;
3624}
3625
3626int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3627{
3628 u32 status;
3629 u32 device_id;
3630 struct dev_reg_resp *registerRespPayload =
3631 (struct dev_reg_resp *)(piomb + 4);
3632
3633 status = le32_to_cpu(registerRespPayload->status);
3634 device_id = le32_to_cpu(registerRespPayload->device_id);
3635 if (status != 0)
3636 PM8001_MSG_DBG(pm8001_ha,
3637 pm8001_printk(" deregister device failed ,status = %x"
3638 ", device_id = %x\n", status, device_id));
3639 return 0;
3640}
3641
3642/**
3643 * fw_flash_update_resp - Response from FW for flash update command.
3644 * @pm8001_ha: our hba card information
3645 * @piomb: IO message buffer
3646 */
3647int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3648 void *piomb)
3649{
3650 u32 status;
3651 struct fw_flash_Update_resp *ppayload =
3652 (struct fw_flash_Update_resp *)(piomb + 4);
3653 u32 tag = le32_to_cpu(ppayload->tag);
3654 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3655 status = le32_to_cpu(ppayload->status);
3656 switch (status) {
3657 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3658 PM8001_MSG_DBG(pm8001_ha,
3659 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3660 break;
3661 case FLASH_UPDATE_IN_PROGRESS:
3662 PM8001_MSG_DBG(pm8001_ha,
3663 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3664 break;
3665 case FLASH_UPDATE_HDR_ERR:
3666 PM8001_MSG_DBG(pm8001_ha,
3667 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3668 break;
3669 case FLASH_UPDATE_OFFSET_ERR:
3670 PM8001_MSG_DBG(pm8001_ha,
3671 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3672 break;
3673 case FLASH_UPDATE_CRC_ERR:
3674 PM8001_MSG_DBG(pm8001_ha,
3675 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3676 break;
3677 case FLASH_UPDATE_LENGTH_ERR:
3678 PM8001_MSG_DBG(pm8001_ha,
3679 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3680 break;
3681 case FLASH_UPDATE_HW_ERR:
3682 PM8001_MSG_DBG(pm8001_ha,
3683 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3684 break;
3685 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3686 PM8001_MSG_DBG(pm8001_ha,
3687 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3688 break;
3689 case FLASH_UPDATE_DISABLED:
3690 PM8001_MSG_DBG(pm8001_ha,
3691 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3692 break;
3693 default:
3694 PM8001_MSG_DBG(pm8001_ha,
3695 pm8001_printk("No matched status = %d\n", status));
3696 break;
3697 }
3698 kfree(ccb->fw_control_context);
3699 ccb->task = NULL;
3700 ccb->ccb_tag = 0xFFFFFFFF;
3701 pm8001_tag_free(pm8001_ha, tag);
3702 complete(pm8001_ha->nvmd_completion);
3703 return 0;
3704}
3705
3706int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3707{
3708 u32 status;
3709 int i;
3710 struct general_event_resp *pPayload =
3711 (struct general_event_resp *)(piomb + 4);
3712 status = le32_to_cpu(pPayload->status);
3713 PM8001_MSG_DBG(pm8001_ha,
3714 pm8001_printk(" status = 0x%x\n", status));
3715 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3716 PM8001_MSG_DBG(pm8001_ha,
3717 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3718 pPayload->inb_IOMB_payload[i]));
3719 return 0;
3720}
3721
3722int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3723{
3724 struct sas_task *t;
3725 struct pm8001_ccb_info *ccb;
3726 unsigned long flags;
3727 u32 status ;
3728 u32 tag, scp;
3729 struct task_status_struct *ts;
3730 struct pm8001_device *pm8001_dev;
3731
3732 struct task_abort_resp *pPayload =
3733 (struct task_abort_resp *)(piomb + 4);
3734
3735 status = le32_to_cpu(pPayload->status);
3736 tag = le32_to_cpu(pPayload->tag);
3737 if (!tag) {
3738 PM8001_FAIL_DBG(pm8001_ha,
3739 pm8001_printk(" TAG NULL. RETURNING !!!"));
3740 return -1;
3741 }
3742
3743 scp = le32_to_cpu(pPayload->scp);
3744 ccb = &pm8001_ha->ccb_info[tag];
3745 t = ccb->task;
3746 pm8001_dev = ccb->device; /* retrieve device */
3747
3748 if (!t) {
3749 PM8001_FAIL_DBG(pm8001_ha,
3750 pm8001_printk(" TASK NULL. RETURNING !!!"));
3751 return -1;
3752 }
3753 ts = &t->task_status;
3754 if (status != 0)
3755 PM8001_FAIL_DBG(pm8001_ha,
3756 pm8001_printk("task abort failed status 0x%x ,"
3757 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3758 switch (status) {
3759 case IO_SUCCESS:
3760 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3761 ts->resp = SAS_TASK_COMPLETE;
3762 ts->stat = SAM_STAT_GOOD;
3763 break;
3764 case IO_NOT_VALID:
3765 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3766 ts->resp = TMF_RESP_FUNC_FAILED;
3767 break;
3768 }
3769 spin_lock_irqsave(&t->task_state_lock, flags);
3770 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3771 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3772 t->task_state_flags |= SAS_TASK_STATE_DONE;
3773 spin_unlock_irqrestore(&t->task_state_lock, flags);
3774 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3775 mb();
3776
3777 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3778 sas_free_task(t);
3779 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3780 } else {
3781 t->task_done(t);
3782 }
3783
3784 return 0;
3785}
3786
3787/**
3788 * mpi_hw_event -The hw event has come.
3789 * @pm8001_ha: our hba card information
3790 * @piomb: IO message buffer
3791 */
3792static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3793{
3794 unsigned long flags;
3795 struct hw_event_resp *pPayload =
3796 (struct hw_event_resp *)(piomb + 4);
3797 u32 lr_evt_status_phyid_portid =
3798 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3799 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3800 u8 phy_id =
3801 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3802 u16 eventType =
3803 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3804 u8 status =
3805 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3806 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3807 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3808 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3809 PM8001_MSG_DBG(pm8001_ha,
3810 pm8001_printk("outbound queue HW event & event type : "));
3811 switch (eventType) {
3812 case HW_EVENT_PHY_START_STATUS:
3813 PM8001_MSG_DBG(pm8001_ha,
3814 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3815 " status = %x\n", status));
3816 if (status == 0) {
3817 phy->phy_state = 1;
3818 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3819 phy->enable_completion != NULL)
3820 complete(phy->enable_completion);
3821 }
3822 break;
3823 case HW_EVENT_SAS_PHY_UP:
3824 PM8001_MSG_DBG(pm8001_ha,
3825 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3826 hw_event_sas_phy_up(pm8001_ha, piomb);
3827 break;
3828 case HW_EVENT_SATA_PHY_UP:
3829 PM8001_MSG_DBG(pm8001_ha,
3830 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3831 hw_event_sata_phy_up(pm8001_ha, piomb);
3832 break;
3833 case HW_EVENT_PHY_STOP_STATUS:
3834 PM8001_MSG_DBG(pm8001_ha,
3835 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3836 "status = %x\n", status));
3837 if (status == 0)
3838 phy->phy_state = 0;
3839 break;
3840 case HW_EVENT_SATA_SPINUP_HOLD:
3841 PM8001_MSG_DBG(pm8001_ha,
3842 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3843 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3844 break;
3845 case HW_EVENT_PHY_DOWN:
3846 PM8001_MSG_DBG(pm8001_ha,
3847 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3848 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3849 phy->phy_attached = 0;
3850 phy->phy_state = 0;
3851 hw_event_phy_down(pm8001_ha, piomb);
3852 break;
3853 case HW_EVENT_PORT_INVALID:
3854 PM8001_MSG_DBG(pm8001_ha,
3855 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3856 sas_phy_disconnected(sas_phy);
3857 phy->phy_attached = 0;
3858 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3859 break;
3860 /* the broadcast change primitive received, tell the LIBSAS this event
3861 to revalidate the sas domain*/
3862 case HW_EVENT_BROADCAST_CHANGE:
3863 PM8001_MSG_DBG(pm8001_ha,
3864 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3865 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3866 port_id, phy_id, 1, 0);
3867 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3868 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3869 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3870 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3871 break;
3872 case HW_EVENT_PHY_ERROR:
3873 PM8001_MSG_DBG(pm8001_ha,
3874 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3875 sas_phy_disconnected(&phy->sas_phy);
3876 phy->phy_attached = 0;
3877 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3878 break;
3879 case HW_EVENT_BROADCAST_EXP:
3880 PM8001_MSG_DBG(pm8001_ha,
3881 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3882 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3883 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3884 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3885 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3886 break;
3887 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3888 PM8001_MSG_DBG(pm8001_ha,
3889 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3890 pm8001_hw_event_ack_req(pm8001_ha, 0,
3891 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3892 sas_phy_disconnected(sas_phy);
3893 phy->phy_attached = 0;
3894 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3895 break;
3896 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3897 PM8001_MSG_DBG(pm8001_ha,
3898 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3899 pm8001_hw_event_ack_req(pm8001_ha, 0,
3900 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3901 port_id, phy_id, 0, 0);
3902 sas_phy_disconnected(sas_phy);
3903 phy->phy_attached = 0;
3904 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3905 break;
3906 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3907 PM8001_MSG_DBG(pm8001_ha,
3908 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3909 pm8001_hw_event_ack_req(pm8001_ha, 0,
3910 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3911 port_id, phy_id, 0, 0);
3912 sas_phy_disconnected(sas_phy);
3913 phy->phy_attached = 0;
3914 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3915 break;
3916 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3917 PM8001_MSG_DBG(pm8001_ha,
3918 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3919 pm8001_hw_event_ack_req(pm8001_ha, 0,
3920 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3921 port_id, phy_id, 0, 0);
3922 sas_phy_disconnected(sas_phy);
3923 phy->phy_attached = 0;
3924 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3925 break;
3926 case HW_EVENT_MALFUNCTION:
3927 PM8001_MSG_DBG(pm8001_ha,
3928 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3929 break;
3930 case HW_EVENT_BROADCAST_SES:
3931 PM8001_MSG_DBG(pm8001_ha,
3932 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3933 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3934 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3935 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3936 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3937 break;
3938 case HW_EVENT_INBOUND_CRC_ERROR:
3939 PM8001_MSG_DBG(pm8001_ha,
3940 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3941 pm8001_hw_event_ack_req(pm8001_ha, 0,
3942 HW_EVENT_INBOUND_CRC_ERROR,
3943 port_id, phy_id, 0, 0);
3944 break;
3945 case HW_EVENT_HARD_RESET_RECEIVED:
3946 PM8001_MSG_DBG(pm8001_ha,
3947 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3948 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3949 break;
3950 case HW_EVENT_ID_FRAME_TIMEOUT:
3951 PM8001_MSG_DBG(pm8001_ha,
3952 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3953 sas_phy_disconnected(sas_phy);
3954 phy->phy_attached = 0;
3955 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3956 break;
3957 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3958 PM8001_MSG_DBG(pm8001_ha,
3959 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3960 pm8001_hw_event_ack_req(pm8001_ha, 0,
3961 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3962 port_id, phy_id, 0, 0);
3963 sas_phy_disconnected(sas_phy);
3964 phy->phy_attached = 0;
3965 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3966 break;
3967 case HW_EVENT_PORT_RESET_TIMER_TMO:
3968 PM8001_MSG_DBG(pm8001_ha,
3969 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3970 sas_phy_disconnected(sas_phy);
3971 phy->phy_attached = 0;
3972 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3973 break;
3974 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3975 PM8001_MSG_DBG(pm8001_ha,
3976 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3977 sas_phy_disconnected(sas_phy);
3978 phy->phy_attached = 0;
3979 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3980 break;
3981 case HW_EVENT_PORT_RECOVER:
3982 PM8001_MSG_DBG(pm8001_ha,
3983 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3984 break;
3985 case HW_EVENT_PORT_RESET_COMPLETE:
3986 PM8001_MSG_DBG(pm8001_ha,
3987 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3988 break;
3989 case EVENT_BROADCAST_ASYNCH_EVENT:
3990 PM8001_MSG_DBG(pm8001_ha,
3991 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3992 break;
3993 default:
3994 PM8001_MSG_DBG(pm8001_ha,
3995 pm8001_printk("Unknown event type = %x\n", eventType));
3996 break;
3997 }
3998 return 0;
3999}
4000
4001/**
4002 * process_one_iomb - process one outbound Queue memory block
4003 * @pm8001_ha: our hba card information
4004 * @piomb: IO message buffer
4005 */
4006static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
4007{
4008 __le32 pHeader = *(__le32 *)piomb;
4009 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
4010
4011 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
4012
4013 switch (opc) {
4014 case OPC_OUB_ECHO:
4015 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
4016 break;
4017 case OPC_OUB_HW_EVENT:
4018 PM8001_MSG_DBG(pm8001_ha,
4019 pm8001_printk("OPC_OUB_HW_EVENT\n"));
4020 mpi_hw_event(pm8001_ha, piomb);
4021 break;
4022 case OPC_OUB_SSP_COMP:
4023 PM8001_MSG_DBG(pm8001_ha,
4024 pm8001_printk("OPC_OUB_SSP_COMP\n"));
4025 mpi_ssp_completion(pm8001_ha, piomb);
4026 break;
4027 case OPC_OUB_SMP_COMP:
4028 PM8001_MSG_DBG(pm8001_ha,
4029 pm8001_printk("OPC_OUB_SMP_COMP\n"));
4030 mpi_smp_completion(pm8001_ha, piomb);
4031 break;
4032 case OPC_OUB_LOCAL_PHY_CNTRL:
4033 PM8001_MSG_DBG(pm8001_ha,
4034 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4035 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4036 break;
4037 case OPC_OUB_DEV_REGIST:
4038 PM8001_MSG_DBG(pm8001_ha,
4039 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4040 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4041 break;
4042 case OPC_OUB_DEREG_DEV:
4043 PM8001_MSG_DBG(pm8001_ha,
4044 pm8001_printk("unregister the device\n"));
4045 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4046 break;
4047 case OPC_OUB_GET_DEV_HANDLE:
4048 PM8001_MSG_DBG(pm8001_ha,
4049 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4050 break;
4051 case OPC_OUB_SATA_COMP:
4052 PM8001_MSG_DBG(pm8001_ha,
4053 pm8001_printk("OPC_OUB_SATA_COMP\n"));
4054 mpi_sata_completion(pm8001_ha, piomb);
4055 break;
4056 case OPC_OUB_SATA_EVENT:
4057 PM8001_MSG_DBG(pm8001_ha,
4058 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4059 mpi_sata_event(pm8001_ha, piomb);
4060 break;
4061 case OPC_OUB_SSP_EVENT:
4062 PM8001_MSG_DBG(pm8001_ha,
4063 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4064 mpi_ssp_event(pm8001_ha, piomb);
4065 break;
4066 case OPC_OUB_DEV_HANDLE_ARRIV:
4067 PM8001_MSG_DBG(pm8001_ha,
4068 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4069 /*This is for target*/
4070 break;
4071 case OPC_OUB_SSP_RECV_EVENT:
4072 PM8001_MSG_DBG(pm8001_ha,
4073 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4074 /*This is for target*/
4075 break;
4076 case OPC_OUB_DEV_INFO:
4077 PM8001_MSG_DBG(pm8001_ha,
4078 pm8001_printk("OPC_OUB_DEV_INFO\n"));
4079 break;
4080 case OPC_OUB_FW_FLASH_UPDATE:
4081 PM8001_MSG_DBG(pm8001_ha,
4082 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4083 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4084 break;
4085 case OPC_OUB_GPIO_RESPONSE:
4086 PM8001_MSG_DBG(pm8001_ha,
4087 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4088 break;
4089 case OPC_OUB_GPIO_EVENT:
4090 PM8001_MSG_DBG(pm8001_ha,
4091 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4092 break;
4093 case OPC_OUB_GENERAL_EVENT:
4094 PM8001_MSG_DBG(pm8001_ha,
4095 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4096 pm8001_mpi_general_event(pm8001_ha, piomb);
4097 break;
4098 case OPC_OUB_SSP_ABORT_RSP:
4099 PM8001_MSG_DBG(pm8001_ha,
4100 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4101 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4102 break;
4103 case OPC_OUB_SATA_ABORT_RSP:
4104 PM8001_MSG_DBG(pm8001_ha,
4105 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4106 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4107 break;
4108 case OPC_OUB_SAS_DIAG_MODE_START_END:
4109 PM8001_MSG_DBG(pm8001_ha,
4110 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4111 break;
4112 case OPC_OUB_SAS_DIAG_EXECUTE:
4113 PM8001_MSG_DBG(pm8001_ha,
4114 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4115 break;
4116 case OPC_OUB_GET_TIME_STAMP:
4117 PM8001_MSG_DBG(pm8001_ha,
4118 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4119 break;
4120 case OPC_OUB_SAS_HW_EVENT_ACK:
4121 PM8001_MSG_DBG(pm8001_ha,
4122 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4123 break;
4124 case OPC_OUB_PORT_CONTROL:
4125 PM8001_MSG_DBG(pm8001_ha,
4126 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4127 break;
4128 case OPC_OUB_SMP_ABORT_RSP:
4129 PM8001_MSG_DBG(pm8001_ha,
4130 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4131 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4132 break;
4133 case OPC_OUB_GET_NVMD_DATA:
4134 PM8001_MSG_DBG(pm8001_ha,
4135 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4136 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4137 break;
4138 case OPC_OUB_SET_NVMD_DATA:
4139 PM8001_MSG_DBG(pm8001_ha,
4140 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4141 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4142 break;
4143 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4144 PM8001_MSG_DBG(pm8001_ha,
4145 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4146 break;
4147 case OPC_OUB_SET_DEVICE_STATE:
4148 PM8001_MSG_DBG(pm8001_ha,
4149 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4150 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4151 break;
4152 case OPC_OUB_GET_DEVICE_STATE:
4153 PM8001_MSG_DBG(pm8001_ha,
4154 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4155 break;
4156 case OPC_OUB_SET_DEV_INFO:
4157 PM8001_MSG_DBG(pm8001_ha,
4158 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4159 break;
4160 case OPC_OUB_SAS_RE_INITIALIZE:
4161 PM8001_MSG_DBG(pm8001_ha,
4162 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4163 break;
4164 default:
4165 PM8001_MSG_DBG(pm8001_ha,
4166 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4167 opc));
4168 break;
4169 }
4170}
4171
4172static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4173{
4174 struct outbound_queue_table *circularQ;
4175 void *pMsg1 = NULL;
4176 u8 bc;
4177 u32 ret = MPI_IO_STATUS_FAIL;
4178 unsigned long flags;
4179
4180 spin_lock_irqsave(&pm8001_ha->lock, flags);
4181 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4182 do {
4183 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4184 if (MPI_IO_STATUS_SUCCESS == ret) {
4185 /* process the outbound message */
4186 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4187 /* free the message from the outbound circular buffer */
4188 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4189 circularQ, bc);
4190 }
4191 if (MPI_IO_STATUS_BUSY == ret) {
4192 /* Update the producer index from SPC */
4193 circularQ->producer_index =
4194 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4195 if (le32_to_cpu(circularQ->producer_index) ==
4196 circularQ->consumer_idx)
4197 /* OQ is empty */
4198 break;
4199 }
4200 } while (1);
4201 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4202 return ret;
4203}
4204
4205/* DMA_... to our direction translation. */
4206static const u8 data_dir_flags[] = {
4207 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4208 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4209 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4210 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4211};
4212void
4213pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4214{
4215 int i;
4216 struct scatterlist *sg;
4217 struct pm8001_prd *buf_prd = prd;
4218
4219 for_each_sg(scatter, sg, nr, i) {
4220 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4221 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4222 buf_prd->im_len.e = 0;
4223 buf_prd++;
4224 }
4225}
4226
4227static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4228{
4229 psmp_cmd->tag = hTag;
4230 psmp_cmd->device_id = cpu_to_le32(deviceID);
4231 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4232}
4233
4234/**
4235 * pm8001_chip_smp_req - send a SMP task to FW
4236 * @pm8001_ha: our hba card information.
4237 * @ccb: the ccb information this request used.
4238 */
4239static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4240 struct pm8001_ccb_info *ccb)
4241{
4242 int elem, rc;
4243 struct sas_task *task = ccb->task;
4244 struct domain_device *dev = task->dev;
4245 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4246 struct scatterlist *sg_req, *sg_resp;
4247 u32 req_len, resp_len;
4248 struct smp_req smp_cmd;
4249 u32 opc;
4250 struct inbound_queue_table *circularQ;
4251
4252 memset(&smp_cmd, 0, sizeof(smp_cmd));
4253 /*
4254 * DMA-map SMP request, response buffers
4255 */
4256 sg_req = &task->smp_task.smp_req;
4257 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4258 if (!elem)
4259 return -ENOMEM;
4260 req_len = sg_dma_len(sg_req);
4261
4262 sg_resp = &task->smp_task.smp_resp;
4263 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4264 if (!elem) {
4265 rc = -ENOMEM;
4266 goto err_out;
4267 }
4268 resp_len = sg_dma_len(sg_resp);
4269 /* must be in dwords */
4270 if ((req_len & 0x3) || (resp_len & 0x3)) {
4271 rc = -EINVAL;
4272 goto err_out_2;
4273 }
4274
4275 opc = OPC_INB_SMP_REQUEST;
4276 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4277 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4278 smp_cmd.long_smp_req.long_req_addr =
4279 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4280 smp_cmd.long_smp_req.long_req_size =
4281 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4282 smp_cmd.long_smp_req.long_resp_addr =
4283 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4284 smp_cmd.long_smp_req.long_resp_size =
4285 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4286 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4287 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4288 (u32 *)&smp_cmd, 0);
4289 if (rc)
4290 goto err_out_2;
4291
4292 return 0;
4293
4294err_out_2:
4295 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4296 DMA_FROM_DEVICE);
4297err_out:
4298 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4299 DMA_TO_DEVICE);
4300 return rc;
4301}
4302
4303/**
4304 * pm8001_chip_ssp_io_req - send a SSP task to FW
4305 * @pm8001_ha: our hba card information.
4306 * @ccb: the ccb information this request used.
4307 */
4308static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4309 struct pm8001_ccb_info *ccb)
4310{
4311 struct sas_task *task = ccb->task;
4312 struct domain_device *dev = task->dev;
4313 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4314 struct ssp_ini_io_start_req ssp_cmd;
4315 u32 tag = ccb->ccb_tag;
4316 int ret;
4317 u64 phys_addr;
4318 struct inbound_queue_table *circularQ;
4319 u32 opc = OPC_INB_SSPINIIOSTART;
4320 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4321 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4322 ssp_cmd.dir_m_tlr =
4323 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4324 SAS 1.1 compatible TLR*/
4325 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4326 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4327 ssp_cmd.tag = cpu_to_le32(tag);
4328 if (task->ssp_task.enable_first_burst)
4329 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4330 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4331 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4332 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4333 task->ssp_task.cmd->cmd_len);
4334 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4335
4336 /* fill in PRD (scatter/gather) table, if any */
4337 if (task->num_scatter > 1) {
4338 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4339 phys_addr = ccb->ccb_dma_handle +
4340 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4341 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4342 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4343 ssp_cmd.esgl = cpu_to_le32(1<<31);
4344 } else if (task->num_scatter == 1) {
4345 u64 dma_addr = sg_dma_address(task->scatter);
4346 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4347 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4348 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4349 ssp_cmd.esgl = 0;
4350 } else if (task->num_scatter == 0) {
4351 ssp_cmd.addr_low = 0;
4352 ssp_cmd.addr_high = 0;
4353 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4354 ssp_cmd.esgl = 0;
4355 }
4356 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4357 return ret;
4358}
4359
4360static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4361 struct pm8001_ccb_info *ccb)
4362{
4363 struct sas_task *task = ccb->task;
4364 struct domain_device *dev = task->dev;
4365 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4366 u32 tag = ccb->ccb_tag;
4367 int ret;
4368 struct sata_start_req sata_cmd;
4369 u32 hdr_tag, ncg_tag = 0;
4370 u64 phys_addr;
4371 u32 ATAP = 0x0;
4372 u32 dir;
4373 struct inbound_queue_table *circularQ;
4374 unsigned long flags;
4375 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4376 memset(&sata_cmd, 0, sizeof(sata_cmd));
4377 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4378 if (task->data_dir == DMA_NONE) {
4379 ATAP = 0x04; /* no data*/
4380 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4381 } else if (likely(!task->ata_task.device_control_reg_update)) {
4382 if (task->ata_task.dma_xfer) {
4383 ATAP = 0x06; /* DMA */
4384 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4385 } else {
4386 ATAP = 0x05; /* PIO*/
4387 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4388 }
4389 if (task->ata_task.use_ncq &&
4390 dev->sata_dev.class != ATA_DEV_ATAPI) {
4391 ATAP = 0x07; /* FPDMA */
4392 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4393 }
4394 }
4395 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4396 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4397 ncg_tag = hdr_tag;
4398 }
4399 dir = data_dir_flags[task->data_dir] << 8;
4400 sata_cmd.tag = cpu_to_le32(tag);
4401 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4402 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4403 sata_cmd.ncqtag_atap_dir_m =
4404 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4405 sata_cmd.sata_fis = task->ata_task.fis;
4406 if (likely(!task->ata_task.device_control_reg_update))
4407 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4408 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4409 /* fill in PRD (scatter/gather) table, if any */
4410 if (task->num_scatter > 1) {
4411 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4412 phys_addr = ccb->ccb_dma_handle +
4413 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4414 sata_cmd.addr_low = lower_32_bits(phys_addr);
4415 sata_cmd.addr_high = upper_32_bits(phys_addr);
4416 sata_cmd.esgl = cpu_to_le32(1 << 31);
4417 } else if (task->num_scatter == 1) {
4418 u64 dma_addr = sg_dma_address(task->scatter);
4419 sata_cmd.addr_low = lower_32_bits(dma_addr);
4420 sata_cmd.addr_high = upper_32_bits(dma_addr);
4421 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4422 sata_cmd.esgl = 0;
4423 } else if (task->num_scatter == 0) {
4424 sata_cmd.addr_low = 0;
4425 sata_cmd.addr_high = 0;
4426 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4427 sata_cmd.esgl = 0;
4428 }
4429
4430 /* Check for read log for failed drive and return */
4431 if (sata_cmd.sata_fis.command == 0x2f) {
4432 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4433 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4434 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4435 struct task_status_struct *ts;
4436
4437 pm8001_ha_dev->id &= 0xDFFFFFFF;
4438 ts = &task->task_status;
4439
4440 spin_lock_irqsave(&task->task_state_lock, flags);
4441 ts->resp = SAS_TASK_COMPLETE;
4442 ts->stat = SAM_STAT_GOOD;
4443 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4444 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4445 task->task_state_flags |= SAS_TASK_STATE_DONE;
4446 if (unlikely((task->task_state_flags &
4447 SAS_TASK_STATE_ABORTED))) {
4448 spin_unlock_irqrestore(&task->task_state_lock,
4449 flags);
4450 PM8001_FAIL_DBG(pm8001_ha,
4451 pm8001_printk("task 0x%p resp 0x%x "
4452 " stat 0x%x but aborted by upper layer "
4453 "\n", task, ts->resp, ts->stat));
4454 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4455 } else {
4456 spin_unlock_irqrestore(&task->task_state_lock,
4457 flags);
4458 pm8001_ccb_task_free_done(pm8001_ha, task,
4459 ccb, tag);
4460 return 0;
4461 }
4462 }
4463 }
4464
4465 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4466 return ret;
4467}
4468
4469/**
4470 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4471 * @pm8001_ha: our hba card information.
4472 * @num: the inbound queue number
4473 * @phy_id: the phy id which we wanted to start up.
4474 */
4475static int
4476pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4477{
4478 struct phy_start_req payload;
4479 struct inbound_queue_table *circularQ;
4480 int ret;
4481 u32 tag = 0x01;
4482 u32 opcode = OPC_INB_PHYSTART;
4483 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4484 memset(&payload, 0, sizeof(payload));
4485 payload.tag = cpu_to_le32(tag);
4486 /*
4487 ** [0:7] PHY Identifier
4488 ** [8:11] link rate 1.5G, 3G, 6G
4489 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4490 ** [14] 0b disable spin up hold; 1b enable spin up hold
4491 */
4492 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4493 LINKMODE_AUTO | LINKRATE_15 |
4494 LINKRATE_30 | LINKRATE_60 | phy_id);
4495 payload.sas_identify.dev_type = SAS_END_DEVICE;
4496 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4497 memcpy(payload.sas_identify.sas_addr,
4498 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4499 payload.sas_identify.phy_id = phy_id;
4500 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4501 return ret;
4502}
4503
4504/**
4505 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4506 * @pm8001_ha: our hba card information.
4507 * @num: the inbound queue number
4508 * @phy_id: the phy id which we wanted to start up.
4509 */
4510static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4511 u8 phy_id)
4512{
4513 struct phy_stop_req payload;
4514 struct inbound_queue_table *circularQ;
4515 int ret;
4516 u32 tag = 0x01;
4517 u32 opcode = OPC_INB_PHYSTOP;
4518 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4519 memset(&payload, 0, sizeof(payload));
4520 payload.tag = cpu_to_le32(tag);
4521 payload.phy_id = cpu_to_le32(phy_id);
4522 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4523 return ret;
4524}
4525
4526/**
4527 * see comments on pm8001_mpi_reg_resp.
4528 */
4529static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4530 struct pm8001_device *pm8001_dev, u32 flag)
4531{
4532 struct reg_dev_req payload;
4533 u32 opc;
4534 u32 stp_sspsmp_sata = 0x4;
4535 struct inbound_queue_table *circularQ;
4536 u32 linkrate, phy_id;
4537 int rc, tag = 0xdeadbeef;
4538 struct pm8001_ccb_info *ccb;
4539 u8 retryFlag = 0x1;
4540 u16 firstBurstSize = 0;
4541 u16 ITNT = 2000;
4542 struct domain_device *dev = pm8001_dev->sas_device;
4543 struct domain_device *parent_dev = dev->parent;
4544 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4545
4546 memset(&payload, 0, sizeof(payload));
4547 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4548 if (rc)
4549 return rc;
4550 ccb = &pm8001_ha->ccb_info[tag];
4551 ccb->device = pm8001_dev;
4552 ccb->ccb_tag = tag;
4553 payload.tag = cpu_to_le32(tag);
4554 if (flag == 1)
4555 stp_sspsmp_sata = 0x02; /*direct attached sata */
4556 else {
4557 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4558 stp_sspsmp_sata = 0x00; /* stp*/
4559 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4560 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4561 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4562 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4563 }
4564 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4565 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4566 else
4567 phy_id = pm8001_dev->attached_phy;
4568 opc = OPC_INB_REG_DEV;
4569 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4570 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4571 payload.phyid_portid =
4572 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4573 ((phy_id & 0x0F) << 4));
4574 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4575 ((linkrate & 0x0F) * 0x1000000) |
4576 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4577 payload.firstburstsize_ITNexustimeout =
4578 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4579 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4580 SAS_ADDR_SIZE);
4581 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4582 return rc;
4583}
4584
4585/**
4586 * see comments on pm8001_mpi_reg_resp.
4587 */
4588int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4589 u32 device_id)
4590{
4591 struct dereg_dev_req payload;
4592 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4593 int ret;
4594 struct inbound_queue_table *circularQ;
4595
4596 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4597 memset(&payload, 0, sizeof(payload));
4598 payload.tag = cpu_to_le32(1);
4599 payload.device_id = cpu_to_le32(device_id);
4600 PM8001_MSG_DBG(pm8001_ha,
4601 pm8001_printk("unregister device device_id = %d\n", device_id));
4602 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4603 return ret;
4604}
4605
4606/**
4607 * pm8001_chip_phy_ctl_req - support the local phy operation
4608 * @pm8001_ha: our hba card information.
4609 * @num: the inbound queue number
4610 * @phy_id: the phy id which we wanted to operate
4611 * @phy_op:
4612 */
4613static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4614 u32 phyId, u32 phy_op)
4615{
4616 struct local_phy_ctl_req payload;
4617 struct inbound_queue_table *circularQ;
4618 int ret;
4619 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4620 memset(&payload, 0, sizeof(payload));
4621 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4622 payload.tag = cpu_to_le32(1);
4623 payload.phyop_phyid =
4624 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4625 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4626 return ret;
4627}
4628
4629static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4630{
4631#ifdef PM8001_USE_MSIX
4632 return 1;
4633#else
4634 u32 value;
4635
4636 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4637 if (value)
4638 return 1;
4639 return 0;
4640#endif
4641}
4642
4643/**
4644 * pm8001_chip_isr - PM8001 isr handler.
4645 * @pm8001_ha: our hba card information.
4646 * @irq: irq number.
4647 * @stat: stat.
4648 */
4649static irqreturn_t
4650pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4651{
4652 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4653 process_oq(pm8001_ha, vec);
4654 pm8001_chip_interrupt_enable(pm8001_ha, vec);
4655 return IRQ_HANDLED;
4656}
4657
4658static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4659 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4660{
4661 struct task_abort_req task_abort;
4662 struct inbound_queue_table *circularQ;
4663 int ret;
4664 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4665 memset(&task_abort, 0, sizeof(task_abort));
4666 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4667 task_abort.abort_all = 0;
4668 task_abort.device_id = cpu_to_le32(dev_id);
4669 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4670 task_abort.tag = cpu_to_le32(cmd_tag);
4671 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4672 task_abort.abort_all = cpu_to_le32(1);
4673 task_abort.device_id = cpu_to_le32(dev_id);
4674 task_abort.tag = cpu_to_le32(cmd_tag);
4675 }
4676 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4677 return ret;
4678}
4679
4680/**
4681 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4682 * @task: the task we wanted to aborted.
4683 * @flag: the abort flag.
4684 */
4685int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4686 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4687{
4688 u32 opc, device_id;
4689 int rc = TMF_RESP_FUNC_FAILED;
4690 PM8001_EH_DBG(pm8001_ha,
4691 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4692 cmd_tag, task_tag));
4693 if (pm8001_dev->dev_type == SAS_END_DEVICE)
4694 opc = OPC_INB_SSP_ABORT;
4695 else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4696 opc = OPC_INB_SATA_ABORT;
4697 else
4698 opc = OPC_INB_SMP_ABORT;/* SMP */
4699 device_id = pm8001_dev->device_id;
4700 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4701 task_tag, cmd_tag);
4702 if (rc != TMF_RESP_FUNC_COMPLETE)
4703 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4704 return rc;
4705}
4706
4707/**
4708 * pm8001_chip_ssp_tm_req - built the task management command.
4709 * @pm8001_ha: our hba card information.
4710 * @ccb: the ccb information.
4711 * @tmf: task management function.
4712 */
4713int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4714 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4715{
4716 struct sas_task *task = ccb->task;
4717 struct domain_device *dev = task->dev;
4718 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4719 u32 opc = OPC_INB_SSPINITMSTART;
4720 struct inbound_queue_table *circularQ;
4721 struct ssp_ini_tm_start_req sspTMCmd;
4722 int ret;
4723
4724 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4725 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4726 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4727 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4728 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4729 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4730 if (pm8001_ha->chip_id != chip_8001)
4731 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4732 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4733 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4734 return ret;
4735}
4736
4737int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4738 void *payload)
4739{
4740 u32 opc = OPC_INB_GET_NVMD_DATA;
4741 u32 nvmd_type;
4742 int rc;
4743 u32 tag;
4744 struct pm8001_ccb_info *ccb;
4745 struct inbound_queue_table *circularQ;
4746 struct get_nvm_data_req nvmd_req;
4747 struct fw_control_ex *fw_control_context;
4748 struct pm8001_ioctl_payload *ioctl_payload = payload;
4749
4750 nvmd_type = ioctl_payload->minor_function;
4751 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4752 if (!fw_control_context)
4753 return -ENOMEM;
4754 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4755 fw_control_context->len = ioctl_payload->length;
4756 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4757 memset(&nvmd_req, 0, sizeof(nvmd_req));
4758 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4759 if (rc) {
4760 kfree(fw_control_context);
4761 return rc;
4762 }
4763 ccb = &pm8001_ha->ccb_info[tag];
4764 ccb->ccb_tag = tag;
4765 ccb->fw_control_context = fw_control_context;
4766 nvmd_req.tag = cpu_to_le32(tag);
4767
4768 switch (nvmd_type) {
4769 case TWI_DEVICE: {
4770 u32 twi_addr, twi_page_size;
4771 twi_addr = 0xa8;
4772 twi_page_size = 2;
4773
4774 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4775 twi_page_size << 8 | TWI_DEVICE);
4776 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4777 nvmd_req.resp_addr_hi =
4778 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4779 nvmd_req.resp_addr_lo =
4780 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4781 break;
4782 }
4783 case C_SEEPROM: {
4784 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4785 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4786 nvmd_req.resp_addr_hi =
4787 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4788 nvmd_req.resp_addr_lo =
4789 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4790 break;
4791 }
4792 case VPD_FLASH: {
4793 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4794 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4795 nvmd_req.resp_addr_hi =
4796 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4797 nvmd_req.resp_addr_lo =
4798 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4799 break;
4800 }
4801 case EXPAN_ROM: {
4802 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4803 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4804 nvmd_req.resp_addr_hi =
4805 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4806 nvmd_req.resp_addr_lo =
4807 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4808 break;
4809 }
4810 case IOP_RDUMP: {
4811 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4812 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4813 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4814 nvmd_req.resp_addr_hi =
4815 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4816 nvmd_req.resp_addr_lo =
4817 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4818 break;
4819 }
4820 default:
4821 break;
4822 }
4823 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4824 if (rc) {
4825 kfree(fw_control_context);
4826 pm8001_tag_free(pm8001_ha, tag);
4827 }
4828 return rc;
4829}
4830
4831int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4832 void *payload)
4833{
4834 u32 opc = OPC_INB_SET_NVMD_DATA;
4835 u32 nvmd_type;
4836 int rc;
4837 u32 tag;
4838 struct pm8001_ccb_info *ccb;
4839 struct inbound_queue_table *circularQ;
4840 struct set_nvm_data_req nvmd_req;
4841 struct fw_control_ex *fw_control_context;
4842 struct pm8001_ioctl_payload *ioctl_payload = payload;
4843
4844 nvmd_type = ioctl_payload->minor_function;
4845 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4846 if (!fw_control_context)
4847 return -ENOMEM;
4848 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4849 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4850 &ioctl_payload->func_specific,
4851 ioctl_payload->length);
4852 memset(&nvmd_req, 0, sizeof(nvmd_req));
4853 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4854 if (rc) {
4855 kfree(fw_control_context);
4856 return -EBUSY;
4857 }
4858 ccb = &pm8001_ha->ccb_info[tag];
4859 ccb->fw_control_context = fw_control_context;
4860 ccb->ccb_tag = tag;
4861 nvmd_req.tag = cpu_to_le32(tag);
4862 switch (nvmd_type) {
4863 case TWI_DEVICE: {
4864 u32 twi_addr, twi_page_size;
4865 twi_addr = 0xa8;
4866 twi_page_size = 2;
4867 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4868 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4869 twi_page_size << 8 | TWI_DEVICE);
4870 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4871 nvmd_req.resp_addr_hi =
4872 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4873 nvmd_req.resp_addr_lo =
4874 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4875 break;
4876 }
4877 case C_SEEPROM:
4878 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4879 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4880 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4881 nvmd_req.resp_addr_hi =
4882 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4883 nvmd_req.resp_addr_lo =
4884 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4885 break;
4886 case VPD_FLASH:
4887 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4888 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4889 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4890 nvmd_req.resp_addr_hi =
4891 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4892 nvmd_req.resp_addr_lo =
4893 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4894 break;
4895 case EXPAN_ROM:
4896 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4897 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4898 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4899 nvmd_req.resp_addr_hi =
4900 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4901 nvmd_req.resp_addr_lo =
4902 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4903 break;
4904 default:
4905 break;
4906 }
4907 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4908 if (rc) {
4909 kfree(fw_control_context);
4910 pm8001_tag_free(pm8001_ha, tag);
4911 }
4912 return rc;
4913}
4914
4915/**
4916 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4917 * @pm8001_ha: our hba card information.
4918 * @fw_flash_updata_info: firmware flash update param
4919 */
4920int
4921pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4922 void *fw_flash_updata_info, u32 tag)
4923{
4924 struct fw_flash_Update_req payload;
4925 struct fw_flash_updata_info *info;
4926 struct inbound_queue_table *circularQ;
4927 int ret;
4928 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4929
4930 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4931 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4932 info = fw_flash_updata_info;
4933 payload.tag = cpu_to_le32(tag);
4934 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4935 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4936 payload.total_image_len = cpu_to_le32(info->total_image_len);
4937 payload.len = info->sgl.im_len.len ;
4938 payload.sgl_addr_lo =
4939 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4940 payload.sgl_addr_hi =
4941 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4942 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4943 return ret;
4944}
4945
4946int
4947pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4948 void *payload)
4949{
4950 struct fw_flash_updata_info flash_update_info;
4951 struct fw_control_info *fw_control;
4952 struct fw_control_ex *fw_control_context;
4953 int rc;
4954 u32 tag;
4955 struct pm8001_ccb_info *ccb;
4956 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4957 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4958 struct pm8001_ioctl_payload *ioctl_payload = payload;
4959
4960 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4961 if (!fw_control_context)
4962 return -ENOMEM;
4963 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4964 memcpy(buffer, fw_control->buffer, fw_control->len);
4965 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4966 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4967 flash_update_info.sgl.im_len.e = 0;
4968 flash_update_info.cur_image_offset = fw_control->offset;
4969 flash_update_info.cur_image_len = fw_control->len;
4970 flash_update_info.total_image_len = fw_control->size;
4971 fw_control_context->fw_control = fw_control;
4972 fw_control_context->virtAddr = buffer;
4973 fw_control_context->phys_addr = phys_addr;
4974 fw_control_context->len = fw_control->len;
4975 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4976 if (rc) {
4977 kfree(fw_control_context);
4978 return -EBUSY;
4979 }
4980 ccb = &pm8001_ha->ccb_info[tag];
4981 ccb->fw_control_context = fw_control_context;
4982 ccb->ccb_tag = tag;
4983 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4984 tag);
4985 return rc;
4986}
4987
4988ssize_t
4989pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4990{
4991 u32 value, rem, offset = 0, bar = 0;
4992 u32 index, work_offset, dw_length;
4993 u32 shift_value, gsm_base, gsm_dump_offset;
4994 char *direct_data;
4995 struct Scsi_Host *shost = class_to_shost(cdev);
4996 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4997 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4998
4999 direct_data = buf;
5000 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
5001
5002 /* check max is 1 Mbytes */
5003 if ((length > 0x100000) || (gsm_dump_offset & 3) ||
5004 ((gsm_dump_offset + length) > 0x1000000))
5005 return -EINVAL;
5006
5007 if (pm8001_ha->chip_id == chip_8001)
5008 bar = 2;
5009 else
5010 bar = 1;
5011
5012 work_offset = gsm_dump_offset & 0xFFFF0000;
5013 offset = gsm_dump_offset & 0x0000FFFF;
5014 gsm_dump_offset = work_offset;
5015 /* adjust length to dword boundary */
5016 rem = length & 3;
5017 dw_length = length >> 2;
5018
5019 for (index = 0; index < dw_length; index++) {
5020 if ((work_offset + offset) & 0xFFFF0000) {
5021 if (pm8001_ha->chip_id == chip_8001)
5022 shift_value = ((gsm_dump_offset + offset) &
5023 SHIFT_REG_64K_MASK);
5024 else
5025 shift_value = (((gsm_dump_offset + offset) &
5026 SHIFT_REG_64K_MASK) >>
5027 SHIFT_REG_BIT_SHIFT);
5028
5029 if (pm8001_ha->chip_id == chip_8001) {
5030 gsm_base = GSM_BASE;
5031 if (-1 == pm8001_bar4_shift(pm8001_ha,
5032 (gsm_base + shift_value)))
5033 return -EIO;
5034 } else {
5035 gsm_base = 0;
5036 if (-1 == pm80xx_bar4_shift(pm8001_ha,
5037 (gsm_base + shift_value)))
5038 return -EIO;
5039 }
5040 gsm_dump_offset = (gsm_dump_offset + offset) &
5041 0xFFFF0000;
5042 work_offset = 0;
5043 offset = offset & 0x0000FFFF;
5044 }
5045 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5046 0x0000FFFF);
5047 direct_data += sprintf(direct_data, "%08x ", value);
5048 offset += 4;
5049 }
5050 if (rem != 0) {
5051 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5052 0x0000FFFF);
5053 /* xfr for non_dw */
5054 direct_data += sprintf(direct_data, "%08x ", value);
5055 }
5056 /* Shift back to BAR4 original address */
5057 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
5058 return -EIO;
5059 pm8001_ha->fatal_forensic_shift_offset += 1024;
5060
5061 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
5062 pm8001_ha->fatal_forensic_shift_offset = 0;
5063 return direct_data - buf;
5064}
5065
5066int
5067pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
5068 struct pm8001_device *pm8001_dev, u32 state)
5069{
5070 struct set_dev_state_req payload;
5071 struct inbound_queue_table *circularQ;
5072 struct pm8001_ccb_info *ccb;
5073 int rc;
5074 u32 tag;
5075 u32 opc = OPC_INB_SET_DEVICE_STATE;
5076 memset(&payload, 0, sizeof(payload));
5077 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5078 if (rc)
5079 return -1;
5080 ccb = &pm8001_ha->ccb_info[tag];
5081 ccb->ccb_tag = tag;
5082 ccb->device = pm8001_dev;
5083 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5084 payload.tag = cpu_to_le32(tag);
5085 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5086 payload.nds = cpu_to_le32(state);
5087 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5088 return rc;
5089
5090}
5091
5092static int
5093pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5094{
5095 struct sas_re_initialization_req payload;
5096 struct inbound_queue_table *circularQ;
5097 struct pm8001_ccb_info *ccb;
5098 int rc;
5099 u32 tag;
5100 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5101 memset(&payload, 0, sizeof(payload));
5102 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5103 if (rc)
5104 return -ENOMEM;
5105 ccb = &pm8001_ha->ccb_info[tag];
5106 ccb->ccb_tag = tag;
5107 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5108 payload.tag = cpu_to_le32(tag);
5109 payload.SSAHOLT = cpu_to_le32(0xd << 25);
5110 payload.sata_hol_tmo = cpu_to_le32(80);
5111 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5112 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5113 if (rc)
5114 pm8001_tag_free(pm8001_ha, tag);
5115 return rc;
5116
5117}
5118
5119const struct pm8001_dispatch pm8001_8001_dispatch = {
5120 .name = "pmc8001",
5121 .chip_init = pm8001_chip_init,
5122 .chip_soft_rst = pm8001_chip_soft_rst,
5123 .chip_rst = pm8001_hw_chip_rst,
5124 .chip_iounmap = pm8001_chip_iounmap,
5125 .isr = pm8001_chip_isr,
5126 .is_our_interrupt = pm8001_chip_is_our_interrupt,
5127 .isr_process_oq = process_oq,
5128 .interrupt_enable = pm8001_chip_interrupt_enable,
5129 .interrupt_disable = pm8001_chip_interrupt_disable,
5130 .make_prd = pm8001_chip_make_sg,
5131 .smp_req = pm8001_chip_smp_req,
5132 .ssp_io_req = pm8001_chip_ssp_io_req,
5133 .sata_req = pm8001_chip_sata_req,
5134 .phy_start_req = pm8001_chip_phy_start_req,
5135 .phy_stop_req = pm8001_chip_phy_stop_req,
5136 .reg_dev_req = pm8001_chip_reg_dev_req,
5137 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5138 .phy_ctl_req = pm8001_chip_phy_ctl_req,
5139 .task_abort = pm8001_chip_abort_task,
5140 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5141 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5142 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5143 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5144 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5145 .sas_re_init_req = pm8001_chip_sas_re_initialization,
5146};