marvell/linux/drivers/soc/asr/geu/asr-geu.h

#ifndef _ASR_GEU_H
#define _ASR_GEU_H

#include <crypto/aes.h>
#include <linux/crypto.h>
#include <crypto/algapi.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/miscdevice.h>

#include "asr-aes.h"

/*
 *	THE REGISTER DEFINES
 */
/* Generic regiseters */
#define GEU_STATUS							(0x0000)
#define GEU_CONFIG							(0x0004)
#define GEU_FUSE_PROG_VAL1					(0x0038)

/* AES related registers */
#define GEU_INIT_KEY(x)						(0x08 + (x << 2))
#define GEU_IN_DATA(x)						(0x28 + (x << 2))
#define GEU_INIT_IV(x)						(0x38 + (x << 2))
#define GEU_OUT_DATA(x)						(0x58 + (x << 2))

#if !defined(CONFIG_CPU_ASR1901)
/* Fuse related registers */
#define GEU_FUSE_STATUS						(0x0484)
#define GEU_FUSE_VAL_APCFG1					(0x0404)
#define GEU_FUSE_VAL_APCFG2					(0x0408)
#define GEU_FUSE_VAL_APCFG3					(0x040C)
#define GEU_FUSE_BANK0_192TO207				(0x041C)
#define BLOCK0_RESERVED_1					(0x0420)
#define GEU_FUSE_VAL_OEM_HASH_KEY			(0x0444)
#define GEU_FUSE_VAL_OEM_UID_H				(0x048C)
#define GEU_FUSE_VAL_OEM_UID_L				(0x04A8)
#define GEU_FUSE_VAL_OEM_UID_H_LAPW			(0x041C)
#define GEU_FUSE_VAL_OEM_UID_L_LAPW			(0x0420)

/* GEU_CONFIG */
#define GEU_FUSE_SOFTWARE_RESET				(1 << 22)
/* GEU_FUSE_STATUS */
#define GEU_FUSE_BURN_DONE					(1 << 8)
#define GEU_FUSE_READY						(1 << 9)
#else
/* 1901/1906 registers */
#define GEU_FUSE_STATUS						(0x0184)
#define GEU_KSTR_BANK6_LCS					(0x0168)
#define GEU_FUSE_VAL_OEM_HASH_KEY			(0x0144)
#define GEU_FUSE_VAL_APCFG1					(0x0104)
#define GEU_FUSE_VAL_APCFG2					(0x0108)
#define GEU_FUSE_VAL_APCFG3					(0x010C)
#define GEU_FUSE_VAL_OEM_UID_L				(0x0298)
#define GEU_FUSE_VAL_OEM_UID_H				(0x029C)

#define GEU_KSTR_LCS_CM_BASE				(0)
#define GEU_KSTR_LCS_DM_BASE				(3)
#define GEU_KSTR_LCS_SP_BASE				(6)
#define GEU_KSTR_LCS_RMA_BASE				(9)
#define GEU_KSTR_LCS_MASK					(0x7)

/* GEU_CONFIG */
#define GEU_FUSE_SOFTWARE_RESET				(1 << 22)
/* GEU_FUSE_STATUS */
#define GEU_FUSE_BURN_DONE					(1 << 0)
#define GEU_FUSE_READY						(1 << 1)
#endif

/*  HWRNG related registers*/
#if defined(CONFIG_CPU_ASR1901)
#define GEU_RNG_CTRL		(0x10C0)
#define GEU_RNG_GEN			(0x10C4)
#define GEU_SQU_RNG_CTRL	(0x1044)
#define GEU_RNG_EN			(3 << 0)
#define RNG_FIFO_CLR		(1 << 30)
#define RNG_VALID			(1 << 31)
#else
#define GEU_RNG_GEN			(0x488)
#define GEU_RNG_SEED_LO		(0x038)
#define GEU_RNG_SEED_HI		(0x03c)
#define GEU_RNG_CTRL		(0x3A8)
#define GEU_RNG_EN			(1 << 24)
#endif

#if defined(CONFIG_CPU_ASR1903)
#define ASR1903_RNG_SEED        (0xD4282C00+0x190)
#endif


/* 1826 specific */
#define GEU_REGULATOR_CNT					(0x03A8)
#define GEU_SCLK_DIV_CNTR					(0x03B0)
#define GEU_SECURITY_CONFIG					(0x0490)

/* GEU status */
#define GEU_STATUS_DATA_ISR				(1 << 9)
#define GEU_STATUS_DATAO_READY			(1 << 3)
#define GEU_STATUS_ROUND_KEY_READY		(1 << 2)
#define GEU_STATUS_DATA_ENCDEC_ENA		(1 << 1)
#define	GEU_STATUS_ROUND_KEY_START		(1 << 0)

/* GEU config*/
#define GEU_CFG_DMA_MODE_EN				(1 << 31)
#define GEU_CFG_CBC_ECB					(1 << 29)
#define GEU_CFG_PWR_BYP					(1 << 28)
#define GEU_CFG_WRITE_IV				(1 << 24)
#define GEU_CFG_ENA_RKEK				(1 << 13)
#define GEU_CFG_DATARSR					(1 << 11)
#define GEU_CFG_DATA_IMR				(1 << 10)
#define GEU_CFG_ENC_DEC					(1 << 3)
#define GEU_CFG_OCB_BYP					(1 << 2)
#define GEU_CFG_KEYSIZE_MASK			(3 << 0)
#define GEU_CFG_KEYSIZE_128				(1 << 0)
#define GEU_CFG_KEYSIZE_192				(2 << 0)
#define GEU_CFG_KEYSIZE_256				(3 << 0)

/* ASR1803/1806/1828/1903 */
#define GEU_SECURE_KEY_ACCESS_DISABLED	(1 << 29)

#define SIZE_IN_WORDS(x)	((x) >> 2)

#define ASR_OEM_KEY_SHA160_SIZE		20
#define ASR_OEM_KEY_SHA224_SIZE		28
#define ASR_OEM_KEY_SHA256_SIZE		32

struct asr_geu_dev;
struct asr_geu_fuse;

struct asr_geu_rng {
	struct device		*dev;
	void __iomem		*io_base;
#ifdef CONFIG_CPU_ASR1903
	void __iomem		*seed_base;
#endif
	struct hwrng *hwrng;
	unsigned int rn_saved;
};

struct asr_geu_fuse { 
	struct device		*dev;
	void __iomem		*io_base;
	struct miscdevice fuse_misc;
	struct asr_geu_dev *geu_dd;
};

struct asr_geu_ops {
	int (*dev_get)(struct asr_geu_dev *);
	int (*dev_put)(struct asr_geu_dev *);
};

struct asr_geu_dev {
	unsigned long		phys_base;
	void __iomem		*io_base;
	struct mutex		geu_lock;
	struct device		*dev;

	struct clk		*geu_clk;
	int			clk_synced;
	refcount_t	refcount;

	int			irq;

	struct asr_geu_rng asr_rng;
	struct asr_geu_fuse asr_fuse;
	struct asr_geu_aes asr_aes;

	struct asr_geu_ops	*geu_ops;
};

int asr_geu_rng_register(struct asr_geu_dev *geu_dd);
int asr_geu_rng_unregister(struct asr_geu_dev *geu_dd);

int asr_geu_fuse_register(struct asr_geu_dev *geu_dd);
int asr_geu_fuse_unregister(struct asr_geu_dev *geu_dd);

int asr_geu_aes_register(struct asr_geu_dev *geu_dd);
int asr_geu_aes_unregister(struct asr_geu_dev *geu_dd);

#endif