b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Freescale SPI controller driver. |
| 4 | * |
| 5 | * Maintainer: Kumar Gala |
| 6 | * |
| 7 | * Copyright (C) 2006 Polycom, Inc. |
| 8 | * Copyright 2010 Freescale Semiconductor, Inc. |
| 9 | * |
| 10 | * CPM SPI and QE buffer descriptors mode support: |
| 11 | * Copyright (c) 2009 MontaVista Software, Inc. |
| 12 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> |
| 13 | * |
| 14 | * GRLIB support: |
| 15 | * Copyright (c) 2012 Aeroflex Gaisler AB. |
| 16 | * Author: Andreas Larsson <andreas@gaisler.com> |
| 17 | */ |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/dma-mapping.h> |
| 20 | #include <linux/fsl_devices.h> |
| 21 | #include <linux/gpio/consumer.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/irq.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/mm.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/mutex.h> |
| 28 | #include <linux/of.h> |
| 29 | #include <linux/of_address.h> |
| 30 | #include <linux/of_irq.h> |
| 31 | #include <linux/of_platform.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/spi/spi.h> |
| 34 | #include <linux/spi/spi_bitbang.h> |
| 35 | #include <linux/types.h> |
| 36 | |
| 37 | #ifdef CONFIG_FSL_SOC |
| 38 | #include <sysdev/fsl_soc.h> |
| 39 | #endif |
| 40 | |
| 41 | /* Specific to the MPC8306/MPC8309 */ |
| 42 | #define IMMR_SPI_CS_OFFSET 0x14c |
| 43 | #define SPI_BOOT_SEL_BIT 0x80000000 |
| 44 | |
| 45 | #include "spi-fsl-lib.h" |
| 46 | #include "spi-fsl-cpm.h" |
| 47 | #include "spi-fsl-spi.h" |
| 48 | |
| 49 | #define TYPE_FSL 0 |
| 50 | #define TYPE_GRLIB 1 |
| 51 | |
| 52 | struct fsl_spi_match_data { |
| 53 | int type; |
| 54 | }; |
| 55 | |
| 56 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { |
| 57 | .type = TYPE_FSL, |
| 58 | }; |
| 59 | |
| 60 | static struct fsl_spi_match_data of_fsl_spi_grlib_config = { |
| 61 | .type = TYPE_GRLIB, |
| 62 | }; |
| 63 | |
| 64 | static const struct of_device_id of_fsl_spi_match[] = { |
| 65 | { |
| 66 | .compatible = "fsl,spi", |
| 67 | .data = &of_fsl_spi_fsl_config, |
| 68 | }, |
| 69 | { |
| 70 | .compatible = "aeroflexgaisler,spictrl", |
| 71 | .data = &of_fsl_spi_grlib_config, |
| 72 | }, |
| 73 | {} |
| 74 | }; |
| 75 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); |
| 76 | |
| 77 | static int fsl_spi_get_type(struct device *dev) |
| 78 | { |
| 79 | const struct of_device_id *match; |
| 80 | |
| 81 | if (dev->of_node) { |
| 82 | match = of_match_node(of_fsl_spi_match, dev->of_node); |
| 83 | if (match && match->data) |
| 84 | return ((struct fsl_spi_match_data *)match->data)->type; |
| 85 | } |
| 86 | return TYPE_FSL; |
| 87 | } |
| 88 | |
| 89 | static void fsl_spi_change_mode(struct spi_device *spi) |
| 90 | { |
| 91 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); |
| 92 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
| 93 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
| 94 | __be32 __iomem *mode = ®_base->mode; |
| 95 | unsigned long flags; |
| 96 | |
| 97 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) |
| 98 | return; |
| 99 | |
| 100 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ |
| 101 | local_irq_save(flags); |
| 102 | |
| 103 | /* Turn off SPI unit prior changing mode */ |
| 104 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); |
| 105 | |
| 106 | /* When in CPM mode, we need to reinit tx and rx. */ |
| 107 | if (mspi->flags & SPI_CPM_MODE) { |
| 108 | fsl_spi_cpm_reinit_txrx(mspi); |
| 109 | } |
| 110 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
| 111 | local_irq_restore(flags); |
| 112 | } |
| 113 | |
| 114 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
| 115 | { |
| 116 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
| 117 | struct fsl_spi_platform_data *pdata; |
| 118 | bool pol = spi->mode & SPI_CS_HIGH; |
| 119 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
| 120 | |
| 121 | pdata = spi->dev.parent->parent->platform_data; |
| 122 | |
| 123 | if (value == BITBANG_CS_INACTIVE) { |
| 124 | if (pdata->cs_control) |
| 125 | pdata->cs_control(spi, !pol); |
| 126 | } |
| 127 | |
| 128 | if (value == BITBANG_CS_ACTIVE) { |
| 129 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
| 130 | mpc8xxx_spi->tx_shift = cs->tx_shift; |
| 131 | mpc8xxx_spi->get_rx = cs->get_rx; |
| 132 | mpc8xxx_spi->get_tx = cs->get_tx; |
| 133 | |
| 134 | fsl_spi_change_mode(spi); |
| 135 | |
| 136 | if (pdata->cs_control) |
| 137 | pdata->cs_control(spi, pol); |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
| 142 | int bits_per_word, int msb_first) |
| 143 | { |
| 144 | *rx_shift = 0; |
| 145 | *tx_shift = 0; |
| 146 | if (msb_first) { |
| 147 | if (bits_per_word <= 8) { |
| 148 | *rx_shift = 16; |
| 149 | *tx_shift = 24; |
| 150 | } else if (bits_per_word <= 16) { |
| 151 | *rx_shift = 16; |
| 152 | *tx_shift = 16; |
| 153 | } |
| 154 | } else { |
| 155 | if (bits_per_word <= 8) |
| 156 | *rx_shift = 8; |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, |
| 161 | int bits_per_word, int msb_first) |
| 162 | { |
| 163 | *rx_shift = 0; |
| 164 | *tx_shift = 0; |
| 165 | if (bits_per_word <= 16) { |
| 166 | if (msb_first) { |
| 167 | *rx_shift = 16; /* LSB in bit 16 */ |
| 168 | *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ |
| 169 | } else { |
| 170 | *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ |
| 171 | } |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
| 176 | struct spi_device *spi, |
| 177 | struct mpc8xxx_spi *mpc8xxx_spi, |
| 178 | int bits_per_word) |
| 179 | { |
| 180 | cs->rx_shift = 0; |
| 181 | cs->tx_shift = 0; |
| 182 | if (bits_per_word <= 8) { |
| 183 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
| 184 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; |
| 185 | } else if (bits_per_word <= 16) { |
| 186 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
| 187 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; |
| 188 | } else if (bits_per_word <= 32) { |
| 189 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
| 190 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; |
| 191 | } else |
| 192 | return -EINVAL; |
| 193 | |
| 194 | if (mpc8xxx_spi->set_shifts) |
| 195 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, |
| 196 | bits_per_word, |
| 197 | !(spi->mode & SPI_LSB_FIRST)); |
| 198 | |
| 199 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
| 200 | mpc8xxx_spi->tx_shift = cs->tx_shift; |
| 201 | mpc8xxx_spi->get_rx = cs->get_rx; |
| 202 | mpc8xxx_spi->get_tx = cs->get_tx; |
| 203 | |
| 204 | return bits_per_word; |
| 205 | } |
| 206 | |
| 207 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
| 208 | struct spi_transfer *t) |
| 209 | { |
| 210 | struct mpc8xxx_spi *mpc8xxx_spi; |
| 211 | int bits_per_word = 0; |
| 212 | u8 pm; |
| 213 | u32 hz = 0; |
| 214 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
| 215 | |
| 216 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
| 217 | |
| 218 | if (t) { |
| 219 | bits_per_word = t->bits_per_word; |
| 220 | hz = t->speed_hz; |
| 221 | } |
| 222 | |
| 223 | /* spi_transfer level calls that work per-word */ |
| 224 | if (!bits_per_word) |
| 225 | bits_per_word = spi->bits_per_word; |
| 226 | |
| 227 | if (!hz) |
| 228 | hz = spi->max_speed_hz; |
| 229 | |
| 230 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) |
| 231 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, |
| 232 | mpc8xxx_spi, |
| 233 | bits_per_word); |
| 234 | |
| 235 | if (bits_per_word < 0) |
| 236 | return bits_per_word; |
| 237 | |
| 238 | if (bits_per_word == 32) |
| 239 | bits_per_word = 0; |
| 240 | else |
| 241 | bits_per_word = bits_per_word - 1; |
| 242 | |
| 243 | /* mask out bits we are going to set */ |
| 244 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
| 245 | | SPMODE_PM(0xF)); |
| 246 | |
| 247 | cs->hw_mode |= SPMODE_LEN(bits_per_word); |
| 248 | |
| 249 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
| 250 | cs->hw_mode |= SPMODE_DIV16; |
| 251 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
| 252 | WARN_ONCE(pm > 16, |
| 253 | "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", |
| 254 | dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); |
| 255 | if (pm > 16) |
| 256 | pm = 16; |
| 257 | } else { |
| 258 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
| 259 | } |
| 260 | if (pm) |
| 261 | pm--; |
| 262 | |
| 263 | cs->hw_mode |= SPMODE_PM(pm); |
| 264 | |
| 265 | fsl_spi_change_mode(spi); |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
| 270 | struct spi_transfer *t, unsigned int len) |
| 271 | { |
| 272 | u32 word; |
| 273 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
| 274 | |
| 275 | mspi->count = len; |
| 276 | |
| 277 | /* enable rx ints */ |
| 278 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
| 279 | |
| 280 | /* transmit word */ |
| 281 | word = mspi->get_tx(mspi); |
| 282 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
| 288 | bool is_dma_mapped) |
| 289 | { |
| 290 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
| 291 | struct fsl_spi_reg *reg_base; |
| 292 | unsigned int len = t->len; |
| 293 | u8 bits_per_word; |
| 294 | int ret; |
| 295 | |
| 296 | reg_base = mpc8xxx_spi->reg_base; |
| 297 | bits_per_word = spi->bits_per_word; |
| 298 | if (t->bits_per_word) |
| 299 | bits_per_word = t->bits_per_word; |
| 300 | |
| 301 | if (bits_per_word > 8) { |
| 302 | /* invalid length? */ |
| 303 | if (len & 1) |
| 304 | return -EINVAL; |
| 305 | len /= 2; |
| 306 | } |
| 307 | if (bits_per_word > 16) { |
| 308 | /* invalid length? */ |
| 309 | if (len & 1) |
| 310 | return -EINVAL; |
| 311 | len /= 2; |
| 312 | } |
| 313 | |
| 314 | mpc8xxx_spi->tx = t->tx_buf; |
| 315 | mpc8xxx_spi->rx = t->rx_buf; |
| 316 | |
| 317 | reinit_completion(&mpc8xxx_spi->done); |
| 318 | |
| 319 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
| 320 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
| 321 | else |
| 322 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
| 323 | if (ret) |
| 324 | return ret; |
| 325 | |
| 326 | wait_for_completion(&mpc8xxx_spi->done); |
| 327 | |
| 328 | /* disable rx ints */ |
| 329 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
| 330 | |
| 331 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
| 332 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
| 333 | |
| 334 | return mpc8xxx_spi->count; |
| 335 | } |
| 336 | |
| 337 | static int fsl_spi_do_one_msg(struct spi_master *master, |
| 338 | struct spi_message *m) |
| 339 | { |
| 340 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
| 341 | struct spi_device *spi = m->spi; |
| 342 | struct spi_transfer *t, *first; |
| 343 | unsigned int cs_change; |
| 344 | const int nsecs = 50; |
| 345 | int status, last_bpw; |
| 346 | |
| 347 | /* |
| 348 | * In CPU mode, optimize large byte transfers to use larger |
| 349 | * bits_per_word values to reduce number of interrupts taken. |
| 350 | */ |
| 351 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 352 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { |
| 353 | if (t->len < 256 || t->bits_per_word != 8) |
| 354 | continue; |
| 355 | if ((t->len & 3) == 0) |
| 356 | t->bits_per_word = 32; |
| 357 | else if ((t->len & 1) == 0) |
| 358 | t->bits_per_word = 16; |
| 359 | } else { |
| 360 | /* |
| 361 | * CPM/QE uses Little Endian for words > 8 |
| 362 | * so transform 16 and 32 bits words into 8 bits |
| 363 | * Unfortnatly that doesn't work for LSB so |
| 364 | * reject these for now |
| 365 | * Note: 32 bits word, LSB works iff |
| 366 | * tfcr/rfcr is set to CPMFCR_GBL |
| 367 | */ |
| 368 | if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) |
| 369 | return -EINVAL; |
| 370 | if (t->bits_per_word == 16 || t->bits_per_word == 32) |
| 371 | t->bits_per_word = 8; /* pretend its 8 bits */ |
| 372 | if (t->bits_per_word == 8 && t->len >= 256 && |
| 373 | (mpc8xxx_spi->flags & SPI_CPM1)) |
| 374 | t->bits_per_word = 16; |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | /* Don't allow changes if CS is active */ |
| 379 | cs_change = 1; |
| 380 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 381 | if (cs_change) |
| 382 | first = t; |
| 383 | cs_change = t->cs_change; |
| 384 | if (first->speed_hz != t->speed_hz) { |
| 385 | dev_err(&spi->dev, |
| 386 | "speed_hz cannot change while CS is active\n"); |
| 387 | return -EINVAL; |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | last_bpw = -1; |
| 392 | cs_change = 1; |
| 393 | status = -EINVAL; |
| 394 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 395 | if (cs_change || last_bpw != t->bits_per_word) |
| 396 | status = fsl_spi_setup_transfer(spi, t); |
| 397 | if (status < 0) |
| 398 | break; |
| 399 | last_bpw = t->bits_per_word; |
| 400 | |
| 401 | if (cs_change) { |
| 402 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
| 403 | ndelay(nsecs); |
| 404 | } |
| 405 | cs_change = t->cs_change; |
| 406 | if (t->len) |
| 407 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
| 408 | if (status) { |
| 409 | status = -EMSGSIZE; |
| 410 | break; |
| 411 | } |
| 412 | m->actual_length += t->len; |
| 413 | |
| 414 | if (t->delay_usecs) |
| 415 | udelay(t->delay_usecs); |
| 416 | |
| 417 | if (cs_change) { |
| 418 | ndelay(nsecs); |
| 419 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
| 420 | ndelay(nsecs); |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | m->status = status; |
| 425 | |
| 426 | if (status || !cs_change) { |
| 427 | ndelay(nsecs); |
| 428 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
| 429 | } |
| 430 | |
| 431 | fsl_spi_setup_transfer(spi, NULL); |
| 432 | spi_finalize_current_message(master); |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | static int fsl_spi_setup(struct spi_device *spi) |
| 437 | { |
| 438 | struct mpc8xxx_spi *mpc8xxx_spi; |
| 439 | struct fsl_spi_reg *reg_base; |
| 440 | bool initial_setup = false; |
| 441 | int retval; |
| 442 | u32 hw_mode; |
| 443 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
| 444 | |
| 445 | if (!spi->max_speed_hz) |
| 446 | return -EINVAL; |
| 447 | |
| 448 | if (!cs) { |
| 449 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
| 450 | if (!cs) |
| 451 | return -ENOMEM; |
| 452 | spi_set_ctldata(spi, cs); |
| 453 | initial_setup = true; |
| 454 | } |
| 455 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
| 456 | |
| 457 | reg_base = mpc8xxx_spi->reg_base; |
| 458 | |
| 459 | hw_mode = cs->hw_mode; /* Save original settings */ |
| 460 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
| 461 | /* mask out bits we are going to set */ |
| 462 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH |
| 463 | | SPMODE_REV | SPMODE_LOOP); |
| 464 | |
| 465 | if (spi->mode & SPI_CPHA) |
| 466 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; |
| 467 | if (spi->mode & SPI_CPOL) |
| 468 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; |
| 469 | if (!(spi->mode & SPI_LSB_FIRST)) |
| 470 | cs->hw_mode |= SPMODE_REV; |
| 471 | if (spi->mode & SPI_LOOP) |
| 472 | cs->hw_mode |= SPMODE_LOOP; |
| 473 | |
| 474 | retval = fsl_spi_setup_transfer(spi, NULL); |
| 475 | if (retval < 0) { |
| 476 | cs->hw_mode = hw_mode; /* Restore settings */ |
| 477 | if (initial_setup) |
| 478 | kfree(cs); |
| 479 | return retval; |
| 480 | } |
| 481 | |
| 482 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ |
| 483 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
| 484 | |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | static void fsl_spi_cleanup(struct spi_device *spi) |
| 489 | { |
| 490 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
| 491 | |
| 492 | kfree(cs); |
| 493 | spi_set_ctldata(spi, NULL); |
| 494 | } |
| 495 | |
| 496 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
| 497 | { |
| 498 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
| 499 | |
| 500 | /* We need handle RX first */ |
| 501 | if (events & SPIE_NE) { |
| 502 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
| 503 | |
| 504 | if (mspi->rx) |
| 505 | mspi->get_rx(rx_data, mspi); |
| 506 | } |
| 507 | |
| 508 | if ((events & SPIE_NF) == 0) |
| 509 | /* spin until TX is done */ |
| 510 | while (((events = |
| 511 | mpc8xxx_spi_read_reg(®_base->event)) & |
| 512 | SPIE_NF) == 0) |
| 513 | cpu_relax(); |
| 514 | |
| 515 | /* Clear the events */ |
| 516 | mpc8xxx_spi_write_reg(®_base->event, events); |
| 517 | |
| 518 | mspi->count -= 1; |
| 519 | if (mspi->count) { |
| 520 | u32 word = mspi->get_tx(mspi); |
| 521 | |
| 522 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
| 523 | } else { |
| 524 | complete(&mspi->done); |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
| 529 | { |
| 530 | struct mpc8xxx_spi *mspi = context_data; |
| 531 | irqreturn_t ret = IRQ_NONE; |
| 532 | u32 events; |
| 533 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
| 534 | |
| 535 | /* Get interrupt events(tx/rx) */ |
| 536 | events = mpc8xxx_spi_read_reg(®_base->event); |
| 537 | if (events) |
| 538 | ret = IRQ_HANDLED; |
| 539 | |
| 540 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); |
| 541 | |
| 542 | if (mspi->flags & SPI_CPM_MODE) |
| 543 | fsl_spi_cpm_irq(mspi, events); |
| 544 | else |
| 545 | fsl_spi_cpu_irq(mspi, events); |
| 546 | |
| 547 | return ret; |
| 548 | } |
| 549 | |
| 550 | static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) |
| 551 | { |
| 552 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
| 553 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; |
| 554 | u32 slvsel; |
| 555 | u16 cs = spi->chip_select; |
| 556 | |
| 557 | if (spi->cs_gpiod) { |
| 558 | gpiod_set_value(spi->cs_gpiod, on); |
| 559 | } else if (cs < mpc8xxx_spi->native_chipselects) { |
| 560 | slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); |
| 561 | slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); |
| 562 | mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | static void fsl_spi_grlib_probe(struct device *dev) |
| 567 | { |
| 568 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
| 569 | struct spi_master *master = dev_get_drvdata(dev); |
| 570 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
| 571 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; |
| 572 | int mbits; |
| 573 | u32 capabilities; |
| 574 | |
| 575 | capabilities = mpc8xxx_spi_read_reg(®_base->cap); |
| 576 | |
| 577 | mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; |
| 578 | mbits = SPCAP_MAXWLEN(capabilities); |
| 579 | if (mbits) |
| 580 | mpc8xxx_spi->max_bits_per_word = mbits + 1; |
| 581 | |
| 582 | mpc8xxx_spi->native_chipselects = 0; |
| 583 | if (SPCAP_SSEN(capabilities)) { |
| 584 | mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); |
| 585 | mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); |
| 586 | } |
| 587 | master->num_chipselect = mpc8xxx_spi->native_chipselects; |
| 588 | pdata->cs_control = fsl_spi_grlib_cs_control; |
| 589 | } |
| 590 | |
| 591 | static struct spi_master * fsl_spi_probe(struct device *dev, |
| 592 | struct resource *mem, unsigned int irq) |
| 593 | { |
| 594 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
| 595 | struct spi_master *master; |
| 596 | struct mpc8xxx_spi *mpc8xxx_spi; |
| 597 | struct fsl_spi_reg *reg_base; |
| 598 | u32 regval; |
| 599 | int ret = 0; |
| 600 | |
| 601 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
| 602 | if (master == NULL) { |
| 603 | ret = -ENOMEM; |
| 604 | goto err; |
| 605 | } |
| 606 | |
| 607 | dev_set_drvdata(dev, master); |
| 608 | |
| 609 | mpc8xxx_spi_probe(dev, mem, irq); |
| 610 | |
| 611 | master->setup = fsl_spi_setup; |
| 612 | master->cleanup = fsl_spi_cleanup; |
| 613 | master->transfer_one_message = fsl_spi_do_one_msg; |
| 614 | master->use_gpio_descriptors = true; |
| 615 | |
| 616 | mpc8xxx_spi = spi_master_get_devdata(master); |
| 617 | mpc8xxx_spi->max_bits_per_word = 32; |
| 618 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
| 619 | |
| 620 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
| 621 | if (ret) |
| 622 | goto err_cpm_init; |
| 623 | |
| 624 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
| 625 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
| 626 | ret = PTR_ERR(mpc8xxx_spi->reg_base); |
| 627 | goto err_probe; |
| 628 | } |
| 629 | |
| 630 | if (mpc8xxx_spi->type == TYPE_GRLIB) |
| 631 | fsl_spi_grlib_probe(dev); |
| 632 | |
| 633 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
| 634 | master->bits_per_word_mask = |
| 635 | (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); |
| 636 | else |
| 637 | master->bits_per_word_mask = |
| 638 | (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); |
| 639 | |
| 640 | master->bits_per_word_mask &= |
| 641 | SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); |
| 642 | |
| 643 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
| 644 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; |
| 645 | |
| 646 | if (mpc8xxx_spi->set_shifts) |
| 647 | /* 8 bits per word and MSB first */ |
| 648 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, |
| 649 | &mpc8xxx_spi->tx_shift, 8, 1); |
| 650 | |
| 651 | /* Register for SPI Interrupt */ |
| 652 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, |
| 653 | 0, "fsl_spi", mpc8xxx_spi); |
| 654 | |
| 655 | if (ret != 0) |
| 656 | goto err_probe; |
| 657 | |
| 658 | reg_base = mpc8xxx_spi->reg_base; |
| 659 | |
| 660 | /* SPI controller initializations */ |
| 661 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
| 662 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
| 663 | mpc8xxx_spi_write_reg(®_base->command, 0); |
| 664 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); |
| 665 | |
| 666 | /* Enable SPI interface */ |
| 667 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; |
| 668 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
| 669 | regval &= ~SPMODE_LEN(0xF); |
| 670 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); |
| 671 | } |
| 672 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
| 673 | regval |= SPMODE_OP; |
| 674 | |
| 675 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
| 676 | |
| 677 | ret = devm_spi_register_master(dev, master); |
| 678 | if (ret < 0) |
| 679 | goto err_probe; |
| 680 | |
| 681 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
| 682 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
| 683 | |
| 684 | return master; |
| 685 | |
| 686 | err_probe: |
| 687 | fsl_spi_cpm_free(mpc8xxx_spi); |
| 688 | err_cpm_init: |
| 689 | spi_master_put(master); |
| 690 | err: |
| 691 | return ERR_PTR(ret); |
| 692 | } |
| 693 | |
| 694 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
| 695 | { |
| 696 | if (spi->cs_gpiod) { |
| 697 | gpiod_set_value(spi->cs_gpiod, on); |
| 698 | } else { |
| 699 | struct device *dev = spi->dev.parent->parent; |
| 700 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
| 701 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
| 702 | |
| 703 | if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) |
| 704 | return; |
| 705 | iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); |
| 706 | } |
| 707 | } |
| 708 | |
| 709 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
| 710 | { |
| 711 | struct device *dev = &ofdev->dev; |
| 712 | struct device_node *np = ofdev->dev.of_node; |
| 713 | struct spi_master *master; |
| 714 | struct resource mem; |
| 715 | int irq = 0, type; |
| 716 | int ret = -ENOMEM; |
| 717 | |
| 718 | ret = of_mpc8xxx_spi_probe(ofdev); |
| 719 | if (ret) |
| 720 | return ret; |
| 721 | |
| 722 | type = fsl_spi_get_type(&ofdev->dev); |
| 723 | if (type == TYPE_FSL) { |
| 724 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
| 725 | bool spisel_boot = false; |
| 726 | #if IS_ENABLED(CONFIG_FSL_SOC) |
| 727 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
| 728 | |
| 729 | spisel_boot = of_property_read_bool(np, "fsl,spisel_boot"); |
| 730 | if (spisel_boot) { |
| 731 | pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); |
| 732 | if (!pinfo->immr_spi_cs) { |
| 733 | ret = -ENOMEM; |
| 734 | goto err; |
| 735 | } |
| 736 | } |
| 737 | #endif |
| 738 | /* |
| 739 | * Handle the case where we have one hardwired (always selected) |
| 740 | * device on the first "chipselect". Else we let the core code |
| 741 | * handle any GPIOs or native chip selects and assign the |
| 742 | * appropriate callback for dealing with the CS lines. This isn't |
| 743 | * supported on the GRLIB variant. |
| 744 | */ |
| 745 | ret = gpiod_count(dev, "cs"); |
| 746 | if (ret < 0) |
| 747 | ret = 0; |
| 748 | if (ret == 0 && !spisel_boot) { |
| 749 | pdata->max_chipselect = 1; |
| 750 | } else { |
| 751 | pdata->max_chipselect = ret + spisel_boot; |
| 752 | pdata->cs_control = fsl_spi_cs_control; |
| 753 | } |
| 754 | } |
| 755 | |
| 756 | ret = of_address_to_resource(np, 0, &mem); |
| 757 | if (ret) |
| 758 | goto err; |
| 759 | |
| 760 | irq = platform_get_irq(ofdev, 0); |
| 761 | if (irq < 0) { |
| 762 | ret = irq; |
| 763 | goto err; |
| 764 | } |
| 765 | |
| 766 | master = fsl_spi_probe(dev, &mem, irq); |
| 767 | if (IS_ERR(master)) { |
| 768 | ret = PTR_ERR(master); |
| 769 | goto err; |
| 770 | } |
| 771 | |
| 772 | return 0; |
| 773 | |
| 774 | err: |
| 775 | return ret; |
| 776 | } |
| 777 | |
| 778 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
| 779 | { |
| 780 | struct spi_master *master = platform_get_drvdata(ofdev); |
| 781 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
| 782 | |
| 783 | fsl_spi_cpm_free(mpc8xxx_spi); |
| 784 | return 0; |
| 785 | } |
| 786 | |
| 787 | static struct platform_driver of_fsl_spi_driver = { |
| 788 | .driver = { |
| 789 | .name = "fsl_spi", |
| 790 | .of_match_table = of_fsl_spi_match, |
| 791 | }, |
| 792 | .probe = of_fsl_spi_probe, |
| 793 | .remove = of_fsl_spi_remove, |
| 794 | }; |
| 795 | |
| 796 | #ifdef CONFIG_MPC832x_RDB |
| 797 | /* |
| 798 | * XXX XXX XXX |
| 799 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
| 800 | * only. The driver should go away soon, since newer MPC8323E-RDB's device |
| 801 | * tree can work with OpenFirmware driver. But for now we support old trees |
| 802 | * as well. |
| 803 | */ |
| 804 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
| 805 | { |
| 806 | struct resource *mem; |
| 807 | int irq; |
| 808 | struct spi_master *master; |
| 809 | |
| 810 | if (!dev_get_platdata(&pdev->dev)) |
| 811 | return -EINVAL; |
| 812 | |
| 813 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 814 | if (!mem) |
| 815 | return -EINVAL; |
| 816 | |
| 817 | irq = platform_get_irq(pdev, 0); |
| 818 | if (irq <= 0) |
| 819 | return -EINVAL; |
| 820 | |
| 821 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
| 822 | return PTR_ERR_OR_ZERO(master); |
| 823 | } |
| 824 | |
| 825 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
| 826 | { |
| 827 | struct spi_master *master = platform_get_drvdata(pdev); |
| 828 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
| 829 | |
| 830 | fsl_spi_cpm_free(mpc8xxx_spi); |
| 831 | |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
| 836 | static struct platform_driver mpc8xxx_spi_driver = { |
| 837 | .probe = plat_mpc8xxx_spi_probe, |
| 838 | .remove = plat_mpc8xxx_spi_remove, |
| 839 | .driver = { |
| 840 | .name = "mpc8xxx_spi", |
| 841 | }, |
| 842 | }; |
| 843 | |
| 844 | static bool legacy_driver_failed; |
| 845 | |
| 846 | static void __init legacy_driver_register(void) |
| 847 | { |
| 848 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
| 849 | } |
| 850 | |
| 851 | static void __exit legacy_driver_unregister(void) |
| 852 | { |
| 853 | if (legacy_driver_failed) |
| 854 | return; |
| 855 | platform_driver_unregister(&mpc8xxx_spi_driver); |
| 856 | } |
| 857 | #else |
| 858 | static void __init legacy_driver_register(void) {} |
| 859 | static void __exit legacy_driver_unregister(void) {} |
| 860 | #endif /* CONFIG_MPC832x_RDB */ |
| 861 | |
| 862 | static int __init fsl_spi_init(void) |
| 863 | { |
| 864 | legacy_driver_register(); |
| 865 | return platform_driver_register(&of_fsl_spi_driver); |
| 866 | } |
| 867 | module_init(fsl_spi_init); |
| 868 | |
| 869 | static void __exit fsl_spi_exit(void) |
| 870 | { |
| 871 | platform_driver_unregister(&of_fsl_spi_driver); |
| 872 | legacy_driver_unregister(); |
| 873 | } |
| 874 | module_exit(fsl_spi_exit); |
| 875 | |
| 876 | MODULE_AUTHOR("Kumar Gala"); |
| 877 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
| 878 | MODULE_LICENSE("GPL"); |