marvell/linux/drivers/usb/dwc2/platform_otg.c

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * platform.c - DesignWare HS OTG Controller platform driver
 *
 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation; either version 2 of the License, or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <linux/reset.h>

#include <linux/usb/of.h>
#include <soc/asr/regs-addr.h>
#include <linux/platform_data/mv_usb.h>
#include <linux/usb/mv_usb2_phy.h>
#include <linux/usb.h>
#include <linux/usb/ch9.h>
#include <linux/usb/otg.h>
#include <linux/usb/gadget.h>
#include <linux/usb/hcd.h>
#include <linux/pm_qos.h>
#include <linux/gpio.h>
#include <linux/edge_wakeup_mmp.h>

#include "core.h"
#include "hcd.h"
#include "debug.h"

static const char dwc2_driver_name[] = "dwc2";

#define USB_HANDLE_TIME_MSEC (5000)

#define APMU_USB_WAKE_CLR		(0x07c)

#define USB_VBUS_WAKE_EN		(0x1 << 11)
#define USB_ID_WAKE_EN			(0x1 << 22)
#define USB_LINEST_WAKE_EN		((0x1 << 9) | (0x1 << 10))

#define USB_VBUS_WAKE_CLR		(0x1 << 4)
#define USB_ID_WAKE_CLR			(0x1 << 23)
#define USB_LINEST_WAKE_CLR		(0x1 << 7)

#define ENNUM		-1
#define DWC2_MAX_HOST_CFG	(16)
#define DWC2_MAX_DEVICE_CFG	(64)

#define APMU_USB_CLK_CTL	(0x05C) /* fact */
#define VBUS_RISE_FALL_MS		(10)

struct dwc2_reg_val {
	u32 val;
	u32 reg;
};

extern void dwc2_release_pm_qos(void);
extern void dwc2_acquire_pm_qos(void);

static u32 force_host = 0;
static u32 force_dev = 0;
static bool usb_host_vbus_on;
static struct dwc2_hsotg *g_hsotg;

module_param(force_dev, uint, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(force_dev, "dwc2 otg force device mode");

module_param(force_host, uint, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(force_host, "dwc2 otg force host mode");

struct dwc2_reg_val dwc2_host_global_cfg[] = {
	{.val = 0x00000000, .reg = 0x00000008},
	{.val = 0x20001400, .reg = 0x0000000c},
	{.val = 0x20001400, .reg = 0x0000000c},
	{.val = 0x00000026, .reg = 0x00000008},
	{.val = 0x20001400, .reg = 0x0000000c},
	{.val = 0x00280000, .reg = 0x00000000},
	{.val = 0xffffffff, .reg = 0x00000004},
	{.val = 0xffffffff, .reg = 0x00000014},
	{.val = 0xd0000806, .reg = 0x00000018},
	{.val = 0xF3000806, .reg = 0x00000018},
};

struct dwc2_reg_val dwc2_device_global_cfg[] = {
	{.val = 0x40001400, .reg = 0x0000000c},
	{.val = 0x00000800, .reg = 0x00000900},
	{.val = 0x00000800, .reg = 0x00000b00},
	{.val = 0x00001000, .reg = 0x00000920},
	{.val = 0x00001000, .reg = 0x00000b20},
	{.val = 0x00001800, .reg = 0x00000940},
	{.val = 0x00001800, .reg = 0x00000b40},
	{.val = 0x00002000, .reg = 0x00000960},
	{.val = 0x00002000, .reg = 0x00000b60},
	{.val = 0x00002800, .reg = 0x00000980},
	{.val = 0x00002800, .reg = 0x00000b80},
	{.val = 0x00003000, .reg = 0x000009a0},
	{.val = 0x00003000, .reg = 0x00000ba0},
	{.val = 0x00003800, .reg = 0x000009c0},
	{.val = 0x00003800, .reg = 0x00000bc0},
	{.val = 0x00004000, .reg = 0x000009e0},
	{.val = 0x00004000, .reg = 0x00000be0},
	{.val = 0x00004800, .reg = 0x00000a00},
	{.val = 0x00004800, .reg = 0x00000c00},
	{.val = 0x00005000, .reg = 0x00000a20},
	{.val = 0x00005000, .reg = 0x00000c20},
	{.val = 0x00005800, .reg = 0x00000a40},
	{.val = 0x00005800, .reg = 0x00000c40},
	{.val = 0x00006000, .reg = 0x00000a60},
	{.val = 0x00006000, .reg = 0x00000c60},
	{.val = 0x00006800, .reg = 0x00000a80},
	{.val = 0x00006800, .reg = 0x00000c80},
	{.val = 0x00007000, .reg = 0x00000aa0},
	{.val = 0x00007000, .reg = 0x00000ca0},
	{.val = 0x00000000, .reg = 0x00000ac0},
	{.val = 0x00000000, .reg = 0x00000cc0},
	{.val = 0x00000800, .reg = 0x00000ae0},
	{.val = 0x00000800, .reg = 0x00000ce0},
};

bool is_otg_host_vbus_on(void)
{
	return usb_host_vbus_on;
}

int usb_otg_set_vbus(struct dwc2_hsotg *hsotg, bool on)
{
	int ret = 0;

	usb_host_vbus_on = on;
	if (hsotg->gpio_num >= 0)
		ret = gpio_direction_output(hsotg->gpio_num, on);
	return ret;
}

static void __dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
			       bool host_mode)
{
	ktime_t start;
	ktime_t end;
	unsigned int timeout = 110;

	dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
		 host_mode ? "host" : "device");

	start = ktime_get();

	while (1) {
		s64 ms;

		if (dwc2_is_host_mode(hsotg) == host_mode) {
			dev_info(hsotg->dev, "%s mode set\n",
				 host_mode ? "Host" : "Device");
			break;
		}

		end = ktime_get();
		ms = ktime_to_ms(ktime_sub(end, start));

		if (ms >= (s64)timeout) {
			dev_warn(hsotg->dev, "!!!!%s: Couldn't set %s mode\n",
				 __func__, host_mode ? "host" : "device");
			break;
		}

		usleep_range(1000, 2000);
	}
}

static void _dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
{
	u32 gusbcfg;
	u32 set;
	u32 clear;

	dev_info(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");

	gusbcfg = dwc2_readl(hsotg, GUSBCFG);

	set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
	clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;

	gusbcfg &= ~clear;
	gusbcfg |= set;
	dwc2_writel(hsotg, gusbcfg, GUSBCFG);

	__dwc2_wait_for_mode(hsotg, host);
	return;
}

static void __maybe_unused dwc2_force_host_mode(struct dwc2_hsotg *hsotg)
{
	_dwc2_force_mode(hsotg, true);
}

static void dwc2_force_device_mode(struct dwc2_hsotg *hsotg)
{
	_dwc2_force_mode(hsotg, false);
}

int hsotg_controller_reset(struct dwc2_hsotg *hsotg)
{
	int ret;
	void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);

	/* Add global reset and phy reinit to guarantee safe reset per ASIC */
	writel(0x0, apmu_base + APMU_USB_CLK_CTL);
	udelay(200);
	writel(0xb, apmu_base + APMU_USB_CLK_CTL);
	hsotg->usb_do_restart = 0;
	usb_phy_shutdown(hsotg->uphy);
	usb_phy_init(hsotg->uphy);
	usb_phy_set_suspend(hsotg->uphy, 0);

	ret = dwc2_core_reset(hsotg, false);
	if (ret) {
		dev_err(g_hsotg->dev, "!!!!!dwc2_core_reset failed(%d)\n", ret);
	}

	return ret;
}

int hsotg_restore_host_cfgs(struct dwc2_hsotg *hsotg)
{
	int i;

	dev_info(hsotg->dev, "restore host cfgs\n");
	for (i = 0; i < ARRAY_SIZE(dwc2_host_global_cfg); i++)
		dwc2_writel(hsotg, dwc2_host_global_cfg[i].val, dwc2_host_global_cfg[i].reg);

	return 0;
}

int hsotg_restore_device_cfgs(struct dwc2_hsotg *hsotg)
{
	int i;

	dev_info(hsotg->dev, "restore dev cfgs\n");
	for (i = 0; i < ARRAY_SIZE(dwc2_device_global_cfg); i++)
		dwc2_writel(hsotg, dwc2_device_global_cfg[i].val, dwc2_device_global_cfg[i].reg);
	return 0;
}

static void hsotg_otg_start_host(struct dwc2_hsotg *hsotg, int on)
{
	struct usb_hcd *hcd = (struct usb_hcd *)g_hsotg->priv;

	if (!hcd) {
		dev_err(g_hsotg->dev, "!!!!!hsotg->hcd is not set!\n");
		return;
	}

	dev_info(g_hsotg->dev, "%s host\n", on ? "start" : "stop");

	if (on) {
		/* set constraint before turn on vbus */
		pm_stay_awake(hsotg->dev);
		pm_qos_update_request(&hsotg->qos_idle, hsotg->lpm_qos);
		hsotg_controller_reset(hsotg);
		dwc2_force_host_mode(hsotg);
		hsotg_restore_host_cfgs(hsotg);
		usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
		dwc2_enable_global_interrupts(hsotg);
	} else {
		usb_remove_hcd(hcd);
		hsotg_controller_reset(hsotg);
		usb_phy_set_suspend(hsotg->uphy, 1);
		pm_qos_update_request(&hsotg->qos_idle, PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE);
		pm_relax(hsotg->dev);
	}
}

static void hsotg_otg_start_peripherals(struct dwc2_hsotg *hsotg, int on)
{
	struct usb_gadget *gadget = (struct usb_gadget *)&g_hsotg->gadget;

	if (!hsotg->gadget_enabled) {
		dev_err(g_hsotg->dev, "!!!!!hsotg->gadget is not enabled!\n");
		return;
	}

	dev_info(g_hsotg->dev, "gadget %s\n", on ? "on" : "off");
	pm_wakeup_event(hsotg->dev, USB_HANDLE_TIME_MSEC);
	pm_qos_update_request_timeout(&hsotg->qos_idle, hsotg->lpm_qos, USB_HANDLE_TIME_MSEC * 1000);
	if (on) {
		hsotg_controller_reset(hsotg);
		dwc2_force_device_mode(hsotg);
		hsotg_restore_device_cfgs(hsotg);
		usb_gadget_vbus_connect(gadget);
	} else {
		usb_gadget_vbus_disconnect(gadget);
		/* usb_phy_set_suspend(hsotg->uphy, 1); */
	}
}

static void usb_otg_work_fn(struct work_struct *work)
{
	int vbus, ret;
	struct dwc2_hsotg *hsotg = g_hsotg;
	int 		old_otg_state;

	/* check ID and VBUS and update cable state */
	if (hsotg->usbid_gpio >= 0)
		hsotg->cur_usbid_val = gpio_get_value(hsotg->usbid_gpio);
	else
		hsotg->cur_usbid_val = 1;
	mutex_lock(&hsotg->mtx_lock);
	ret = pxa_usb_extern_call(PXA_USB_DEV_OTG, vbus, get_vbus, &vbus);
	if (ret) {
		vbus = usb_phy_get_vbus(hsotg->uphy);
	}
	hsotg->cur_vbus_val = vbus;

	if (force_host)
		hsotg->cur_usbid_val = 0;
	else if (force_dev)
		hsotg->cur_usbid_val = 1;

	old_otg_state = hsotg->otg_state;
	pr_info("=>old_otg_state: %d, usbid: %d vbus: %d\n",
			old_otg_state, hsotg->cur_usbid_val, hsotg->cur_vbus_val);

	/* at first we clean states which are no longer active */
	if (hsotg->otg_state == OTG_STATE_B_IDLE) {
		if (!hsotg->cur_usbid_val) {
			printk("disable vbus irq\n");
			disable_irq(hsotg->vbus_irq);
			usb_otg_set_vbus(hsotg, true);
			msleep(VBUS_RISE_FALL_MS);
			hsotg->otg_state = OTG_STATE_A_HOST;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_host(hsotg, 1);
		} else {
			if (vbus)
				hsotg->otg_state = OTG_STATE_B_PERIPHERAL;
			else
				hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_peripherals(hsotg, vbus);
		}
	} else if (hsotg->otg_state == OTG_STATE_B_PERIPHERAL) {
		if (!hsotg->cur_vbus_val) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg_otg_start_peripherals(hsotg, 0);
		}
	} else if (hsotg->otg_state == OTG_STATE_A_HOST) {
		if (hsotg->cur_usbid_val) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_host(hsotg, 0);
			msleep(1);
			usb_otg_set_vbus(hsotg, false);
			msleep(VBUS_RISE_FALL_MS);
			printk("enable vbus irq\n");
			enable_irq(hsotg->vbus_irq);
		}
	}
	mutex_unlock(&hsotg->mtx_lock);
	pr_info("cur_otg_state: [%d->%d], usbid: %d vbus: %d\n",
			old_otg_state, hsotg->otg_state,
			hsotg->cur_usbid_val, hsotg->cur_vbus_val);
}

static irqreturn_t vbus_irq(int irq, void *dev);
static irqreturn_t usbid_irq(int irq, void *dev_id)
{
	struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)g_hsotg;
	dev_info(hsotg->dev, "dwc2 usbid_irq is served..\n");
	vbus_irq(irq, dev_id);
	return IRQ_HANDLED;
}

static void usbid_wakeup_handler(int gpio, void *data)
{
}

static int usbid_irq_init(struct platform_device *pdev, struct dwc2_hsotg *hsotg)
{
	int ret = -1;

	ret = of_property_read_u32(pdev->dev.of_node,
			"usbid_gpio", &hsotg->usbid_gpio);
	pr_info("dwc2:usbid_gpio: %d\n", hsotg->usbid_gpio);

	if (ret) {
		hsotg->usbid_gpio = -1;
		pr_err("%s no usbid-gpio defined\n", __func__);
		return ret;
	}

	of_property_read_u32(pdev->dev.of_node,
			"edge_detect_gpio", &hsotg->edge_det_gpio);
	if (hsotg->edge_det_gpio > 0) {
			ret = request_mfp_edge_wakeup(hsotg->edge_det_gpio,
						      usbid_wakeup_handler,
						      NULL, &pdev->dev);
			if (ret) {
				dev_err(hsotg->dev, "failed to request edge wakeup.\n");
				goto out;	
			}
	}

	hsotg->cur_usbid_val = gpio_get_value(hsotg->usbid_gpio);
	ret = gpio_request(hsotg->usbid_gpio, "dwc2-usbid");
	gpio_direction_input(hsotg->usbid_gpio);

	hsotg->usbid_irq = gpio_to_irq(hsotg->usbid_gpio);
	ret =
	    request_threaded_irq(hsotg->usbid_irq, NULL, usbid_irq,
			IRQF_SHARED | IRQF_TRIGGER_RISING |
			IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "dwc2-usbid",
			hsotg);
	if (ret < 0) {
		dev_err(hsotg->dev, "%s: request irq failed!\n",
				 __func__);
	}

out:
	return ret;
}

static irqreturn_t vbus_irq(int irq, void *dev)
{
	struct dwc2_hsotg *hsotg_dev = (struct dwc2_hsotg *)dev;
	void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
	dev_info(hsotg_dev->dev, "asr-usb vbus int enter..\n");
	/* wait 50ms for vbus to be stable */
	msleep(50);
	writel(readl(apmu_base + APMU_USB_WAKE_CLR)
			| (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR
			| USB_ID_WAKE_CLR),
			apmu_base + APMU_USB_WAKE_CLR);

	pm_wakeup_event(hsotg_dev->dev, USB_HANDLE_TIME_MSEC);
	if (work_pending(&g_hsotg->otg_work.work)) {
		dev_info(hsotg_dev->dev, "cancel otg work...");
		cancel_delayed_work_sync(&g_hsotg->otg_work);
		dev_info(hsotg_dev->dev, "done\n");
		pm_wakeup_event(hsotg_dev->dev, USB_HANDLE_TIME_MSEC);
	}
	schedule_delayed_work(&g_hsotg->otg_work, 0);
	dev_info(hsotg_dev->dev, "asr-usb vbus interrupt is served..\n");
	return IRQ_HANDLED;
}

/*
 * Check the dr_mode against the module configuration and hardware
 * capabilities.
 *
 * The hardware, module, and dr_mode, can each be set to host, device,
 * or otg. Check that all these values are compatible and adjust the
 * value of dr_mode if possible.
 *
 *                      actual
 *    HW  MOD dr_mode   dr_mode
 *  ------------------------------
 *   HST  HST  any    :  HST
 *   HST  DEV  any    :  ---
 *   HST  OTG  any    :  HST
 *
 *   DEV  HST  any    :  ---
 *   DEV  DEV  any    :  DEV
 *   DEV  OTG  any    :  DEV
 *
 *   OTG  HST  any    :  HST
 *   OTG  DEV  any    :  DEV
 *   OTG  OTG  any    :  dr_mode
 */
static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
{
	enum usb_dr_mode mode;

	hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
	if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
		hsotg->dr_mode = USB_DR_MODE_OTG;

	mode = hsotg->dr_mode;

	if (dwc2_hw_is_device(hsotg)) {
		if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
			dev_err(hsotg->dev,
				"Controller does not support host mode.\n");
			return -EINVAL;
		}
		mode = USB_DR_MODE_PERIPHERAL;
	} else if (dwc2_hw_is_host(hsotg)) {
		if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
			dev_err(hsotg->dev,
				"Controller does not support device mode.\n");
			return -EINVAL;
		}
		mode = USB_DR_MODE_HOST;
	} else {
		if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
			mode = USB_DR_MODE_HOST;
		else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
			mode = USB_DR_MODE_PERIPHERAL;
	}

	if (mode != hsotg->dr_mode) {
		dev_warn(hsotg->dev,
			 "Configuration mismatch. dr_mode forced to %s\n",
			mode == USB_DR_MODE_HOST ? "host" : "device");

		hsotg->dr_mode = mode;
	}

	dev_info(hsotg->dev, "dr_mode: %d\n", hsotg->dr_mode);
	return 0;
}

static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
{
	struct platform_device *pdev = to_platform_device(hsotg->dev);
	int ret;

	ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
				    hsotg->supplies);
	if (ret)
		return ret;

	if (hsotg->clk) {
		ret = clk_prepare_enable(hsotg->clk);
		if (ret)
			return ret;
	}

	if (hsotg->uphy) {
		ret = usb_phy_init(hsotg->uphy);
	} else if (hsotg->plat && hsotg->plat->phy_init) {
		ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
	} else {
		ret = phy_power_on(hsotg->phy);
		if (ret == 0)
			ret = phy_init(hsotg->phy);
	}

	return ret;
}

/**
 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 * @hsotg: The driver state
 *
 * A wrapper for platform code responsible for controlling
 * low-level USB platform resources (phy, clock, regulators)
 */
int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
{
	int ret = __dwc2_lowlevel_hw_enable(hsotg);

	if (ret == 0)
		hsotg->ll_hw_enabled = true;
	return ret;
}

static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
{
	struct platform_device *pdev = to_platform_device(hsotg->dev);
	int ret = 0;

#ifdef CONFIG_CPU_ASR18XX
	return 0;
#endif

	if (hsotg->uphy) {
		usb_phy_shutdown(hsotg->uphy);
	} else if (hsotg->plat && hsotg->plat->phy_exit) {
		ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
	} else {
		ret = phy_exit(hsotg->phy);
		if (ret == 0)
			ret = phy_power_off(hsotg->phy);
	}
	if (ret)
		return ret;

	if (hsotg->clk)
		clk_disable_unprepare(hsotg->clk);

	ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
				     hsotg->supplies);

	return ret;
}

/**
 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 * @hsotg: The driver state
 *
 * A wrapper for platform code responsible for controlling
 * low-level USB platform resources (phy, clock, regulators)
 */
int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
{
	int ret = __dwc2_lowlevel_hw_disable(hsotg);

	if (ret == 0)
		hsotg->ll_hw_enabled = false;
	return ret;
}

static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
{
	int i, ret;

	hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
	if (IS_ERR(hsotg->reset)) {
		ret = PTR_ERR(hsotg->reset);
		dev_err(hsotg->dev, "error getting reset control %d\n", ret);
		return ret;
	}

	reset_control_deassert(hsotg->reset);

	hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
	if (IS_ERR(hsotg->reset_ecc)) {
		ret = PTR_ERR(hsotg->reset_ecc);
		dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
		return ret;
	}

	reset_control_deassert(hsotg->reset_ecc);

	/*
	 * Attempt to find a generic PHY, then look for an old style
	 * USB PHY and then fall back to pdata
	 */
	hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
	if (IS_ERR(hsotg->phy)) {
		ret = PTR_ERR(hsotg->phy);
		switch (ret) {
		case -ENODEV:
		case -ENOSYS:
			hsotg->phy = NULL;
			break;
		case -EPROBE_DEFER:
			return ret;
		default:
			dev_err(hsotg->dev, "error getting phy %d\n", ret);
			return ret;
		}
	}

	if (!hsotg->phy) {
		hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
		if (IS_ERR(hsotg->uphy)) {
			ret = PTR_ERR(hsotg->uphy);
			switch (ret) {
			case -ENODEV:
			case -ENXIO:
				hsotg->uphy = NULL;
				break;
			case -EPROBE_DEFER:
				return ret;
			default:
				dev_err(hsotg->dev, "error getting usb phy %d\n",
					ret);
				return ret;
			}
		}
	}

	hsotg->plat = dev_get_platdata(hsotg->dev);

	/* Clock */
	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
	if (IS_ERR(hsotg->clk)) {
		dev_err(hsotg->dev, "cannot get otg clock\n");
		return PTR_ERR(hsotg->clk);
	}

	/* Regulators */
	for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
		hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];

	ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
				      hsotg->supplies);
	if (ret) {
		dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
		return ret;
	}
	return 0;
}

/**
 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 * DWC_otg driver
 *
 * @dev: Platform device
 *
 * This routine is called, for example, when the rmmod command is executed. The
 * device may or may not be electrically present. If it is present, the driver
 * stops device processing. Any resources used on behalf of this device are
 * freed.
 */
static int dwc2_driver_remove(struct platform_device *dev)
{
	struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);

	dwc2_debugfs_exit(hsotg);
	if (hsotg->hcd_enabled)
		dwc2_hcd_remove(hsotg);
	if (hsotg->gadget_enabled)
		dwc2_hsotg_remove(hsotg);

	if (hsotg->ll_hw_enabled)
		dwc2_lowlevel_hw_disable(hsotg);

	reset_control_assert(hsotg->reset);
	reset_control_assert(hsotg->reset_ecc);

	return 0;
}

/**
 * dwc2_driver_shutdown() - Called on device shutdown
 *
 * @dev: Platform device
 *
 * In specific conditions (involving usb hubs) dwc2 devices can create a
 * lot of interrupts, even to the point of overwhelming devices running
 * at low frequencies. Some devices need to do special clock handling
 * at shutdown-time which may bring the system clock below the threshold
 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
 * prevents reboots/poweroffs from getting stuck in such cases.
 */
static void dwc2_driver_shutdown(struct platform_device *dev)
{
	struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);

	dwc2_disable_global_interrupts(hsotg);
	synchronize_irq(hsotg->irq);
}

/**
 * dwc2_check_core_endianness() - Returns true if core and AHB have
 * opposite endianness.
 * @hsotg:	Programming view of the DWC_otg controller.
 */
static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
{
	u32 snpsid;

	snpsid = ioread32(hsotg->regs + GSNPSID);
	if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
	    (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
	    (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
		return false;
	return true;
}

static ssize_t otg_mode_store(struct device *pdev, struct device_attribute *attr,
			      const char *buf, size_t count)
{
	struct dwc2_hsotg *hsotg = dev_get_drvdata(pdev);
	enum usb_dr_mode dr_mode;

	mutex_lock(&hsotg->mtx_lock);
	if (!strncmp(buf, "host", 4)) {
		if(hsotg->otg_state == OTG_STATE_A_HOST) {
			pr_err("already in host mode\n");
			goto out;
		}
		disable_irq(hsotg->vbus_irq);
		pr_info("disable vbus irq\n");

		if (hsotg->otg_state == OTG_STATE_B_PERIPHERAL) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_peripherals(hsotg, 0);
		}

		if (hsotg->otg_state == OTG_STATE_B_IDLE) {
			force_host = 1;
			force_dev  = 0;
			usb_otg_set_vbus(hsotg, true);
			msleep(VBUS_RISE_FALL_MS);
			hsotg->otg_state = OTG_STATE_A_HOST;
			hsotg->op_state = hsotg->otg_state;
			dr_mode = USB_DR_MODE_HOST;
			hsotg->dr_mode = dr_mode;
			hsotg_otg_start_host(hsotg, 1);
			dev_info(pdev, "userspace set host: otg_mode: %d\n", hsotg->otg_state);
		}
	} else if (!strncmp(buf, "device", 6)) {
		if(hsotg->otg_state == OTG_STATE_B_PERIPHERAL) {
			pr_err("already in device mode\n");
			goto out;
		}

		if (hsotg->otg_state == OTG_STATE_A_HOST) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_host(hsotg, 0);
			msleep(1);
			usb_otg_set_vbus(hsotg, false);
			msleep(VBUS_RISE_FALL_MS);
		}

		if (hsotg->otg_state == OTG_STATE_B_IDLE) {
			force_host = 0;
			force_dev  = 1;
			dr_mode = USB_DR_MODE_PERIPHERAL;
			hsotg->dr_mode = dr_mode;
			hsotg->otg_state = OTG_STATE_B_PERIPHERAL;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_peripherals(hsotg, 1);
			dev_info(pdev, "userspace set device: otg_mode: %d\n", hsotg->otg_state);
		}

		enable_irq(hsotg->vbus_irq);
		pr_err("enable vbus irq\n");
	} else {
		force_host = 0;
		force_dev  = 0;
		if (hsotg->otg_state == OTG_STATE_B_PERIPHERAL) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg_otg_start_peripherals(hsotg, 0);
		} else if (hsotg->otg_state == OTG_STATE_A_HOST) {
			hsotg->otg_state = OTG_STATE_B_IDLE;
			hsotg->op_state = hsotg->otg_state;
			hsotg_otg_start_host(hsotg, 0);
			msleep(1);
			usb_otg_set_vbus(hsotg, false);
			msleep(VBUS_RISE_FALL_MS);
			printk("enable vbus irq\n");
			enable_irq(hsotg->vbus_irq);
		} else {
			 dev_info(pdev, "already in idle none host/device mode: %d\n", hsotg->otg_state);
		}
	}

out:
	mutex_unlock(&hsotg->mtx_lock);

	return count;
}

static ssize_t otg_mode_show(struct device *pdev, struct device_attribute *attr, char *buf)
{
	struct dwc2_hsotg *hsotg = dev_get_drvdata(pdev);
	char *host_dev_str;

	if (hsotg->otg_state == OTG_STATE_A_HOST)
		host_dev_str = "host";
	else if (hsotg->otg_state == OTG_STATE_B_PERIPHERAL)
		host_dev_str = "device";
	else
		host_dev_str = "idle";

	return sprintf(buf, "otg_state:%d, otg mode: %s\n", hsotg->otg_state, host_dev_str);
}

static DEVICE_ATTR(otg_mode, S_IWUSR |S_IRUGO, otg_mode_show, otg_mode_store);

/**
 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 * driver
 *
 * @dev: Platform device
 *
 * This routine creates the driver components required to control the device
 * (core, HCD, and PCD) and initializes the device. The driver components are
 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 * in the device private data. This allows the driver to access the dwc2_hsotg
 * structure on subsequent calls to driver methods for this device.
 */
static int dwc2_driver_probe(struct platform_device *dev)
{
	struct dwc2_hsotg *hsotg;
	struct resource *res;
	int retval;
	void __iomem *apmu_base;
	struct device_node *node = dev->dev.of_node;
	u32 data;

	hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
	if (!hsotg)
		return -ENOMEM;

	hsotg->dev = &dev->dev;

	/*
	 * Use reasonable defaults so platforms don't have to provide these.
	 */
	if (!dev->dev.dma_mask)
		dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
	retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
	if (retval) {
		dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
		return retval;
	}

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	hsotg->regs = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(hsotg->regs))
		return PTR_ERR(hsotg->regs);

	dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
		(unsigned long)res->start, hsotg->regs);

	retval = dwc2_lowlevel_hw_init(hsotg);
	if (retval)
		return retval;

	spin_lock_init(&hsotg->lock);
	mutex_init(&hsotg->mtx_lock);

	hsotg->irq = platform_get_irq(dev, 0);
	if (hsotg->irq < 0)
		return hsotg->irq;

	dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
		hsotg->irq);
	retval = devm_request_irq(hsotg->dev, hsotg->irq,
				  dwc2_handle_common_intr, IRQF_SHARED,
				  dev_name(hsotg->dev), hsotg);
	if (retval)
		return retval;

	hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
	if (IS_ERR(hsotg->vbus_supply)) {
		retval = PTR_ERR(hsotg->vbus_supply);
		hsotg->vbus_supply = NULL;
		if (retval != -ENODEV)
			return retval;
	}

	retval = dwc2_lowlevel_hw_enable(hsotg);
	if (retval)
		return retval;

	hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);

	retval = dwc2_get_dr_mode(hsotg);
	if (retval)
		goto error;

	hsotg->need_phy_for_wake =
		of_property_read_bool(dev->dev.of_node,
				      "snps,need-phy-for-wake");
	hsotg->no_acchg_det =
		of_property_read_bool(dev->dev.of_node,
				      "snps,no-acchg-det");

	/*
	 * Reset before dwc2_get_hwparams() then it could get power-on real
	 * reset value form registers.
	 */
	retval = dwc2_core_reset(hsotg, false);
	if (retval)
		goto error;

	/* Detect config values from hardware */
	retval = dwc2_get_hwparams(hsotg);
	if (retval)
		goto error;

	/*
	 * For OTG cores, set the force mode bits to reflect the value
	 * of dr_mode. Force mode bits should not be touched at any
	 * other time after this.
	 */
	//dwc2_force_dr_mode(hsotg);
	retval = dwc2_init_params(hsotg);
	if (retval)
		goto error;

	if (hsotg->dr_mode != USB_DR_MODE_HOST) {
		dwc2_force_device_mode(hsotg);
		retval = dwc2_gadget_init(hsotg);
		if (retval)
			goto error;
		hsotg->gadget_enabled = 1;
	}

	/*
	 * If we need PHY for wakeup we must be wakeup capable.
	 * When we have a device that can wake without the PHY we
	 * can adjust this condition.
	 */
	if (hsotg->need_phy_for_wake)
		device_set_wakeup_capable(&dev->dev, true);

	if (!of_property_read_u32(dev->dev.of_node, "otg-force-host-mode", &data)) {
		dev_info(hsotg->dev, "otg force host mode\n");
		force_host = 1;
		force_dev = 0;
	} else if (!of_property_read_u32(dev->dev.of_node, "otg-force-dev-mode", &data)) {
		dev_info(hsotg->dev, "otg force dev mode\n");
		force_dev = 1;
		force_host = 0;
	}

	hsotg->reset_phy_on_wake =
		of_property_read_bool(dev->dev.of_node,
				      "snps,reset-phy-on-wake");
	if (hsotg->reset_phy_on_wake && !hsotg->phy) {
		dev_warn(hsotg->dev,
			 "Quirk reset-phy-on-wake only supports generic PHYs\n");
		hsotg->reset_phy_on_wake = false;
	}

	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
		hsotg_controller_reset(hsotg);
		dwc2_force_host_mode(hsotg);
		retval = dwc2_hcd_init(hsotg);
		if (retval) {
			if (hsotg->gadget_enabled)
				dwc2_hsotg_remove(hsotg);
			goto error;
		}
		hsotg->hcd_enabled = 1;
	}

	platform_set_drvdata(dev, hsotg);
	hsotg->hibernated = 0;

	dwc2_debugfs_init(hsotg);

	retval = sysfs_create_file(&dev->dev.kobj, &dev_attr_otg_mode.attr);
	if(retval){
		dev_err(&dev->dev, "create host_dev mode failed");
		goto error;
	}

	/* Gadget code manages lowlevel hw on its own */
	if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
		dwc2_lowlevel_hw_disable(hsotg);

#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
	/* Postponed adding a new gadget to the udc class driver list */
	if (hsotg->gadget_enabled) {
		retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
		if (retval) {
			hsotg->gadget.udc = NULL;
			dwc2_hsotg_remove(hsotg);
			goto error;
		}
	}
#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */

	hsotg->vbus_irq = platform_get_irq(dev, 1);
	if (hsotg->vbus_irq < 0) {
		dev_err(&dev->dev, "failed to get vbus irq\n");
		retval = -ENXIO;
		goto error;
	}

	retval = devm_request_threaded_irq(&dev->dev, hsotg->vbus_irq,
					NULL, vbus_irq,
					IRQF_ONESHOT | IRQF_NO_SUSPEND,
					"asr-usb-vbus", hsotg);
	if (retval) {
		dev_info(&dev->dev,
			"Can not request irq for VBUS\n");
		goto error;
	}

	usbid_irq_init(dev, hsotg);
	INIT_DELAYED_WORK(&hsotg->otg_work, usb_otg_work_fn);

	if (of_property_read_bool(node , "otg,use-gpio-vbus")) {
		if (of_property_read_u32(node , "gpio-num", &hsotg->gpio_num)) {
			hsotg->gpio_num = ENNUM;
			dev_info(&dev->dev, "failed to find GPIO number in dts\n");
		} else {
			if (gpio_request(hsotg->gpio_num, "OTGVBUS")) {
				dev_err(&dev->dev , "OTG Request GPIO failed, gpio: %d\n" ,
					hsotg->gpio_num);
				hsotg->gpio_num = ENNUM;
			} else
				gpio_direction_output(hsotg->gpio_num , 0);
		}
	} else
		hsotg->gpio_num = ENNUM;
/**
	prop = of_get_property(node, "lpm-qos", &proplen);
	if (!prop) {
		pr_err("lpm-qos for dwc otg is not defined\n");
		goto error;
	} else
		hsotg->lpm_qos = be32_to_cpup(prop);

	hsotg->qos_idle.name = "dwc2-otg";
	pm_qos_add_request(&hsotg->qos_idle, PM_QOS_CPUIDLE_BLOCK,
			PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE);
**/
	g_hsotg = hsotg;
	schedule_delayed_work(&g_hsotg->otg_work, HZ);
	g_hsotg->otg_state = OTG_STATE_B_IDLE;
	apmu_base = regs_addr_get_va(REGS_ADDR_APMU);
	writel(readl(apmu_base + APMU_USB_WAKE_CLR) | USB_VBUS_WAKE_EN
		| (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR),
		apmu_base + APMU_USB_WAKE_CLR);
	writel(readl(apmu_base + APMU_USB_WAKE_CLR)
		| (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR),
		apmu_base + APMU_USB_WAKE_CLR);

	device_init_wakeup(&dev->dev, 1);
	pm_stay_awake(&dev->dev);
	dev_info(hsotg->dev, "probe done\n");

	return 0;

error:
	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
		dwc2_lowlevel_hw_disable(hsotg);
	return retval;
}

static int __maybe_unused dwc2_suspend(struct device *dev)
{
	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
	bool is_device_mode = dwc2_is_device_mode(dwc2);
	int ret = 0;

	/* asr private */
	return 0;

	if (is_device_mode)
		dwc2_hsotg_suspend(dwc2);

	if (dwc2->ll_hw_enabled &&
	    (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
		ret = __dwc2_lowlevel_hw_disable(dwc2);
		dwc2->phy_off_for_suspend = true;
	}

	return ret;
}

static int __maybe_unused dwc2_resume(struct device *dev)
{
	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
	int ret = 0;

	/* asr private */
	return 0;

	if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
		ret = __dwc2_lowlevel_hw_enable(dwc2);
		if (ret)
			return ret;
	}
	dwc2->phy_off_for_suspend = false;

	if (dwc2_is_device_mode(dwc2))
		ret = dwc2_hsotg_resume(dwc2);

	return ret;
}

static int dwc2_noirq_suspend(struct device *dev)
{
	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
	void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);

	writel(readl(apmu_base + APMU_USB_WAKE_CLR)
		| (USB_VBUS_WAKE_CLR | USB_LINEST_WAKE_CLR | USB_ID_WAKE_CLR
		| USB_VBUS_WAKE_EN | USB_LINEST_WAKE_EN | USB_ID_WAKE_EN),
		apmu_base + APMU_USB_WAKE_CLR);

	if (dwc2->allow_suspend) {
		if (dwc2->lx_state == DWC2_L2)
			usb_phy_set_suspend2(dwc2->uphy, 1);
		else
			pr_info("dwc2 lx_state: %d\n", dwc2->lx_state);
	}

	enable_irq_wake(dwc2->vbus_irq);

	dwc2_release_pm_qos();
	return 0;
}

static int dwc2_noirq_resume(struct device *dev)
{
	volatile u32 value;
	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
	void __iomem *apmu_base = regs_addr_get_va(REGS_ADDR_APMU);

	if (dwc2->vbus_active)
		dwc2_acquire_pm_qos();

	disable_irq_wake(dwc2->vbus_irq);
	if (dwc2->allow_suspend) {
		if (dwc2->vbus_active) {
			usb_phy_set_suspend2(dwc2->uphy, 0);
		} else {
			pr_info("dwc2 vbus off, lx_state: %d\n", dwc2->lx_state);
		}
	}

	/* clear linestat wakeup and disable linestat/pmu wake en */
	value = readl(apmu_base + APMU_USB_WAKE_CLR);
	value |= (USB_LINEST_WAKE_CLR);
	writel(value, apmu_base + APMU_USB_WAKE_CLR);
	udelay(50);
	value = readl(apmu_base + APMU_USB_WAKE_CLR);
	value &= ~(USB_LINEST_WAKE_EN);
	writel(value, apmu_base + APMU_USB_WAKE_CLR);

	dev_info(dwc2->dev, "dwc2 resume\n");
	return 0;
}

static const struct dev_pm_ops dwc2_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dwc2_noirq_suspend, dwc2_noirq_resume)
};

static struct platform_driver dwc2_platform_driver = {
	.driver = {
		.name = dwc2_driver_name,
		.of_match_table = dwc2_of_match_table,
		.pm = &dwc2_dev_pm_ops,
	},
	.probe = dwc2_driver_probe,
	.remove = dwc2_driver_remove,
	.shutdown = dwc2_driver_shutdown,
};

module_platform_driver(dwc2_platform_driver);

MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
MODULE_LICENSE("Dual BSD/GPL");