b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/include/mach/pxa1928_ddrtable.h |
| 3 | * |
| 4 | * Copyright: (C) 2013 Marvell International Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | |
| 13 | #ifndef __PXA1928_DDRTABLE_H__ |
| 14 | #define __PXA1928_DDRTABLE_H__ |
| 15 | |
| 16 | struct ddr_regtbl { |
| 17 | u32 reg; |
| 18 | u32 b2c; |
| 19 | u32 b2s; |
| 20 | }; |
| 21 | |
| 22 | struct ddr_regtbl_info { |
| 23 | u32 array_size; |
| 24 | u32 timing_cnt; |
| 25 | }; |
| 26 | |
| 27 | enum ddr_regtbl_type { |
| 28 | DDR_TYPE_MT42L256M = 0, |
| 29 | DDR_TYPE_LPDDR3 = 1, |
| 30 | DDR_TYPE_INVALID = 255, |
| 31 | }; |
| 32 | |
| 33 | extern struct ddr_regtbl *mt42l256m32d2lg18_array[]; |
| 34 | extern struct ddr_regtbl *lpddr3_array[]; |
| 35 | |
| 36 | extern void pxa1928_ddrhwt_select_array(u32 ind); |
| 37 | extern int pxa1928_ddrhwt_get_freqnr(void); |
| 38 | extern int pxa1928_ddrhwt_get_timingcnt(void); |
| 39 | extern void pxa1928_ddrhwt_lpddr2_h2l(u32 *dmcu, struct ddr_regtbl *newtiming, |
| 40 | u32 timing_cnt, u32 table_index); |
| 41 | extern void pxa1928_ddrhwt_lpddr2_l2h(u32 *dmcu, struct ddr_regtbl *newtiming, |
| 42 | u32 timing_cnt, u32 table_index); |
| 43 | extern void pxa1928_register_table_lpddr2_dll_calibration(u32 *dmcu); |
| 44 | extern void pxa1928_enable_lpm_ddrdll_recalibration(void); |
| 45 | extern void pxa1928_ddrhwt_lpddr2_h2l_lowfreq(u32 *dmcu, |
| 46 | struct ddr_regtbl *newtiming, u32 timing_cnt, u32 table_index); |
| 47 | extern void pxa1928_ddrhwt_lpddr2_l2h_lowfreq(u32 *dmcu, |
| 48 | struct ddr_regtbl *newtiming, u32 timing_cnt, u32 table_index); |
| 49 | #endif |