| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/include/soc/asr/regs-accu.h |
| 3 | * |
| 4 | * Application Clock Control Unit |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_MACH_REGS_ACCU_H |
| 12 | #define __ASM_MACH_REGS_ACCU_H |
| 13 | |
| 14 | /* |
| 15 | * ACCU register offsets for PXA1986 |
| 16 | */ |
| 17 | #define ACCU_FABRIC_N1_CLK_CNTRL_REG (0x004) |
| 18 | #define ACCU_APPS_MDMA_CLK_CNTRL_REG (0x00C) |
| 19 | #define ACCU_APPS_STM_CLK_CNTRL_REG (0x010) |
| 20 | #define ACCU_APPS_IC_CLK_CNTRL_REG (0x014) |
| 21 | #define ACCU_WTM_MAIN_CLK_CNTRL_REG (0x018) |
| 22 | #define ACCU_WTM_CORE_CLK_CNTRL_REG (0x01C) |
| 23 | #define ACCU_WTM_CORE_BUS_CLK_CNTRL_REG (0x020) |
| 24 | #define ACCU_FABRIC_N2_CLK_CNTRL_REG (0x030) |
| 25 | #define ACCU_VID_DEC_CLK_CNTRL_REG (0x034) |
| 26 | #define ACCU_VID_ENC_CLK_CNTRL_REG (0x038) |
| 27 | #define ACCU_FABRIC_N3_CLK_CNTRL_REG (0x040) |
| 28 | #define ACCU_USB_CLK_CNTRL_REG (0x044) |
| 29 | #define ACCU_HSIC_CLK_CNTRL_REG (0x048) |
| 30 | #define ACCU_NAND_CLK_CNTRL_REG (0x04C) |
| 31 | #define ACCU_FABRIC_N4_CLK_CNTRL_REG (0x058) |
| 32 | #define ACCU_APPS_INT_SRAM_CLK_CNTRL_REG (0x05C) |
| 33 | #define ACCU_VDMA_CLK_CNTRL_REG (0x060) |
| 34 | #define ACCU_CI1_CCIC_CLK_CNTRL_REG (0x064) |
| 35 | #define ACCU_CI2_CCIC_CLK_CNTRL_REG (0x068) |
| 36 | #define ACCU_ISP_CLK_CNTRL_REG (0x06C) |
| 37 | #define ACCU_DISPLAY1_CLK_CNTRL_REG (0x074) |
| 38 | #define ACCU_DISPLAY2_CLK_CNTRL_REG (0x078) |
| 39 | #define ACCU_DISPLAY_UNIT_CLK_CNTRL_REG (0x07C) |
| 40 | #define ACCU_FABRIC_N5_CLK_CNTRL_REG (0x080) |
| 41 | #define ACCU_GC1_3D_CLK_CNTRL_REG (0x084) |
| 42 | #define ACCU_GC2_3D_CLK_CNTRL_REG (0x088) |
| 43 | #define ACCU_GC_2D_CLK_CNTRL_REG (0x08C) |
| 44 | #define ACCU_FABRIC_N6_CLK_CNTRL_REG (0x090) |
| 45 | #define ACCU_APPS_LSP_APB_CLK_CNTRL_REG (0x0A0) |
| 46 | #define ACCU_APPS_OW_CLK_CNTRL_REG (0x0A4) |
| 47 | #define ACCU_APPS_PWM01_CLK_CNTRL_REG (0x0A8) |
| 48 | #define ACCU_APPS_PWM23_CLK_CNTRL_REG (0x0AC) |
| 49 | #define ACCU_APPS_TIMERS1_CLK_CNTRL_REG (0x0B0) |
| 50 | #define ACCU_APPS_TIMERS2_CLK_CNTRL_REG (0x0B4) |
| 51 | #define ACCU_APPS_TIMERS3_CLK_CNTRL_REG (0x0B8) |
| 52 | #define ACCU_APPS_KP_CLK_CNTRL_REG (0x0C4) |
| 53 | #define ACCU_APPS_RTC_CLK_CNTRL_REG (0x0C8) |
| 54 | #define ACCU_APPS_SSP1_CLK_CNTRL_REG (0x0D0) |
| 55 | #define ACCU_APPS_SSP2_CLK_CNTRL_REG (0x0D4) |
| 56 | #define ACCU_APPS_I2C1_CLK_CNTRL_REG (0x0DC) |
| 57 | #define ACCU_APPS_I2C2_CLK_CNTRL_REG (0x0E0) |
| 58 | #define ACCU_APPS_I2C3_CLK_CNTRL_REG (0x0E4) |
| 59 | #define ACCU_APPS_I2C4_CLK_CNTRL_REG (0x0E8) |
| 60 | #define ACCU_APPS_I2C5_CLK_CNTRL_REG (0x0EC) |
| 61 | #define ACCU_APPS_UART1_CLK_CNTRL_REG (0x0F0) |
| 62 | #define ACCU_APPS_UART2_CLK_CNTRL_REG (0x0F4) |
| 63 | #define ACCU_APPS_UART3_CLK_CNTRL_REG (0x0F8) |
| 64 | #define ACCU_APPS_TEMP_S1_CLK_CNTRL_REG (0x100) |
| 65 | #define ACCU_APPS_TEMP_S2_CLK_CNTRL_REG (0x104) |
| 66 | #define ACCU_APPS_TEMP_S3_CLK_CNTRL_REG (0x108) |
| 67 | #define ACCU_APPS_CORE_B_CLK_CNTRL_REG (0x120) |
| 68 | #define ACCU_APPS_CORE_B_CLK_CNTRL2_REG (0x124) |
| 69 | #define ACCU_APPS_CORE_L_CLK_CNTRL_REG (0x12C) |
| 70 | #define ACCU_APPS_CORE_L_CLK_CNTRL2_REG (0x130) |
| 71 | #define ACCU_APPS_CORE_TOP_CLK_CNTRL_REG (0x138) |
| 72 | #define ACCU_APPS_CORE_CS_CLK_CNTRL_REG (0x13C) |
| 73 | #define ACCU_SDH_BUS_CLK_CNTRL_REG (0x170) |
| 74 | #define ACCU_SDH_CLK_CNTRL_REG (0x174) |
| 75 | #define ACCU_HSI_CLK_CNTRL_REG (0x17C) |
| 76 | |
| 77 | /* Common ACCU clock register bit definitions */ |
| 78 | #define ACCU_ST_BIT BIT(29) |
| 79 | #define ACCU_GO_BIT BIT(28) |
| 80 | |
| 81 | #define ACCU_AHBCLK BIT(10) |
| 82 | #define ACCU_APBCLK BIT(9) /* Bus Clock Enable */ |
| 83 | #define ACCU_FNCLK BIT(8) /* Functional Clock Enable */ |
| 84 | |
| 85 | #define ACCU_AHBRST BIT(2) |
| 86 | #define ACCU_APBRST BIT(1) |
| 87 | #define ACCU_RST BIT(0) /* Reset Generation */ |
| 88 | |
| 89 | /* Functional Clock Selection Mask */ |
| 90 | #define ACCU_RATIO_MASK (0xf << 20) |
| 91 | #define ACCU_SOURCE_MASK (0x7 << 16) |
| 92 | |
| 93 | /* Functional Clock Set */ |
| 94 | #define SET_ACCU_RATIO(x) (((x) & 0xf) << 20) |
| 95 | #define SET_ACCU_SOURCE(x) (((x) & 0x7) << 16) |
| 96 | |
| 97 | /* Functional Clock Get */ |
| 98 | #define GET_ACCU_RATIO(x) ((x & ACCU_RATIO_MASK) >> 20) |
| 99 | #define GET_ACCU_SOURCE(x) ((x & ACCU_SOURCE_MASK) >> 16) |
| 100 | |
| 101 | #define ACCU_GC3D_INTLCLK (1 << 12) |
| 102 | #define ACCU_GC3D_AHBCLK (1 << 11) |
| 103 | #define ACCU_GC3D_APBCLK (1 << 10) /* Bus Clock Enable */ |
| 104 | #define ACCU_GC3D_SHADERCLK (1 << 9) |
| 105 | #define ACCU_GC3D_FNCLK (1 << 8) /* Functional Clock Enable */ |
| 106 | |
| 107 | #endif /* __ASM_MACH_REGS_ACCU_H */ |