| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/include/soc/asr/regs-mcu.h |
| 3 | * |
| 4 | * Memory Control Unit |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_MACH_MCU_H |
| 12 | #define __ASM_MACH_MCU_H |
| 13 | |
| 14 | #include <soc/asr/addr-map.h> |
| 15 | |
| 16 | #if defined(CONFIG_CPU_MMP3) |
| 17 | #define FIXADDR(base, offset) ((u32 *)(((u32)base)+offset)) |
| 18 | #define DMCU_HWTCTRL(base) FIXADDR(base, 0x1c0) |
| 19 | #define DMCU_HWTDAT0(base) FIXADDR(base, 0x1c8) |
| 20 | #define DMCU_HWTDAT1(base) FIXADDR(base, 0x1cc) |
| 21 | #elif defined(CONFIG_CPU_PXA1928) |
| 22 | #define FIXADDR(base, offset) ((u32 *)(((u32)base)+offset)) |
| 23 | #define DMCU_HWTCTRL(base) FIXADDR(base, 0xc0) |
| 24 | #define DMCU_HWTDAT0(base) FIXADDR(base, 0xc4) |
| 25 | #define DMCU_HWTDAT1(base) FIXADDR(base, 0xc8) |
| 26 | #define DMCU_REG(x) FIXADDR(DMCU_VIRT_BASE, (x)) |
| 27 | #else |
| 28 | #define DMCU_VIRT_REG(x) (DMCU_VIRT_BASE + (x)) |
| 29 | #define DMCU_PHYS_REG(x) (DMCU_PHYS_BASE + (x)) |
| 30 | #define DMCU_HWTCTRL (0x1c0) |
| 31 | #define DMCU_HWTDAT0 (0x1c8) |
| 32 | #define DMCU_HWTDAT1 (0x1cc) |
| 33 | #endif |
| 34 | #define DMCU_HWTPAUSE (0x00010000) |
| 35 | #define DMCU_HWTEND (0x00020000) |
| 36 | #define DMCU_HWTWRITE (0x80000000) |
| 37 | |
| 38 | #define DMCU_CPU_ID_REV (0x00) |
| 39 | #define DMCU_STATUS (0x04) |
| 40 | #define DMCU_DRAM_STATUS (0x08) |
| 41 | |
| 42 | #define DMCU_DRAM_STATUS_PD (4) |
| 43 | #define DMCU_DRAM_STATUS_DPD (2) |
| 44 | #define DMCU_DRAM_STATUS_SR (1) |
| 45 | |
| 46 | #ifdef CONFIG_CPU_PXA1928 |
| 47 | #define DMCU_MAP_CS0 (0x200) |
| 48 | #define DMCU_MAP_CS1 (0x204) |
| 49 | #else |
| 50 | #define DMCU_MAP_CS0 (0x10) |
| 51 | #define DMCU_MAP_CS1 (0x14) |
| 52 | #endif |
| 53 | |
| 54 | #define DMCU_MAP_VALID (1u << 0) |
| 55 | #define DMCU_CMD_CSSEL_CS0 (1u << 24) |
| 56 | #define DMCU_CMD_CSSEL_CS1 (1u << 25) |
| 57 | |
| 58 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 59 | #define DMCU_MAP_CS2 (0x18) |
| 60 | #define DMCU_MAP_CS3 (0x1c) |
| 61 | #endif |
| 62 | |
| 63 | #define DMCU_SDRAM_CFG0_TYPE1 (0x20) |
| 64 | #define DMCU_SDRAM_CFG1_TYPE1 (0x24) |
| 65 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 66 | #define DMCU_SDRAM_CFG2_TYPE1 (0x28) |
| 67 | #define DMCU_SDRAM_CFG3_TYPE1 (0x2c) |
| 68 | #endif |
| 69 | |
| 70 | #define DMCU_SDRAM_CFG0_TYPE2 (0x30) |
| 71 | #define DMCU_SDRAM_CFG1_TYPE2 (0x34) |
| 72 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 73 | #define DMCU_SDRAM_CFG2_TYPE2 (0x38) |
| 74 | #define DMCU_SDRAM_CFG3_TYPE2 (0x3c) |
| 75 | #endif |
| 76 | |
| 77 | #define DMCU_SDRAM_CTRL1 (0x50) |
| 78 | #define DMCU_SDRAM_CTRL2 (0x54) |
| 79 | #define DMCU_SDRAM_CTRL4 (0x58) |
| 80 | #define DMCU_SDRAM_TYPE_MASK (7u << 2) |
| 81 | #define DMCU_SDRAM_TYPE_DDR3 (2u << 2) |
| 82 | #define DMCU_SDRAM_TYPE_LPDDR2 (5u << 2) |
| 83 | #define DMCU_SDRAM_CTRL4_CL_SHIFT (13) |
| 84 | #define DMCU_SDRAM_CTRL4_CL_MASK (0xf << DMCU_SDRAM_CTRL4_CL_SHIFT) |
| 85 | #define DMCU_SDRAM_CTRL4_BL_SHIFT (22) |
| 86 | #define DMCU_SDRAM_CTRL4_BL_MASK (0x3 << DMCU_SDRAM_CTRL4_BL_SHIFT) |
| 87 | #define DMCU_SDRAM_CTRL6 (0x5c) |
| 88 | #define DMCU_SDRAM_CTRL7 (0x60) |
| 89 | #define DMCU_SDRAM_CTRL13 (0x64) |
| 90 | #define DMCU_SDRAM_CTRL14 (0x68) |
| 91 | |
| 92 | #ifdef CONFIG_CPU_PXA1928 |
| 93 | #define DMCU_SDRAM_TIMING1 (0x300) |
| 94 | #define DMCU_SDRAM_TIMING2 (0x380) |
| 95 | #define DMCU_SDRAM_TIMING3 (0x384) |
| 96 | #define DMCU_SDRAM_TIMING4 (0x388) |
| 97 | #define DMCU_SDRAM_TIMING5 (0x38c) |
| 98 | #define DMCU_SDRAM_TIMING6 (0x390) |
| 99 | #define DMCU_SDRAM_TIMING7 (0x394) |
| 100 | #define DMCU_SDRAM_TIMING8 (0x398) |
| 101 | #define DMCU_SDRAM_TIMING9 (0x39c) |
| 102 | #define DMCU_SDRAM_TIMING10 (0x3a0) |
| 103 | #define DMCU_SDRAM_TIMING11 (0x3a4) |
| 104 | #define DMCU_SDRAM_TIMING12 (0x3a8) |
| 105 | #define DMCU_SDRAM_TIMING13 (0x500) |
| 106 | #define DMCU_SDRAM_TIMING14 (0x504) |
| 107 | #define DMCU_SDRAM_TIMING15 (0x508) |
| 108 | #define DMCU_SDRAM_TIMING16 (0x50c) |
| 109 | #else |
| 110 | #define DMCU_SDRAM_TIMING1 (0x80) |
| 111 | #define DMCU_SDRAM_TIMING2 (0x84) |
| 112 | #define DMCU_SDRAM_TIMING3 (0x88) |
| 113 | #define DMCU_SDRAM_TIMING4 (0x8c) |
| 114 | #define DMCU_SDRAM_TIMING5 (0x90) |
| 115 | #define DMCU_SDRAM_TIMING6 (0x94) |
| 116 | #define DMCU_SDRAM_TIMING7 (0x98) |
| 117 | #define DMCU_SDRAM_TIMING8 (0x9c) |
| 118 | #endif |
| 119 | |
| 120 | #define DMCU_EXCLUSIVE_MONITOR_CTRL (0x100) |
| 121 | #define DMCU_DATA_COH_CTRL (0x110) |
| 122 | #define DMCU_TRUSTZONE_SEL (0x120) |
| 123 | #define DMCU_TRUSTZONE_RANGE0 (0x124) |
| 124 | #define DMCU_TRUSTZONE_RANGE1 (0x128) |
| 125 | #define DMCU_TRUSTZONE_PERMISSION (0x12C) |
| 126 | #define DMCU_PORT_PRIORITY (0x140) |
| 127 | #define DMCU_BQ_STARV_PREVENTION (0x144) |
| 128 | #define DMCU_RRB_STARV_PREVENTION0 (0x148) |
| 129 | #define DMCU_RRB_STARV_PREVENTION1 (0x14C) |
| 130 | #define DMCU_SRAM_CTRL1 (0x150) |
| 131 | #define DMCU_SRAM_CTRL2 (0x154) |
| 132 | #define DMCU_SRAM_CTRL3 (0x158) |
| 133 | |
| 134 | #ifdef CONFIG_CPU_PXA1928 |
| 135 | #define DMCU_USER_COMMAND0 (0x20) |
| 136 | #define DMCU_USER_COMMAND1 (0x24) |
| 137 | #else |
| 138 | #define DMCU_USER_COMMAND0 (0x160) |
| 139 | #define DMCU_USER_COMMAND1 (0x164) |
| 140 | #endif |
| 141 | |
| 142 | #define DMCU_MODE_RD_DATA (0x170) |
| 143 | |
| 144 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 145 | #define DMCU_SMR1 (0x180) |
| 146 | #define DMCU_SMR2 (0x184) |
| 147 | #endif |
| 148 | |
| 149 | #if defined(CONFIG_CPU_PXA1928) |
| 150 | #define DMCU_CTRL_0 (0x044) |
| 151 | #define DMCU_CH0_PMAP0 (0x210) |
| 152 | #define DMCU_PHY_CTRL3 (0x408) |
| 153 | #define DMCU_PHY_CTRL8 (0x41c) |
| 154 | #define DMCU_PHY_CTRL9 (0x420) |
| 155 | #define DMCU_PHY_CTRL10 (0x424) |
| 156 | #define DMCU_PHY_CTRL11 (0x428) |
| 157 | #else |
| 158 | #define DMCU_PHY_CTRL3 (0x220) |
| 159 | #define DMCU_PHY_CTRL7 (0x230) |
| 160 | #define DMCU_PHY_CTRL8 (0x234) |
| 161 | #define DMCU_PHY_CTRL9 (0x238) |
| 162 | #define DMCU_PHY_CTRL10 (0x23c) |
| 163 | #define DMCU_PHY_CTRL11 (0x240) |
| 164 | #endif |
| 165 | |
| 166 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 167 | #define DMCU_PHY_CTRL12 (0x244) |
| 168 | #endif |
| 169 | |
| 170 | #define DMCU_PHY_CTRL13 (0x248) |
| 171 | #define DMCU_PHY_CTRL14 (0x24c) |
| 172 | #define DMCU_PHY_CTRL15 (0x250) |
| 173 | #define DMCU_PHY_CTRL16 (0x254) |
| 174 | #define DMCU_PHY_CTRL21 (0x258) |
| 175 | #define DMCU_PHY_CTRL19 (0x280) |
| 176 | #define DMCU_PHY_CTRL20 (0x284) |
| 177 | #define DMCU_PHY_CTRL22 (0x288) |
| 178 | #define DMCU_PHY_DQ_BYTE_SEL (0x300) |
| 179 | #define DMCU_PHY_DLL_CTRL_BYTE1 (0x304) |
| 180 | #define DMCU_PHY_DLL_WL_SEL (0x380) |
| 181 | #define DMCU_PHY_DLL_WL_CTRL0 (0x384) |
| 182 | #define DMCU_PHY_DLL_WL_CTRL1 (0x388) |
| 183 | #define DMCU_PHY_DLL_WL_CTRL2 (0x38C) |
| 184 | #define DMCU_PHY_DLL_RL_CTRL (0x390) |
| 185 | |
| 186 | #define PHY_CTRL14_DLL_RESET (1u << 29) |
| 187 | #define PHY_CTRL14_DLL_UPDATE (1u << 30) |
| 188 | #define PHY_CTRL14_PHY_SYNC (1u << 31) |
| 189 | |
| 190 | #if defined(CONFIG_CPU_PXA988) || defined(CONFIG_CPU_PXA1088) |
| 191 | #define DMCU_PHY_CTRL_TESTMODE (0x400) |
| 192 | #endif |
| 193 | |
| 194 | #define DMCU_TEST_MODE0 (0x410) |
| 195 | #define DMCU_TEST_MODE1 (0x414) |
| 196 | #define DMCU_PERF_CNT_CTRL0 (0x440) |
| 197 | #define DMCU_PERF_CNT_STATUS (0x444) |
| 198 | #define DMCU_PERF_CNT_SEL (0x448) |
| 199 | #define DMCU_PERF_CNT0 (0x450) |
| 200 | #define DMCU_PERF_CNT1 (0x454) |
| 201 | #define DMCU_PERF_CNT2 (0x458) |
| 202 | #define DMCU_PERF_CNT3 (0x45c) |
| 203 | |
| 204 | #endif /* __ASM_MACH_MCU_H */ |