| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/include/soc/asr/regs-mpmu.h |
| 3 | * |
| 4 | * Main Power Management Unit |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_MACH_REGS_MPMU_H |
| 12 | #define __ASM_MACH_REGS_MPMU_H |
| 13 | |
| 14 | #ifdef CONFIG_CPU_PXA1986 |
| 15 | /* |
| 16 | * MPMU_PCR_0 : used by the Cortex-A7 CPU0 Apps Subsystem |
| 17 | * MPMU_PCR_1 : used by the Secure Processor subsystem |
| 18 | * MPMU_PCR_2 : used by the Comm Cortex R-5 subsystem core (aka CP1) |
| 19 | * MPMU_PCR_3 : used by the Comm MSA subsystem (aka CP2) |
| 20 | * MPMU_PCR_4 : used by the Audio subsystem |
| 21 | */ |
| 22 | #define MPMU_PCR_0 (0x0000) |
| 23 | #define MPMU_PCR_1 (0x0004) |
| 24 | #define MPMU_PCR_2 (0x0008) |
| 25 | #define MPMU_PCR_3 (0x000C) |
| 26 | #define MPMU_PCR_4 (0x0010) |
| 27 | #define MPMU_VCXOCR (0x0014) |
| 28 | #define MPMU_DFCCR (0x0018) |
| 29 | #define MPMU_PLL1DLY (0x001C) |
| 30 | #define MPMU_PLL2DLY (0x0020) |
| 31 | #define MPMU_PLLDDLY (0x0024) |
| 32 | #define MPMU_PLLADLY (0x0028) |
| 33 | #define MPMU_ANAGCR (0x002C) |
| 34 | #define MPMU_MCKCR (0x0030) |
| 35 | #define MPMU_EXVCXOCR (0x0034) |
| 36 | #define MPMU_RSTOCR (0x0038) |
| 37 | #define MPMU_AP_PLLREQ (0x003C) |
| 38 | #define MPMU_CP_PLLREQ (0x0040) |
| 39 | #define MPMU_AUD_PLLREQ (0x0044) |
| 40 | #define MPMU_SRD_PLLREQ (0x0048) |
| 41 | #define MPMU_RSTSR (0x004C) |
| 42 | #define MPMU_PWRDLY (0x0050) |
| 43 | #define MPMU_CKEN32K (0x0054) |
| 44 | #define MPMU_RST32K (0x0058) |
| 45 | #define MPMU_CPCTL (0x005C) |
| 46 | #define MPMU_AUDSSCR (0x0060) |
| 47 | #define MPMU_RSRV1 (0x0064) |
| 48 | #define MPMU_PLLSTAT (0x0068) |
| 49 | #define MPMU_SLPIND_CR (0x006C) |
| 50 | #define MPMU_PLL1_CF1 (0x0070) |
| 51 | #define MPMU_PLL1_CF2 (0x0074) |
| 52 | #define MPMU_PLL2_CF1 (0x0078) |
| 53 | #define MPMU_PLL2_CF2 (0x007C) |
| 54 | #define MPMU_PLL2_CF3 (0x0080) |
| 55 | #define MPMU_PLLD_CF1 (0x0084) |
| 56 | #define MPMU_PLLD_CF2 (0x0088) |
| 57 | #define MPMU_PLLD_CF3 (0x008C) |
| 58 | #define MPMU_PLLD_CF4 (0x0090) |
| 59 | #define MPMU_PLLA_CF1 (0x0094) |
| 60 | #define MPMU_PLLA_CF2 (0x0098) |
| 61 | #define MPMU_PCSTAT (0x00A0) |
| 62 | #define MPMU_PLL1FCGO (0x00A4) |
| 63 | #define MPMU_PLL2FCGO (0x00A8) |
| 64 | #define MPMU_PLLDFCGO (0x00AC) |
| 65 | #define MPMU_PLLAFCGO (0x00B0) |
| 66 | #define MPMU_LPMUDLY0 (0x00B4) |
| 67 | #define MPMU_LPMUDLY1 (0x00B8) |
| 68 | #define MPMU_LPMUDLY2 (0x00BC) |
| 69 | #define MPMU_TROPCR (0x00C0) |
| 70 | #define MPMU_AUD_PMUDLY (0x00C4) |
| 71 | #define MPMU_TRO_PMUDLY (0x00C8) |
| 72 | #define MPMU_CK32KCR (0x00CC) |
| 73 | #define MPMU_MIPSHL_CR (0x00D0) |
| 74 | #define MPMU_RSRV2 (0x00D4) |
| 75 | #define MPMU_IOPADCR (0x00D8) |
| 76 | #define MPMU_PLL1SEL (0x00DC) |
| 77 | #define MPMU_WKUP_STAT (0x00E0) |
| 78 | #define MPMU_GENSW1 (0x00E4) |
| 79 | #define MPMU_GENSW2 (0x00E8) |
| 80 | #define MPMU_GENSW3 (0x00EC) |
| 81 | #define MPMU_GENSW4 (0x00F0) |
| 82 | #define MPMU_AUDVDLY (0x00F4) |
| 83 | #define MPMU_AVS_SNSCR (0x00F8) |
| 84 | /* |
| 85 | * MPMU_PCR_AP_1 : used by the Cortex-A7 CPU1 Apps Subsystem |
| 86 | * MPMU_PCR_AP_2 : used by the Cortex-A15 CPU0 Apps Subsystem |
| 87 | * MPMU_PCR_AP_3 : used by the Cortex-A15 CPU1 Apps Subsystem |
| 88 | */ |
| 89 | #define MPMU_PCR_AP_1 (0x0100) |
| 90 | #define MPMU_PCR_AP_2 (0x0104) |
| 91 | #define MPMU_PCR_AP_3 (0x0108) |
| 92 | #define MAVS_LVDDL (0x0120) |
| 93 | #define MAVS_HVDDL (0x0124) |
| 94 | #define MAVS_DELTA (0x0128) |
| 95 | #define MAVS_SPDT_0 (0x012C) |
| 96 | #define MAVS_SPDT_1 (0x0130) |
| 97 | #define MAVS_EN_GEN (0x0134) |
| 98 | #define MAVS_VC (0x0138) |
| 99 | #define MAVS_GP1 (0x013C) |
| 100 | #define MAVS_GP2 (0x0140) |
| 101 | #define MAVS_DRO_CFG (0x0144) |
| 102 | #define MAVS_TP (0x0148) |
| 103 | #define MAVS_DRO_CNT_STATUS1 (0x014C) |
| 104 | #define MAVS_DRO_CNT_STATUS2 (0x0150) |
| 105 | #define MAVS_STATUS1 (0x0154) |
| 106 | #define MAVS_STATUS2 (0x0158) |
| 107 | #define CAVS_LVDDL (0x0160) |
| 108 | #define CAVS_HVDDL (0x0164) |
| 109 | #define CAVS_DELTA (0x0168) |
| 110 | #define CAVS_SPDT_0 (0x016C) |
| 111 | #define CAVS_SPDT_1 (0x0170) |
| 112 | #define CAVS_EN_GEN (0x0174) |
| 113 | #define CAVS_VC (0x0178) |
| 114 | #define CAVS_GP1 (0x017C) |
| 115 | #define CAVS_GP2 (0x0180) |
| 116 | #define CAVS_DRO_CFG (0x0184) |
| 117 | #define CAVS_TP (0x0188) |
| 118 | #define CAVS_DRO_CNT_STATUS1 (0x018C) |
| 119 | #define CAVS_DRO_CNT_STATUS2 (0x0190) |
| 120 | #define CAVS_STATUS1 (0x0194) |
| 121 | #define CAVS_STATUS2 (0x0198) |
| 122 | #define GAVS_LVDDL (0x01A0) |
| 123 | #define GAVS_HVDDL (0x01A4) |
| 124 | #define GAVS_DELTA (0x01A8) |
| 125 | #define GAVS_SPDT_0 (0x01AC) |
| 126 | #define GAVS_SPDT_1 (0x01B0) |
| 127 | #define GAVS_EN_GEN (0x01B4) |
| 128 | #define GAVS_VC (0x01B8) |
| 129 | #define GAVS_GP1 (0x01BC) |
| 130 | #define GAVS_GP2 (0x01C0) |
| 131 | #define GAVS_DRO_CFG (0x01C4) |
| 132 | #define GAVS_TP (0x01C8) |
| 133 | #define GAVS_DRO_CNT_STATUS1 (0x01CC) |
| 134 | #define GAVS_DRO_CNT_STATUS2 (0x01D0) |
| 135 | #define GAVS_STATUS1 (0x01D4) |
| 136 | #define GAVS_STATUS2 (0x01D8) |
| 137 | #define MDRO_CLCTR_CTL (0x01E0) |
| 138 | #define CDRO_CLCTR_CTL (0x01E4) |
| 139 | #define GDRO_CLCTR_CTL (0x01E8) |
| 140 | #endif /* CONFIG_CPU_PXA1986 */ |
| 141 | |
| 142 | #endif /* __ASM_MACH_REGS_MPMU_H */ |