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192.168.1.100 / T108 / e958203796650e3959a43708d67534bf36f4c83b / . / marvell / linux / sound / soc / codecs / mt6358.c
blob: 494ba0eeb433630e377e5b0fd5733cd2774b1521 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2//
3// mt6358.c -- mt6358 ALSA SoC audio codec driver
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/platform_device.h>
9#include <linux/module.h>
10#include <linux/of_device.h>
11#include <linux/delay.h>
12#include <linux/kthread.h>
13#include <linux/sched.h>
14#include <linux/mfd/mt6397/core.h>
15#include <linux/regulator/consumer.h>
16
17#include <sound/soc.h>
18#include <sound/tlv.h>
19
20#include "mt6358.h"
21
22enum {
23 AUDIO_ANALOG_VOLUME_HSOUTL,
24 AUDIO_ANALOG_VOLUME_HSOUTR,
25 AUDIO_ANALOG_VOLUME_HPOUTL,
26 AUDIO_ANALOG_VOLUME_HPOUTR,
27 AUDIO_ANALOG_VOLUME_LINEOUTL,
28 AUDIO_ANALOG_VOLUME_LINEOUTR,
29 AUDIO_ANALOG_VOLUME_MICAMP1,
30 AUDIO_ANALOG_VOLUME_MICAMP2,
31 AUDIO_ANALOG_VOLUME_TYPE_MAX
32};
33
34enum {
35 MUX_ADC_L,
36 MUX_ADC_R,
37 MUX_PGA_L,
38 MUX_PGA_R,
39 MUX_MIC_TYPE,
40 MUX_HP_L,
41 MUX_HP_R,
42 MUX_NUM,
43};
44
45enum {
46 DEVICE_HP,
47 DEVICE_LO,
48 DEVICE_RCV,
49 DEVICE_MIC1,
50 DEVICE_MIC2,
51 DEVICE_NUM
52};
53
54/* Supply widget subseq */
55enum {
56 /* common */
57 SUPPLY_SEQ_CLK_BUF,
58 SUPPLY_SEQ_AUD_GLB,
59 SUPPLY_SEQ_CLKSQ,
60 SUPPLY_SEQ_VOW_AUD_LPW,
61 SUPPLY_SEQ_AUD_VOW,
62 SUPPLY_SEQ_VOW_CLK,
63 SUPPLY_SEQ_VOW_LDO,
64 SUPPLY_SEQ_TOP_CK,
65 SUPPLY_SEQ_TOP_CK_LAST,
66 SUPPLY_SEQ_AUD_TOP,
67 SUPPLY_SEQ_AUD_TOP_LAST,
68 SUPPLY_SEQ_AFE,
69 /* capture */
70 SUPPLY_SEQ_ADC_SUPPLY,
71};
72
73enum {
74 CH_L = 0,
75 CH_R,
76 NUM_CH,
77};
78
79#define REG_STRIDE 2
80
81struct mt6358_priv {
82 struct device *dev;
83 struct regmap *regmap;
84
85 unsigned int dl_rate;
86 unsigned int ul_rate;
87
88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
89 unsigned int mux_select[MUX_NUM];
90
91 int dev_counter[DEVICE_NUM];
92
93 int mtkaif_protocol;
94
95 struct regulator *avdd_reg;
96};
97
98int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
99 int mtkaif_protocol)
100{
101 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
102
103 priv->mtkaif_protocol = mtkaif_protocol;
104 return 0;
105}
106EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
107
108static void playback_gpio_set(struct mt6358_priv *priv)
109{
110 /* set gpio mosi mode */
111 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
112 0x01f8, 0x01f8);
113 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
114 0xffff, 0x0249);
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
116 0xffff, 0x0249);
117}
118
119static void playback_gpio_reset(struct mt6358_priv *priv)
120{
121 /* set pad_aud_*_mosi to GPIO mode and dir input
122 * reason:
123 * pad_aud_dat_mosi*, because the pin is used as boot strap
124 * don't clean clk/sync, for mtkaif protocol 2
125 */
126 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
127 0x01f8, 0x01f8);
128 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
129 0x01f8, 0x0000);
130 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
131 0xf << 8, 0x0);
132}
133
134static void capture_gpio_set(struct mt6358_priv *priv)
135{
136 /* set gpio miso mode */
137 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
138 0xffff, 0xffff);
139 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
140 0xffff, 0x0249);
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
142 0xffff, 0x0249);
143}
144
145static void capture_gpio_reset(struct mt6358_priv *priv)
146{
147 /* set pad_aud_*_miso to GPIO mode and dir input
148 * reason:
149 * pad_aud_clk_miso, because when playback only the miso_clk
150 * will also have 26m, so will have power leak
151 * pad_aud_dat_miso*, because the pin is used as boot strap
152 */
153 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
154 0xffff, 0xffff);
155 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
156 0xffff, 0x0000);
157 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
158 0xf << 12, 0x0);
159}
160
161/* use only when not govern by DAPM */
162static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
163{
164 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
165 0x1 << RG_XO_AUDIO_EN_M_SFT,
166 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
167 return 0;
168}
169
170/* use only when not govern by DAPM */
171static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
172{
173 /* audio clk source from internal dcxo */
174 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
175 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
176 0x0);
177
178 /* Enable/disable CLKSQ 26MHz */
179 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
180 RG_CLKSQ_EN_MASK_SFT,
181 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
182 return 0;
183}
184
185/* use only when not govern by DAPM */
186static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
187{
188 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
189 RG_AUDGLB_PWRDN_VA28_MASK_SFT,
190 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
191 return 0;
192}
193
194/* use only when not govern by DAPM */
195static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
196{
197 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
198 0x0066, enable ? 0x0 : 0x66);
199 return 0;
200}
201
202static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
203{
204 switch (priv->mtkaif_protocol) {
205 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
206 /* MTKAIF TX format setting */
207 regmap_update_bits(priv->regmap,
208 MT6358_AFE_ADDA_MTKAIF_CFG0,
209 0xffff, 0x0010);
210 /* enable aud_pad TX fifos */
211 regmap_update_bits(priv->regmap,
212 MT6358_AFE_AUD_PAD_TOP,
213 0xff00, 0x3800);
214 regmap_update_bits(priv->regmap,
215 MT6358_AFE_AUD_PAD_TOP,
216 0xff00, 0x3900);
217 break;
218 case MT6358_MTKAIF_PROTOCOL_2:
219 /* MTKAIF TX format setting */
220 regmap_update_bits(priv->regmap,
221 MT6358_AFE_ADDA_MTKAIF_CFG0,
222 0xffff, 0x0010);
223 /* enable aud_pad TX fifos */
224 regmap_update_bits(priv->regmap,
225 MT6358_AFE_AUD_PAD_TOP,
226 0xff00, 0x3100);
227 break;
228 case MT6358_MTKAIF_PROTOCOL_1:
229 default:
230 /* MTKAIF TX format setting */
231 regmap_update_bits(priv->regmap,
232 MT6358_AFE_ADDA_MTKAIF_CFG0,
233 0xffff, 0x0000);
234 /* enable aud_pad TX fifos */
235 regmap_update_bits(priv->regmap,
236 MT6358_AFE_AUD_PAD_TOP,
237 0xff00, 0x3100);
238 break;
239 }
240 return 0;
241}
242
243static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
244{
245 /* disable aud_pad TX fifos */
246 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
247 0xff00, 0x3000);
248 return 0;
249}
250
251int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
252{
253 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
254
255 playback_gpio_set(priv);
256 capture_gpio_set(priv);
257 mt6358_mtkaif_tx_enable(priv);
258
259 mt6358_set_dcxo(priv, true);
260 mt6358_set_aud_global_bias(priv, true);
261 mt6358_set_clksq(priv, true);
262 mt6358_set_topck(priv, true);
263
264 /* set dat_miso_loopback on */
265 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
266 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
267 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
268 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
269 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
270 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
271 return 0;
272}
273EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable);
274
275int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
276{
277 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
278
279 /* set dat_miso_loopback off */
280 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
281 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
282 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
283 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
284 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
285 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
286
287 mt6358_set_topck(priv, false);
288 mt6358_set_clksq(priv, false);
289 mt6358_set_aud_global_bias(priv, false);
290 mt6358_set_dcxo(priv, false);
291
292 mt6358_mtkaif_tx_disable(priv);
293 playback_gpio_reset(priv);
294 capture_gpio_reset(priv);
295 return 0;
296}
297EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable);
298
299int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
300 int phase_1, int phase_2)
301{
302 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
303
304 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
305 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
306 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
307 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
308 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
309 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
310 return 0;
311}
312EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase);
313
314/* dl pga gain */
315enum {
316 DL_GAIN_8DB = 0,
317 DL_GAIN_0DB = 8,
318 DL_GAIN_N_1DB = 9,
319 DL_GAIN_N_10DB = 18,
320 DL_GAIN_N_40DB = 0x1f,
321};
322
323#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
324#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
325#define DL_GAIN_REG_MASK 0x0f9f
326
327static void hp_zcd_disable(struct mt6358_priv *priv)
328{
329 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
330}
331
332static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
333{
334 int i = 0, stage = 0;
335 int target = 7;
336
337 /* Enable/Reduce HPL/R main output stage step by step */
338 for (i = 0; i <= target; i++) {
339 stage = up ? i : target - i;
340 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
341 0x7 << 8, stage << 8);
342 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
343 0x7 << 11, stage << 11);
344 usleep_range(100, 150);
345 }
346}
347
348static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
349{
350 int i = 0, stage = 0;
351
352 /* Reduce HP aux feedback loop gain step by step */
353 for (i = 0; i <= 0xf; i++) {
354 stage = up ? i : 0xf - i;
355 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
356 0xf << 12, stage << 12);
357 usleep_range(100, 150);
358 }
359}
360
361static void hp_pull_down(struct mt6358_priv *priv, bool enable)
362{
363 int i;
364
365 if (enable) {
366 for (i = 0x0; i <= 0x6; i++) {
367 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
368 0x7, i);
369 usleep_range(600, 700);
370 }
371 } else {
372 for (i = 0x6; i >= 0x1; i--) {
373 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
374 0x7, i);
375 usleep_range(600, 700);
376 }
377 }
378}
379
380static bool is_valid_hp_pga_idx(int reg_idx)
381{
382 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
383 reg_idx == DL_GAIN_N_40DB;
384}
385
386static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
387{
388 int offset = 0, count = 0, reg_idx;
389
390 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
391 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
392 __func__, from, to);
393
394 dev_info(priv->dev, "%s(), from %d, to %d\n",
395 __func__, from, to);
396
397 if (to > from)
398 offset = to - from;
399 else
400 offset = from - to;
401
402 while (offset >= 0) {
403 if (to > from)
404 reg_idx = from + count;
405 else
406 reg_idx = from - count;
407
408 if (is_valid_hp_pga_idx(reg_idx)) {
409 regmap_update_bits(priv->regmap,
410 MT6358_ZCD_CON2,
411 DL_GAIN_REG_MASK,
412 (reg_idx << 7) | reg_idx);
413 usleep_range(200, 300);
414 }
415 offset--;
416 count++;
417 }
418}
419
420static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
421 struct snd_ctl_elem_value *ucontrol)
422{
423 struct snd_soc_component *component =
424 snd_soc_kcontrol_component(kcontrol);
425 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
426 struct soc_mixer_control *mc =
427 (struct soc_mixer_control *)kcontrol->private_value;
428 unsigned int reg;
429 int ret;
430
431 ret = snd_soc_put_volsw(kcontrol, ucontrol);
432 if (ret < 0)
433 return ret;
434
435 switch (mc->reg) {
436 case MT6358_ZCD_CON2:
437 regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
438 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
439 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
440 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
441 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
442 break;
443 case MT6358_ZCD_CON1:
444 regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
445 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
446 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
447 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
448 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
449 break;
450 case MT6358_ZCD_CON3:
451 regmap_read(priv->regmap, MT6358_ZCD_CON3, &reg);
452 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
453 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
454 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
455 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
456 break;
457 case MT6358_AUDENC_ANA_CON0:
458 case MT6358_AUDENC_ANA_CON1:
459 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &reg);
460 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
461 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
462 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &reg);
463 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
464 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
465 break;
466 }
467
468 return ret;
469}
470
471static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
472static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
473
474static const struct snd_kcontrol_new mt6358_snd_controls[] = {
475 /* dl pga gain */
476 SOC_DOUBLE_EXT_TLV("Headphone Volume",
477 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
478 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
479 SOC_DOUBLE_EXT_TLV("Lineout Volume",
480 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
481 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
482 SOC_SINGLE_EXT_TLV("Handset Volume",
483 MT6358_ZCD_CON3, 0, 0x12, 1,
484 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
485 /* ul pga gain */
486 SOC_DOUBLE_R_EXT_TLV("PGA Volume",
487 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
488 8, 4, 0,
489 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
490};
491
492/* MUX */
493/* LOL MUX */
494static const char * const lo_in_mux_map[] = {
495 "Open", "Mute", "Playback", "Test Mode"
496};
497
498static int lo_in_mux_map_value[] = {
499 0x0, 0x1, 0x2, 0x3,
500};
501
502static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
503 MT6358_AUDDEC_ANA_CON7,
504 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
505 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
506 lo_in_mux_map,
507 lo_in_mux_map_value);
508
509static const struct snd_kcontrol_new lo_in_mux_control =
510 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
511
512/*HP MUX */
513enum {
514 HP_MUX_OPEN = 0,
515 HP_MUX_HPSPK,
516 HP_MUX_HP,
517 HP_MUX_TEST_MODE,
518 HP_MUX_HP_IMPEDANCE,
519 HP_MUX_MASK = 0x7,
520};
521
522static const char * const hp_in_mux_map[] = {
523 "Open",
524 "LoudSPK Playback",
525 "Audio Playback",
526 "Test Mode",
527 "HP Impedance",
528 "undefined1",
529 "undefined2",
530 "undefined3",
531};
532
533static int hp_in_mux_map_value[] = {
534 HP_MUX_OPEN,
535 HP_MUX_HPSPK,
536 HP_MUX_HP,
537 HP_MUX_TEST_MODE,
538 HP_MUX_HP_IMPEDANCE,
539 HP_MUX_OPEN,
540 HP_MUX_OPEN,
541 HP_MUX_OPEN,
542};
543
544static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
545 SND_SOC_NOPM,
546 0,
547 HP_MUX_MASK,
548 hp_in_mux_map,
549 hp_in_mux_map_value);
550
551static const struct snd_kcontrol_new hpl_in_mux_control =
552 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
553
554static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
555 SND_SOC_NOPM,
556 0,
557 HP_MUX_MASK,
558 hp_in_mux_map,
559 hp_in_mux_map_value);
560
561static const struct snd_kcontrol_new hpr_in_mux_control =
562 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
563
564/* RCV MUX */
565enum {
566 RCV_MUX_OPEN = 0,
567 RCV_MUX_MUTE,
568 RCV_MUX_VOICE_PLAYBACK,
569 RCV_MUX_TEST_MODE,
570 RCV_MUX_MASK = 0x3,
571};
572
573static const char * const rcv_in_mux_map[] = {
574 "Open", "Mute", "Voice Playback", "Test Mode"
575};
576
577static int rcv_in_mux_map_value[] = {
578 RCV_MUX_OPEN,
579 RCV_MUX_MUTE,
580 RCV_MUX_VOICE_PLAYBACK,
581 RCV_MUX_TEST_MODE,
582};
583
584static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
585 SND_SOC_NOPM,
586 0,
587 RCV_MUX_MASK,
588 rcv_in_mux_map,
589 rcv_in_mux_map_value);
590
591static const struct snd_kcontrol_new rcv_in_mux_control =
592 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
593
594/* DAC In MUX */
595static const char * const dac_in_mux_map[] = {
596 "Normal Path", "Sgen"
597};
598
599static int dac_in_mux_map_value[] = {
600 0x0, 0x1,
601};
602
603static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
604 MT6358_AFE_TOP_CON0,
605 DL_SINE_ON_SFT,
606 DL_SINE_ON_MASK,
607 dac_in_mux_map,
608 dac_in_mux_map_value);
609
610static const struct snd_kcontrol_new dac_in_mux_control =
611 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
612
613/* AIF Out MUX */
614static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
615 MT6358_AFE_TOP_CON0,
616 UL_SINE_ON_SFT,
617 UL_SINE_ON_MASK,
618 dac_in_mux_map,
619 dac_in_mux_map_value);
620
621static const struct snd_kcontrol_new aif_out_mux_control =
622 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
623
624/* Mic Type MUX */
625enum {
626 MIC_TYPE_MUX_IDLE = 0,
627 MIC_TYPE_MUX_ACC,
628 MIC_TYPE_MUX_DMIC,
629 MIC_TYPE_MUX_DCC,
630 MIC_TYPE_MUX_DCC_ECM_DIFF,
631 MIC_TYPE_MUX_DCC_ECM_SINGLE,
632 MIC_TYPE_MUX_MASK = 0x7,
633};
634
635#define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
636 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
637 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
638
639static const char * const mic_type_mux_map[] = {
640 "Idle",
641 "ACC",
642 "DMIC",
643 "DCC",
644 "DCC_ECM_DIFF",
645 "DCC_ECM_SINGLE",
646};
647
648static int mic_type_mux_map_value[] = {
649 MIC_TYPE_MUX_IDLE,
650 MIC_TYPE_MUX_ACC,
651 MIC_TYPE_MUX_DMIC,
652 MIC_TYPE_MUX_DCC,
653 MIC_TYPE_MUX_DCC_ECM_DIFF,
654 MIC_TYPE_MUX_DCC_ECM_SINGLE,
655};
656
657static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
658 SND_SOC_NOPM,
659 0,
660 MIC_TYPE_MUX_MASK,
661 mic_type_mux_map,
662 mic_type_mux_map_value);
663
664static const struct snd_kcontrol_new mic_type_mux_control =
665 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
666
667/* ADC L MUX */
668enum {
669 ADC_MUX_IDLE = 0,
670 ADC_MUX_AIN0,
671 ADC_MUX_PREAMPLIFIER,
672 ADC_MUX_IDLE1,
673 ADC_MUX_MASK = 0x3,
674};
675
676static const char * const adc_left_mux_map[] = {
677 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
678};
679
680static int adc_mux_map_value[] = {
681 ADC_MUX_IDLE,
682 ADC_MUX_AIN0,
683 ADC_MUX_PREAMPLIFIER,
684 ADC_MUX_IDLE1,
685};
686
687static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
688 SND_SOC_NOPM,
689 0,
690 ADC_MUX_MASK,
691 adc_left_mux_map,
692 adc_mux_map_value);
693
694static const struct snd_kcontrol_new adc_left_mux_control =
695 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
696
697/* ADC R MUX */
698static const char * const adc_right_mux_map[] = {
699 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
700};
701
702static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
703 SND_SOC_NOPM,
704 0,
705 ADC_MUX_MASK,
706 adc_right_mux_map,
707 adc_mux_map_value);
708
709static const struct snd_kcontrol_new adc_right_mux_control =
710 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
711
712/* PGA L MUX */
713enum {
714 PGA_MUX_NONE = 0,
715 PGA_MUX_AIN0,
716 PGA_MUX_AIN1,
717 PGA_MUX_AIN2,
718 PGA_MUX_MASK = 0x3,
719};
720
721static const char * const pga_mux_map[] = {
722 "None", "AIN0", "AIN1", "AIN2"
723};
724
725static int pga_mux_map_value[] = {
726 PGA_MUX_NONE,
727 PGA_MUX_AIN0,
728 PGA_MUX_AIN1,
729 PGA_MUX_AIN2,
730};
731
732static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
733 SND_SOC_NOPM,
734 0,
735 PGA_MUX_MASK,
736 pga_mux_map,
737 pga_mux_map_value);
738
739static const struct snd_kcontrol_new pga_left_mux_control =
740 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
741
742/* PGA R MUX */
743static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
744 SND_SOC_NOPM,
745 0,
746 PGA_MUX_MASK,
747 pga_mux_map,
748 pga_mux_map_value);
749
750static const struct snd_kcontrol_new pga_right_mux_control =
751 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
752
753static int mt_clksq_event(struct snd_soc_dapm_widget *w,
754 struct snd_kcontrol *kcontrol,
755 int event)
756{
757 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
758 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
759
760 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
761
762 switch (event) {
763 case SND_SOC_DAPM_PRE_PMU:
764 /* audio clk source from internal dcxo */
765 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
766 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
767 0x0);
768 break;
769 default:
770 break;
771 }
772
773 return 0;
774}
775
776static int mt_sgen_event(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol,
778 int event)
779{
780 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
781 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
782
783 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
784
785 switch (event) {
786 case SND_SOC_DAPM_PRE_PMU:
787 /* sdm audio fifo clock power on */
788 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
789 /* scrambler clock on enable */
790 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
791 /* sdm power on */
792 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
793 /* sdm fifo enable */
794 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
795
796 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
797 0xff3f,
798 0x0000);
799 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
800 0xffff,
801 0x0001);
802 break;
803 case SND_SOC_DAPM_POST_PMD:
804 /* DL scrambler disabling sequence */
805 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
806 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
807 break;
808 default:
809 break;
810 }
811
812 return 0;
813}
814
815static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
816 struct snd_kcontrol *kcontrol,
817 int event)
818{
819 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
820 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
821
822 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
823 __func__, event, priv->dl_rate);
824
825 switch (event) {
826 case SND_SOC_DAPM_PRE_PMU:
827 playback_gpio_set(priv);
828
829 /* sdm audio fifo clock power on */
830 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
831 /* scrambler clock on enable */
832 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
833 /* sdm power on */
834 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
835 /* sdm fifo enable */
836 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
837 break;
838 case SND_SOC_DAPM_POST_PMD:
839 /* DL scrambler disabling sequence */
840 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
841 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
842
843 playback_gpio_reset(priv);
844 break;
845 default:
846 break;
847 }
848
849 return 0;
850}
851
852static int mtk_hp_enable(struct mt6358_priv *priv)
853{
854 /* Pull-down HPL/R to AVSS28_AUD */
855 hp_pull_down(priv, true);
856 /* release HP CMFB gate rstb */
857 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
858 0x1 << 6, 0x1 << 6);
859
860 /* Reduce ESD resistance of AU_REFN */
861 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
862
863 /* Set HPR/HPL gain as minimum (~ -40dB) */
864 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
865
866 /* Turn on DA_600K_NCP_VA18 */
867 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
868 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
869 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
870 /* Toggle RG_DIVCKS_CHG */
871 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
872 /* Set NCP soft start mode as default mode: 100us */
873 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
874 /* Enable NCP */
875 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
876 usleep_range(250, 270);
877
878 /* Enable cap-less LDOs (1.5V) */
879 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
880 0x1055, 0x1055);
881 /* Enable NV regulator (-1.2V) */
882 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
883 usleep_range(100, 120);
884
885 /* Disable AUD_ZCD */
886 hp_zcd_disable(priv);
887
888 /* Disable headphone short-circuit protection */
889 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
890
891 /* Enable IBIST */
892 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
893
894 /* Set HP DR bias current optimization, 010: 6uA */
895 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
896 /* Set HP & ZCD bias current optimization */
897 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
898 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
899 /* Set HPP/N STB enhance circuits */
900 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
901
902 /* Enable HP aux output stage */
903 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
904 /* Enable HP aux feedback loop */
905 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
906 /* Enable HP aux CMFB loop */
907 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
908 /* Enable HP driver bias circuits */
909 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
910 /* Enable HP driver core circuits */
911 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
912 /* Short HP main output to HP aux output stage */
913 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
914
915 /* Enable HP main CMFB loop */
916 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
917 /* Disable HP aux CMFB loop */
918 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
919
920 /* Select CMFB resistor bulk to AC mode */
921 /* Selec HS/LO cap size (6.5pF default) */
922 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
923
924 /* Enable HP main output stage */
925 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
926 /* Enable HPR/L main output stage step by step */
927 hp_main_output_ramp(priv, true);
928
929 /* Reduce HP aux feedback loop gain */
930 hp_aux_feedback_loop_gain_ramp(priv, true);
931 /* Disable HP aux feedback loop */
932 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
933
934 /* apply volume setting */
935 headset_volume_ramp(priv,
936 DL_GAIN_N_10DB,
937 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
938
939 /* Disable HP aux output stage */
940 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
941 /* Unshort HP main output to HP aux output stage */
942 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
943 usleep_range(100, 120);
944
945 /* Enable AUD_CLK */
946 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
947 /* Enable Audio DAC */
948 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
949 /* Enable low-noise mode of DAC */
950 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
951 usleep_range(100, 120);
952
953 /* Switch HPL MUX to audio DAC */
954 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
955 /* Switch HPR MUX to audio DAC */
956 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
957
958 /* Disable Pull-down HPL/R to AVSS28_AUD */
959 hp_pull_down(priv, false);
960
961 return 0;
962}
963
964static int mtk_hp_disable(struct mt6358_priv *priv)
965{
966 /* Pull-down HPL/R to AVSS28_AUD */
967 hp_pull_down(priv, true);
968
969 /* HPR/HPL mux to open */
970 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
971 0x0f00, 0x0000);
972
973 /* Disable low-noise mode of DAC */
974 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
975 0x0001, 0x0000);
976
977 /* Disable Audio DAC */
978 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
979 0x000f, 0x0000);
980
981 /* Disable AUD_CLK */
982 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
983
984 /* Short HP main output to HP aux output stage */
985 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
986 /* Enable HP aux output stage */
987 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
988
989 /* decrease HPL/R gain to normal gain step by step */
990 headset_volume_ramp(priv,
991 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
992 DL_GAIN_N_40DB);
993
994 /* Enable HP aux feedback loop */
995 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
996
997 /* Reduce HP aux feedback loop gain */
998 hp_aux_feedback_loop_gain_ramp(priv, false);
999
1000 /* decrease HPR/L main output stage step by step */
1001 hp_main_output_ramp(priv, false);
1002
1003 /* Disable HP main output stage */
1004 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1005
1006 /* Enable HP aux CMFB loop */
1007 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1008
1009 /* Disable HP main CMFB loop */
1010 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1011
1012 /* Unshort HP main output to HP aux output stage */
1013 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1014 0x3 << 6, 0x0);
1015
1016 /* Disable HP driver core circuits */
1017 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1018 0x3 << 4, 0x0);
1019
1020 /* Disable HP driver bias circuits */
1021 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1022 0x3 << 6, 0x0);
1023
1024 /* Disable HP aux CMFB loop */
1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1026
1027 /* Disable HP aux feedback loop */
1028 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1029 0x3 << 4, 0x0);
1030
1031 /* Disable HP aux output stage */
1032 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1033 0x3 << 2, 0x0);
1034
1035 /* Disable IBIST */
1036 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1037 0x1 << 8, 0x1 << 8);
1038
1039 /* Disable NV regulator (-1.2V) */
1040 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1041 /* Disable cap-less LDOs (1.5V) */
1042 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1043 0x1055, 0x0);
1044 /* Disable NCP */
1045 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1046 0x1, 0x1);
1047
1048 /* Increase ESD resistance of AU_REFN */
1049 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1050 0x1 << 14, 0x0);
1051
1052 /* Set HP CMFB gate rstb */
1053 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1054 0x1 << 6, 0x0);
1055 /* disable Pull-down HPL/R to AVSS28_AUD */
1056 hp_pull_down(priv, false);
1057
1058 return 0;
1059}
1060
1061static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1062{
1063 /* Pull-down HPL/R to AVSS28_AUD */
1064 hp_pull_down(priv, true);
1065 /* release HP CMFB gate rstb */
1066 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1067 0x1 << 6, 0x1 << 6);
1068
1069 /* Reduce ESD resistance of AU_REFN */
1070 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1071
1072 /* Set HPR/HPL gain to -10dB */
1073 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1074
1075 /* Turn on DA_600K_NCP_VA18 */
1076 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1077 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1078 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1079 /* Toggle RG_DIVCKS_CHG */
1080 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1081 /* Set NCP soft start mode as default mode: 100us */
1082 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1083 /* Enable NCP */
1084 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1085 usleep_range(250, 270);
1086
1087 /* Enable cap-less LDOs (1.5V) */
1088 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1089 0x1055, 0x1055);
1090 /* Enable NV regulator (-1.2V) */
1091 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1092 usleep_range(100, 120);
1093
1094 /* Disable AUD_ZCD */
1095 hp_zcd_disable(priv);
1096
1097 /* Disable headphone short-circuit protection */
1098 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1099
1100 /* Enable IBIST */
1101 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1102
1103 /* Set HP DR bias current optimization, 010: 6uA */
1104 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1105 /* Set HP & ZCD bias current optimization */
1106 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1107 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1108 /* Set HPP/N STB enhance circuits */
1109 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1110
1111 /* Disable Pull-down HPL/R to AVSS28_AUD */
1112 hp_pull_down(priv, false);
1113
1114 /* Enable HP driver bias circuits */
1115 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1116 /* Enable HP driver core circuits */
1117 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1118 /* Enable HP main CMFB loop */
1119 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1120
1121 /* Select CMFB resistor bulk to AC mode */
1122 /* Selec HS/LO cap size (6.5pF default) */
1123 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1124
1125 /* Enable HP main output stage */
1126 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1127 /* Enable HPR/L main output stage step by step */
1128 hp_main_output_ramp(priv, true);
1129
1130 /* Set LO gain as minimum (~ -40dB) */
1131 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1132 /* apply volume setting */
1133 headset_volume_ramp(priv,
1134 DL_GAIN_N_10DB,
1135 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1136
1137 /* Set LO STB enhance circuits */
1138 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1139 /* Enable LO driver bias circuits */
1140 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1141 /* Enable LO driver core circuits */
1142 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1143
1144 /* Set LOL gain to normal gain step by step */
1145 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1146 RG_AUDLOLGAIN_MASK_SFT,
1147 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1148 RG_AUDLOLGAIN_SFT);
1149 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1150 RG_AUDLORGAIN_MASK_SFT,
1151 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1152 RG_AUDLORGAIN_SFT);
1153
1154 /* Enable AUD_CLK */
1155 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1156 /* Enable Audio DAC */
1157 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1158 /* Enable low-noise mode of DAC */
1159 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1160 /* Switch LOL MUX to audio DAC */
1161 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1162 /* Switch HPL/R MUX to Line-out */
1163 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1164
1165 return 0;
1166}
1167
1168static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1169{
1170 /* HPR/HPL mux to open */
1171 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1172 0x0f00, 0x0000);
1173 /* LOL mux to open */
1174 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1175 0x3 << 2, 0x0000);
1176
1177 /* Disable Audio DAC */
1178 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1179 0x000f, 0x0000);
1180
1181 /* Disable AUD_CLK */
1182 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1183
1184 /* decrease HPL/R gain to normal gain step by step */
1185 headset_volume_ramp(priv,
1186 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1187 DL_GAIN_N_40DB);
1188
1189 /* decrease LOL gain to minimum gain step by step */
1190 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1191 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1192
1193 /* decrease HPR/L main output stage step by step */
1194 hp_main_output_ramp(priv, false);
1195
1196 /* Disable HP main output stage */
1197 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1198
1199 /* Short HP main output to HP aux output stage */
1200 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1201 /* Enable HP aux output stage */
1202 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1203
1204 /* Enable HP aux feedback loop */
1205 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1206
1207 /* Reduce HP aux feedback loop gain */
1208 hp_aux_feedback_loop_gain_ramp(priv, false);
1209
1210 /* Disable HP driver core circuits */
1211 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1212 0x3 << 4, 0x0);
1213 /* Disable LO driver core circuits */
1214 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1215 0x1, 0x0);
1216
1217 /* Disable HP driver bias circuits */
1218 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1219 0x3 << 6, 0x0);
1220 /* Disable LO driver bias circuits */
1221 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1222 0x1 << 1, 0x0);
1223
1224 /* Disable HP aux CMFB loop */
1225 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1226 0xff << 8, 0x0000);
1227
1228 /* Disable IBIST */
1229 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1230 0x1 << 8, 0x1 << 8);
1231 /* Disable NV regulator (-1.2V) */
1232 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1233 /* Disable cap-less LDOs (1.5V) */
1234 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1235 /* Disable NCP */
1236 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1237
1238 /* Set HP CMFB gate rstb */
1239 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1240 0x1 << 6, 0x0);
1241 /* disable Pull-down HPL/R to AVSS28_AUD */
1242 hp_pull_down(priv, false);
1243
1244 return 0;
1245}
1246
1247static int mt_hp_event(struct snd_soc_dapm_widget *w,
1248 struct snd_kcontrol *kcontrol,
1249 int event)
1250{
1251 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1252 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1253 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1254 int device = DEVICE_HP;
1255
1256 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1257 __func__,
1258 event,
1259 priv->dev_counter[device],
1260 mux);
1261
1262 switch (event) {
1263 case SND_SOC_DAPM_PRE_PMU:
1264 priv->dev_counter[device]++;
1265 if (priv->dev_counter[device] > 1)
1266 break; /* already enabled, do nothing */
1267 else if (priv->dev_counter[device] <= 0)
1268 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1269 __func__,
1270 priv->dev_counter[device]);
1271
1272 priv->mux_select[MUX_HP_L] = mux;
1273
1274 if (mux == HP_MUX_HP)
1275 mtk_hp_enable(priv);
1276 else if (mux == HP_MUX_HPSPK)
1277 mtk_hp_spk_enable(priv);
1278 break;
1279 case SND_SOC_DAPM_PRE_PMD:
1280 priv->dev_counter[device]--;
1281 if (priv->dev_counter[device] > 0) {
1282 break; /* still being used, don't close */
1283 } else if (priv->dev_counter[device] < 0) {
1284 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1285 __func__,
1286 priv->dev_counter[device]);
1287 priv->dev_counter[device] = 0;
1288 break;
1289 }
1290
1291 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1292 mtk_hp_disable(priv);
1293 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1294 mtk_hp_spk_disable(priv);
1295
1296 priv->mux_select[MUX_HP_L] = mux;
1297 break;
1298 default:
1299 break;
1300 }
1301
1302 return 0;
1303}
1304
1305static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1306 struct snd_kcontrol *kcontrol,
1307 int event)
1308{
1309 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1310 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1311
1312 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1313 __func__,
1314 event,
1315 dapm_kcontrol_get_value(w->kcontrols[0]));
1316
1317 switch (event) {
1318 case SND_SOC_DAPM_PRE_PMU:
1319 /* Reduce ESD resistance of AU_REFN */
1320 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1321
1322 /* Turn on DA_600K_NCP_VA18 */
1323 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1324 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1325 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1326 /* Toggle RG_DIVCKS_CHG */
1327 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1328 /* Set NCP soft start mode as default mode: 100us */
1329 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1330 /* Enable NCP */
1331 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1332 usleep_range(250, 270);
1333
1334 /* Enable cap-less LDOs (1.5V) */
1335 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1336 0x1055, 0x1055);
1337 /* Enable NV regulator (-1.2V) */
1338 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1339 usleep_range(100, 120);
1340
1341 /* Disable AUD_ZCD */
1342 hp_zcd_disable(priv);
1343
1344 /* Disable handset short-circuit protection */
1345 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1346
1347 /* Enable IBIST */
1348 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1349 /* Set HP DR bias current optimization, 010: 6uA */
1350 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1351 /* Set HP & ZCD bias current optimization */
1352 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1353 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1354 /* Set HS STB enhance circuits */
1355 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1356
1357 /* Disable HP main CMFB loop */
1358 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1359 /* Select CMFB resistor bulk to AC mode */
1360 /* Selec HS/LO cap size (6.5pF default) */
1361 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1362
1363 /* Enable HS driver bias circuits */
1364 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1365 /* Enable HS driver core circuits */
1366 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1367
1368 /* Enable AUD_CLK */
1369 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1370 0x1, 0x1);
1371
1372 /* Enable Audio DAC */
1373 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1374 /* Enable low-noise mode of DAC */
1375 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1376 /* Switch HS MUX to audio DAC */
1377 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1378 break;
1379 case SND_SOC_DAPM_PRE_PMD:
1380 /* HS mux to open */
1381 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1382 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1383 RCV_MUX_OPEN);
1384
1385 /* Disable Audio DAC */
1386 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1387 0x000f, 0x0000);
1388
1389 /* Disable AUD_CLK */
1390 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1391 0x1, 0x0);
1392
1393 /* decrease HS gain to minimum gain step by step */
1394 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1395
1396 /* Disable HS driver core circuits */
1397 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1398 0x1, 0x0);
1399
1400 /* Disable HS driver bias circuits */
1401 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1402 0x1 << 1, 0x0000);
1403
1404 /* Disable HP aux CMFB loop */
1405 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1406 0xff << 8, 0x0);
1407
1408 /* Enable HP main CMFB Switch */
1409 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1410 0xff << 8, 0x2 << 8);
1411
1412 /* Disable IBIST */
1413 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1414 0x1 << 8, 0x1 << 8);
1415
1416 /* Disable NV regulator (-1.2V) */
1417 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1418 0x1, 0x0);
1419 /* Disable cap-less LDOs (1.5V) */
1420 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1421 0x1055, 0x0);
1422 /* Disable NCP */
1423 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1424 0x1, 0x1);
1425 break;
1426 default:
1427 break;
1428 }
1429
1430 return 0;
1431}
1432
1433static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1434 struct snd_kcontrol *kcontrol,
1435 int event)
1436{
1437 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1438 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1439
1440 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1441 __func__, event, priv->ul_rate);
1442
1443 switch (event) {
1444 case SND_SOC_DAPM_PRE_PMU:
1445 capture_gpio_set(priv);
1446 break;
1447 case SND_SOC_DAPM_POST_PMD:
1448 capture_gpio_reset(priv);
1449 break;
1450 default:
1451 break;
1452 }
1453
1454 return 0;
1455}
1456
1457static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1458 struct snd_kcontrol *kcontrol,
1459 int event)
1460{
1461 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1462 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1463
1464 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1465 __func__, event);
1466
1467 switch (event) {
1468 case SND_SOC_DAPM_PRE_PMU:
1469 /* Enable audio ADC CLKGEN */
1470 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1471 0x1 << 5, 0x1 << 5);
1472 /* ADC CLK from CLKGEN (13MHz) */
1473 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1474 0x0000);
1475 /* Enable LCLDO_ENC 1P8V */
1476 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1477 0x2500, 0x0100);
1478 /* LCLDO_ENC remote sense */
1479 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1480 0x2500, 0x2500);
1481 break;
1482 case SND_SOC_DAPM_POST_PMD:
1483 /* LCLDO_ENC remote sense off */
1484 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1485 0x2500, 0x0100);
1486 /* disable LCLDO_ENC 1P8V */
1487 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1488 0x2500, 0x0000);
1489
1490 /* ADC CLK from CLKGEN (13MHz) */
1491 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1492 /* disable audio ADC CLKGEN */
1493 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1494 0x1 << 5, 0x0 << 5);
1495 break;
1496 default:
1497 break;
1498 }
1499
1500 return 0;
1501}
1502
1503static int mt6358_amic_enable(struct mt6358_priv *priv)
1504{
1505 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1506 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1507 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1508
1509 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1510 __func__, mic_type, mux_pga_l, mux_pga_r);
1511
1512 if (IS_DCC_BASE(mic_type)) {
1513 /* DCC 50k CLK (from 26M) */
1514 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1515 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1516 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1517 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1518 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1519 }
1520
1521 /* mic bias 0 */
1522 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1523 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1524 switch (mic_type) {
1525 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1526 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1527 0xff00, 0x7700);
1528 break;
1529 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1530 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1531 0xff00, 0x1100);
1532 break;
1533 default:
1534 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1535 0xff00, 0x0000);
1536 break;
1537 }
1538 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1539 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1540 0xff, 0x21);
1541 }
1542
1543 /* mic bias 1 */
1544 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1545 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1546 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1547 regmap_write(priv->regmap,
1548 MT6358_AUDENC_ANA_CON10, 0x0161);
1549 else
1550 regmap_write(priv->regmap,
1551 MT6358_AUDENC_ANA_CON10, 0x0061);
1552 }
1553
1554 if (IS_DCC_BASE(mic_type)) {
1555 /* Audio L/R preamplifier DCC precharge */
1556 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1557 0xf8ff, 0x0004);
1558 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1559 0xf8ff, 0x0004);
1560 } else {
1561 /* reset reg */
1562 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1563 0xf8ff, 0x0000);
1564 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1565 0xf8ff, 0x0000);
1566 }
1567
1568 if (mux_pga_l != PGA_MUX_NONE) {
1569 /* L preamplifier input sel */
1570 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1571 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1572 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1573
1574 /* L preamplifier enable */
1575 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1576 RG_AUDPREAMPLON_MASK_SFT,
1577 0x1 << RG_AUDPREAMPLON_SFT);
1578
1579 if (IS_DCC_BASE(mic_type)) {
1580 /* L preamplifier DCCEN */
1581 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1582 RG_AUDPREAMPLDCCEN_MASK_SFT,
1583 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1584 }
1585
1586 /* L ADC input sel : L PGA. Enable audio L ADC */
1587 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1588 RG_AUDADCLINPUTSEL_MASK_SFT,
1589 ADC_MUX_PREAMPLIFIER <<
1590 RG_AUDADCLINPUTSEL_SFT);
1591 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1592 RG_AUDADCLPWRUP_MASK_SFT,
1593 0x1 << RG_AUDADCLPWRUP_SFT);
1594 }
1595
1596 if (mux_pga_r != PGA_MUX_NONE) {
1597 /* R preamplifier input sel */
1598 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1599 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1600 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1601
1602 /* R preamplifier enable */
1603 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1604 RG_AUDPREAMPRON_MASK_SFT,
1605 0x1 << RG_AUDPREAMPRON_SFT);
1606
1607 if (IS_DCC_BASE(mic_type)) {
1608 /* R preamplifier DCCEN */
1609 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1610 RG_AUDPREAMPRDCCEN_MASK_SFT,
1611 0x1 << RG_AUDPREAMPRDCCEN_SFT);
1612 }
1613
1614 /* R ADC input sel : R PGA. Enable audio R ADC */
1615 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1616 RG_AUDADCRINPUTSEL_MASK_SFT,
1617 ADC_MUX_PREAMPLIFIER <<
1618 RG_AUDADCRINPUTSEL_SFT);
1619 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1620 RG_AUDADCRPWRUP_MASK_SFT,
1621 0x1 << RG_AUDADCRPWRUP_SFT);
1622 }
1623
1624 if (IS_DCC_BASE(mic_type)) {
1625 usleep_range(100, 150);
1626 /* Audio L preamplifier DCC precharge off */
1627 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1628 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1629 /* Audio R preamplifier DCC precharge off */
1630 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1631 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1632
1633 /* Short body to ground in PGA */
1634 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1635 0x1 << 12, 0x0);
1636 }
1637
1638 /* here to set digital part */
1639 mt6358_mtkaif_tx_enable(priv);
1640
1641 /* UL dmic setting off */
1642 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1643
1644 /* UL turn on */
1645 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1646
1647 return 0;
1648}
1649
1650static void mt6358_amic_disable(struct mt6358_priv *priv)
1651{
1652 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1653 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1654 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1655
1656 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1657 __func__, mic_type, mux_pga_l, mux_pga_r);
1658
1659 /* UL turn off */
1660 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1661 0x0001, 0x0000);
1662
1663 /* disable aud_pad TX fifos */
1664 mt6358_mtkaif_tx_disable(priv);
1665
1666 /* L ADC input sel : off, disable L ADC */
1667 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1668 0xf000, 0x0000);
1669 /* L preamplifier DCCEN */
1670 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1671 0x1 << 1, 0x0);
1672 /* L preamplifier input sel : off, L PGA 0 dB gain */
1673 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1674 0xfffb, 0x0000);
1675
1676 /* disable L preamplifier DCC precharge */
1677 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1678 0x1 << 2, 0x0);
1679
1680 /* R ADC input sel : off, disable R ADC */
1681 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1682 0xf000, 0x0000);
1683 /* R preamplifier DCCEN */
1684 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1685 0x1 << 1, 0x0);
1686 /* R preamplifier input sel : off, R PGA 0 dB gain */
1687 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1688 0x0ffb, 0x0000);
1689
1690 /* disable R preamplifier DCC precharge */
1691 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1692 0x1 << 2, 0x0);
1693
1694 /* mic bias */
1695 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1696 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1697
1698 /* Disable MICBIAS1 */
1699 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1700 0x0001, 0x0000);
1701
1702 if (IS_DCC_BASE(mic_type)) {
1703 /* dcclk_gen_on=1'b0 */
1704 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1705 /* dcclk_pdn=1'b1 */
1706 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1707 /* dcclk_ref_ck_sel=2'b00 */
1708 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1709 /* dcclk_div=11'b00100000011 */
1710 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1711 }
1712}
1713
1714static int mt6358_dmic_enable(struct mt6358_priv *priv)
1715{
1716 dev_info(priv->dev, "%s()\n", __func__);
1717
1718 /* mic bias */
1719 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1720 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1721
1722 /* RG_BANDGAPGEN=1'b0 */
1723 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1724 0x1 << 12, 0x0);
1725
1726 /* DMIC enable */
1727 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1728
1729 /* here to set digital part */
1730 mt6358_mtkaif_tx_enable(priv);
1731
1732 /* UL dmic setting */
1733 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1734
1735 /* UL turn on */
1736 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1737
1738 /* Prevent pop noise form dmic hw */
1739 msleep(100);
1740
1741 return 0;
1742}
1743
1744static void mt6358_dmic_disable(struct mt6358_priv *priv)
1745{
1746 dev_info(priv->dev, "%s()\n", __func__);
1747
1748 /* UL turn off */
1749 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1750 0x0003, 0x0000);
1751
1752 /* disable aud_pad TX fifos */
1753 mt6358_mtkaif_tx_disable(priv);
1754
1755 /* DMIC disable */
1756 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1757
1758 /* mic bias */
1759 /* MISBIAS0 = 1P7V */
1760 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1761
1762 /* RG_BANDGAPGEN=1'b0 */
1763 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1764 0x1 << 12, 0x0);
1765
1766 /* MICBIA0 disable */
1767 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1768}
1769
1770static void mt6358_restore_pga(struct mt6358_priv *priv)
1771{
1772 unsigned int gain_l, gain_r;
1773
1774 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1775 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1776
1777 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1778 RG_AUDPREAMPLGAIN_MASK_SFT,
1779 gain_l << RG_AUDPREAMPLGAIN_SFT);
1780 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1781 RG_AUDPREAMPRGAIN_MASK_SFT,
1782 gain_r << RG_AUDPREAMPRGAIN_SFT);
1783}
1784
1785static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1786 struct snd_kcontrol *kcontrol,
1787 int event)
1788{
1789 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1790 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1791 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1792
1793 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1794 __func__, event, mux);
1795
1796 switch (event) {
1797 case SND_SOC_DAPM_WILL_PMU:
1798 priv->mux_select[MUX_MIC_TYPE] = mux;
1799 break;
1800 case SND_SOC_DAPM_PRE_PMU:
1801 switch (mux) {
1802 case MIC_TYPE_MUX_DMIC:
1803 mt6358_dmic_enable(priv);
1804 break;
1805 default:
1806 mt6358_amic_enable(priv);
1807 break;
1808 }
1809 mt6358_restore_pga(priv);
1810
1811 break;
1812 case SND_SOC_DAPM_POST_PMD:
1813 switch (priv->mux_select[MUX_MIC_TYPE]) {
1814 case MIC_TYPE_MUX_DMIC:
1815 mt6358_dmic_disable(priv);
1816 break;
1817 default:
1818 mt6358_amic_disable(priv);
1819 break;
1820 }
1821
1822 priv->mux_select[MUX_MIC_TYPE] = mux;
1823 break;
1824 default:
1825 break;
1826 }
1827
1828 return 0;
1829}
1830
1831static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1832 struct snd_kcontrol *kcontrol,
1833 int event)
1834{
1835 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1836 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1837 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1838
1839 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1840 __func__, event, mux);
1841
1842 priv->mux_select[MUX_ADC_L] = mux;
1843
1844 return 0;
1845}
1846
1847static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1848 struct snd_kcontrol *kcontrol,
1849 int event)
1850{
1851 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1852 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1853 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1854
1855 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1856 __func__, event, mux);
1857
1858 priv->mux_select[MUX_ADC_R] = mux;
1859
1860 return 0;
1861}
1862
1863static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1864 struct snd_kcontrol *kcontrol,
1865 int event)
1866{
1867 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1868 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1869 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1870
1871 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1872 __func__, event, mux);
1873
1874 priv->mux_select[MUX_PGA_L] = mux;
1875
1876 return 0;
1877}
1878
1879static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1880 struct snd_kcontrol *kcontrol,
1881 int event)
1882{
1883 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1884 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1885 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1886
1887 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1888 __func__, event, mux);
1889
1890 priv->mux_select[MUX_PGA_R] = mux;
1891
1892 return 0;
1893}
1894
1895static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1896 struct snd_kcontrol *kcontrol,
1897 int event)
1898{
1899 switch (event) {
1900 case SND_SOC_DAPM_POST_PMU:
1901 usleep_range(250, 270);
1902 break;
1903 case SND_SOC_DAPM_PRE_PMD:
1904 usleep_range(250, 270);
1905 break;
1906 default:
1907 break;
1908 }
1909
1910 return 0;
1911}
1912
1913/* DAPM Widgets */
1914static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
1915 /* Global Supply*/
1916 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1917 MT6358_DCXO_CW14,
1918 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1919 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1920 MT6358_AUDDEC_ANA_CON13,
1921 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1922 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1923 MT6358_AUDENC_ANA_CON6,
1924 RG_CLKSQ_EN_SFT, 0,
1925 mt_clksq_event,
1926 SND_SOC_DAPM_PRE_PMU),
1927 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1928 MT6358_AUD_TOP_CKPDN_CON0,
1929 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1930 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1931 MT6358_AUD_TOP_CKPDN_CON0,
1932 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1933 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1934 MT6358_AUD_TOP_CKPDN_CON0,
1935 RG_AUD_CK_PDN_SFT, 1,
1936 mt_delay_250_event,
1937 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1938 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1939 MT6358_AUD_TOP_CKPDN_CON0,
1940 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1941
1942 /* Digital Clock */
1943 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1944 MT6358_AUDIO_TOP_CON0,
1945 PDN_AFE_CTL_SFT, 1,
1946 mt_delay_250_event,
1947 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1948 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1949 MT6358_AUDIO_TOP_CON0,
1950 PDN_DAC_CTL_SFT, 1, NULL, 0),
1951 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1952 MT6358_AUDIO_TOP_CON0,
1953 PDN_ADC_CTL_SFT, 1, NULL, 0),
1954 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1955 MT6358_AUDIO_TOP_CON0,
1956 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1957 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1958 MT6358_AUDIO_TOP_CON0,
1959 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1960 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
1961 MT6358_AUDIO_TOP_CON0,
1962 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1963 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
1964 MT6358_AUDIO_TOP_CON0,
1965 PDN_RESERVED_SFT, 1, NULL, 0),
1966
1967 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1968 0, 0, NULL, 0),
1969
1970 /* AFE ON */
1971 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
1972 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
1973 NULL, 0),
1974
1975 /* AIF Rx*/
1976 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1977 MT6358_AFE_DL_SRC2_CON0_L,
1978 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
1979 mt_aif_in_event,
1980 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1981
1982 /* DL Supply */
1983 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1984 0, 0, NULL, 0),
1985
1986 /* DAC */
1987 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1988
1989 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
1990
1991 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
1992
1993 /* LOL */
1994 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1995
1996 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
1997 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
1998
1999 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
2000 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2001
2002 /* Headphone */
2003 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2004 &hpl_in_mux_control,
2005 mt_hp_event,
2006 SND_SOC_DAPM_PRE_PMU |
2007 SND_SOC_DAPM_PRE_PMD),
2008
2009 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2010 &hpr_in_mux_control,
2011 mt_hp_event,
2012 SND_SOC_DAPM_PRE_PMU |
2013 SND_SOC_DAPM_PRE_PMD),
2014
2015 /* Receiver */
2016 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2017 &rcv_in_mux_control,
2018 mt_rcv_event,
2019 SND_SOC_DAPM_PRE_PMU |
2020 SND_SOC_DAPM_PRE_PMD),
2021
2022 /* Outputs */
2023 SND_SOC_DAPM_OUTPUT("Receiver"),
2024 SND_SOC_DAPM_OUTPUT("Headphone L"),
2025 SND_SOC_DAPM_OUTPUT("Headphone R"),
2026 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2027 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2028 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2029 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2030
2031 /* SGEN */
2032 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2033 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2034 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2035 SGEN_MUTE_SW_CTL_SFT, 1,
2036 mt_sgen_event,
2037 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2038 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2039 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2040
2041 SND_SOC_DAPM_INPUT("SGEN DL"),
2042
2043 /* Uplinks */
2044 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2045 SND_SOC_NOPM, 0, 0,
2046 mt_aif_out_event,
2047 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2048
2049 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2050 SND_SOC_NOPM, 0, 0,
2051 mt_adc_supply_event,
2052 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2053
2054 /* Uplinks MUX */
2055 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2056 &aif_out_mux_control),
2057
2058 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2059 &mic_type_mux_control,
2060 mt_mic_type_event,
2061 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2062 SND_SOC_DAPM_WILL_PMU),
2063
2064 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2065 &adc_left_mux_control,
2066 mt_adc_l_event,
2067 SND_SOC_DAPM_WILL_PMU),
2068 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2069 &adc_right_mux_control,
2070 mt_adc_r_event,
2071 SND_SOC_DAPM_WILL_PMU),
2072
2073 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2074 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2075
2076 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2077 &pga_left_mux_control,
2078 mt_pga_left_event,
2079 SND_SOC_DAPM_WILL_PMU),
2080 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2081 &pga_right_mux_control,
2082 mt_pga_right_event,
2083 SND_SOC_DAPM_WILL_PMU),
2084
2085 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2086 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2087
2088 /* UL input */
2089 SND_SOC_DAPM_INPUT("AIN0"),
2090 SND_SOC_DAPM_INPUT("AIN1"),
2091 SND_SOC_DAPM_INPUT("AIN2"),
2092};
2093
2094static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2095 /* Capture */
2096 {"AIF1TX", NULL, "AIF Out Mux"},
2097 {"AIF1TX", NULL, "CLK_BUF"},
2098 {"AIF1TX", NULL, "AUDGLB"},
2099 {"AIF1TX", NULL, "CLKSQ Audio"},
2100
2101 {"AIF1TX", NULL, "AUD_CK"},
2102 {"AIF1TX", NULL, "AUDIF_CK"},
2103
2104 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2105 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2106 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2107 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2108 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2109
2110 {"AIF1TX", NULL, "AFE_ON"},
2111
2112 {"AIF Out Mux", NULL, "Mic Type Mux"},
2113
2114 {"Mic Type Mux", "ACC", "ADC L"},
2115 {"Mic Type Mux", "ACC", "ADC R"},
2116 {"Mic Type Mux", "DCC", "ADC L"},
2117 {"Mic Type Mux", "DCC", "ADC R"},
2118 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2119 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2120 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2121 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2122 {"Mic Type Mux", "DMIC", "AIN0"},
2123 {"Mic Type Mux", "DMIC", "AIN2"},
2124
2125 {"ADC L", NULL, "ADC L Mux"},
2126 {"ADC L", NULL, "ADC Supply"},
2127 {"ADC R", NULL, "ADC R Mux"},
2128 {"ADC R", NULL, "ADC Supply"},
2129
2130 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2131
2132 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2133
2134 {"PGA L", NULL, "PGA L Mux"},
2135 {"PGA R", NULL, "PGA R Mux"},
2136
2137 {"PGA L Mux", "AIN0", "AIN0"},
2138 {"PGA L Mux", "AIN1", "AIN1"},
2139 {"PGA L Mux", "AIN2", "AIN2"},
2140
2141 {"PGA R Mux", "AIN0", "AIN0"},
2142 {"PGA R Mux", "AIN1", "AIN1"},
2143 {"PGA R Mux", "AIN2", "AIN2"},
2144
2145 /* DL Supply */
2146 {"DL Power Supply", NULL, "CLK_BUF"},
2147 {"DL Power Supply", NULL, "AUDGLB"},
2148 {"DL Power Supply", NULL, "CLKSQ Audio"},
2149
2150 {"DL Power Supply", NULL, "AUDNCP_CK"},
2151 {"DL Power Supply", NULL, "ZCD13M_CK"},
2152 {"DL Power Supply", NULL, "AUD_CK"},
2153 {"DL Power Supply", NULL, "AUDIF_CK"},
2154
2155 /* DL Digital Supply */
2156 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2157 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2158 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2159
2160 {"DL Digital Clock", NULL, "AFE_ON"},
2161
2162 {"AIF_RX", NULL, "DL Digital Clock"},
2163
2164 /* DL Path */
2165 {"DAC In Mux", "Normal Path", "AIF_RX"},
2166
2167 {"DAC In Mux", "Sgen", "SGEN DL"},
2168 {"SGEN DL", NULL, "SGEN DL SRC"},
2169 {"SGEN DL", NULL, "SGEN MUTE"},
2170 {"SGEN DL", NULL, "SGEN DL Enable"},
2171 {"SGEN DL", NULL, "DL Digital Clock"},
2172 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2173
2174 {"DACL", NULL, "DAC In Mux"},
2175 {"DACL", NULL, "DL Power Supply"},
2176
2177 {"DACR", NULL, "DAC In Mux"},
2178 {"DACR", NULL, "DL Power Supply"},
2179
2180 /* Lineout Path */
2181 {"LOL Mux", "Playback", "DACL"},
2182
2183 {"LOL Buffer", NULL, "LOL Mux"},
2184 {"LOL Buffer", NULL, "LO Stability Enh"},
2185
2186 {"LINEOUT L", NULL, "LOL Buffer"},
2187
2188 /* Headphone Path */
2189 {"HPL Mux", "Audio Playback", "DACL"},
2190 {"HPR Mux", "Audio Playback", "DACR"},
2191 {"HPL Mux", "HP Impedance", "DACL"},
2192 {"HPR Mux", "HP Impedance", "DACR"},
2193 {"HPL Mux", "LoudSPK Playback", "DACL"},
2194 {"HPR Mux", "LoudSPK Playback", "DACR"},
2195
2196 {"Headphone L", NULL, "HPL Mux"},
2197 {"Headphone R", NULL, "HPR Mux"},
2198 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2199 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2200 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2201
2202 /* Receiver Path */
2203 {"RCV Mux", "Voice Playback", "DACL"},
2204 {"Receiver", NULL, "RCV Mux"},
2205};
2206
2207static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2208 struct snd_pcm_hw_params *params,
2209 struct snd_soc_dai *dai)
2210{
2211 struct snd_soc_component *cmpnt = dai->component;
2212 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2213 unsigned int rate = params_rate(params);
2214
2215 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2216 __func__,
2217 substream->stream,
2218 rate,
2219 substream->number);
2220
2221 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2222 priv->dl_rate = rate;
2223 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2224 priv->ul_rate = rate;
2225
2226 return 0;
2227}
2228
2229static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2230 .hw_params = mt6358_codec_dai_hw_params,
2231};
2232
2233#define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2234 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2235 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2236 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2237 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2238 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2239
2240static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2241 {
2242 .name = "mt6358-snd-codec-aif1",
2243 .playback = {
2244 .stream_name = "AIF1 Playback",
2245 .channels_min = 1,
2246 .channels_max = 2,
2247 .rates = SNDRV_PCM_RATE_8000_48000 |
2248 SNDRV_PCM_RATE_96000 |
2249 SNDRV_PCM_RATE_192000,
2250 .formats = MT6358_FORMATS,
2251 },
2252 .capture = {
2253 .stream_name = "AIF1 Capture",
2254 .channels_min = 1,
2255 .channels_max = 2,
2256 .rates = SNDRV_PCM_RATE_8000 |
2257 SNDRV_PCM_RATE_16000 |
2258 SNDRV_PCM_RATE_32000 |
2259 SNDRV_PCM_RATE_48000,
2260 .formats = MT6358_FORMATS,
2261 },
2262 .ops = &mt6358_codec_dai_ops,
2263 },
2264};
2265
2266static void mt6358_codec_init_reg(struct mt6358_priv *priv)
2267{
2268 /* Disable HeadphoneL/HeadphoneR short circuit protection */
2269 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2270 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2271 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2272 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2273 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2274 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2275 /* Disable voice short circuit protection */
2276 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2277 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2278 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2279 /* disable LO buffer left short circuit protection */
2280 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2281 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2282 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2283
2284 /* accdet s/w enable */
2285 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2286 0xFFFF, 0x700E);
2287
2288 /* gpio miso driving set to 4mA */
2289 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2290
2291 /* set gpio */
2292 playback_gpio_reset(priv);
2293 capture_gpio_reset(priv);
2294}
2295
2296static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2297{
2298 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2299 int ret;
2300
2301 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2302
2303 mt6358_codec_init_reg(priv);
2304
2305 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2306 if (IS_ERR(priv->avdd_reg)) {
2307 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2308 return PTR_ERR(priv->avdd_reg);
2309 }
2310
2311 ret = regulator_enable(priv->avdd_reg);
2312 if (ret)
2313 return ret;
2314
2315 return 0;
2316}
2317
2318static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2319 .probe = mt6358_codec_probe,
2320 .controls = mt6358_snd_controls,
2321 .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2322 .dapm_widgets = mt6358_dapm_widgets,
2323 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2324 .dapm_routes = mt6358_dapm_routes,
2325 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2326};
2327
2328static int mt6358_platform_driver_probe(struct platform_device *pdev)
2329{
2330 struct mt6358_priv *priv;
2331 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2332
2333 priv = devm_kzalloc(&pdev->dev,
2334 sizeof(struct mt6358_priv),
2335 GFP_KERNEL);
2336 if (!priv)
2337 return -ENOMEM;
2338
2339 dev_set_drvdata(&pdev->dev, priv);
2340
2341 priv->dev = &pdev->dev;
2342
2343 priv->regmap = mt6397->regmap;
2344 if (IS_ERR(priv->regmap))
2345 return PTR_ERR(priv->regmap);
2346
2347 dev_info(priv->dev, "%s(), dev name %s\n",
2348 __func__, dev_name(&pdev->dev));
2349
2350 return devm_snd_soc_register_component(&pdev->dev,
2351 &mt6358_soc_component_driver,
2352 mt6358_dai_driver,
2353 ARRAY_SIZE(mt6358_dai_driver));
2354}
2355
2356static const struct of_device_id mt6358_of_match[] = {
2357 {.compatible = "mediatek,mt6358-sound",},
2358 {}
2359};
2360MODULE_DEVICE_TABLE(of, mt6358_of_match);
2361
2362static struct platform_driver mt6358_platform_driver = {
2363 .driver = {
2364 .name = "mt6358-sound",
2365 .of_match_table = mt6358_of_match,
2366 },
2367 .probe = mt6358_platform_driver_probe,
2368};
2369
2370module_platform_driver(mt6358_platform_driver)
2371
2372/* Module information */
2373MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2374MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2375MODULE_LICENSE("GPL v2");